EP1018107B1 - Alternating plasma display panel incorporating ionization and method for controlling the panel - Google Patents

Description

The present invention relates to a method for controlling a alternative color display panel incorporating ionization.

This process is particularly applicable to panels with color plasma displaying a large number of halftone and large size (more than one meter diagonal) for television application.

Plasma panels work on the principle of electrical discharge in gases. They have two insulating tiles each carrying at least one network of electrodes, and delimiting between them a space filled with gas. The tiles are joined to each other by so that the electrode arrays are substantially orthogonal, one materializing rows and the other of the columns. Each intersection of electrodes defines a cell to which a gas space corresponds. The ignition of a given cell is carried out by the selection of two crossed electrodes to which we apply, at a given time, appropriate voltages for the potential difference to cause between these electrodes gas discharge and light emission. The cells are arranged in rows and columns.

To obtain a color panel, we apply strips of phosphor materials, corresponding to the colors green, red and blue excitable by ultraviolet radiation and a gas is used which emits ultraviolet during discharge. A barrier system between the bands allows to physically delimit the cells of the panel and to limit the diffusion phenomena from one color to another. A video pixel is composed of a triplet of cells (one red, one green, one blue).

Discharges in a plasma display panel initiate correctly if the gaseous medium in which they occur is ionized. The display panels that are being developed for these television applications are “alternative” plasma panels. In these panels, the electrodes carried by the tiles are isolated from the discharge gas by a dielectric layer, generally made on the basis of magnesia.

A signal is permanently applied to all the lines maintenance formed by a succession of slots, which has the effect of maintain each cell in the state assigned to it during a phase addressing. Addressing which consists of either switching on or off selectively the panel cells is done by set of one or multiple lines and each line is scanned several times during the time display of an image or image cycle.

It turns out that these color plasma display panels, partly due to the nature of the gas mixture, partly due to technology. have difficulty lighting certain cells by law probabilistic. The gaseous mixture of color panels is generally a mixture of neon and xenon at about 10% xenon. This mixture diffuses ionization poorly.

During the addressing phase, some cells do not light up not when they should or take longer to turn on and when during the maintenance phase, ignition does not take place either or takes place randomly or deferred. The displayed image therefore has defects.

Regarding the structure of the panel, the cells are delimited by barriers which have a role of containment, that is to say on the one hand, they are intended to prevent landfills from spreading to neighboring cells which should not be on and on the other hand to avoid the ultraviolet radiation created by a discharge in a given cell neither excites the phosphors of neighboring cells and does not generate lack of color saturation. These containment barriers do not are not conducive to the diffusion of ionization even if their height is less than the spacing between the two slabs and if they extend according to a single network of electrodes.

The nature of the dielectric layer in contact with the mixture gas has the particularity of having a high emission coefficient secondary helping to start the landfill but this effect is not enough to solve this ionization problem.

In alternative plasma display panels monochrome this ionization problem does not arise if you plan everything around the panel in a hidden frame of the observer, cells of conditioning permanently on according to voltage levels and a timeline determined.

Within these cells, continuous discharges are initiated which favor the ionization of all the gas contained in the space delimited by slabs. These conditioning cells are effective even if the panel is large. Keep in mind that in the panels monochrome the gas mixture is usually neon and argon with about 0.2% argon and its role in the diffusion of ionization is important.

The transposition of these conditioning cells, outside the zone useful in an alternating plasma panel, color hardly brings no improvement to this ionization problem.

There are also DC plasma panels in which the electrodes are in contact with the gas mixture see Fig. 1. Each cell is partitioned and the ionization problem is even more crucial. he could only be resolved by placing next to each useful cell 1 visible by the observer a conditioning cell 2 masked from the observer. The ignition of a conditioning cell 2 precedes that of a cell useful 1 neighbor. Usually a conditioning cell is provided for two useful cells. A section of such a panel is presented at the figure 1. The two tiles bear the reference 10a, 10b. Each of them carries a network of useful electrodes 11a, 11b. Each intersection useful electrodes 11a, 11b defines a useful cell 1. Partitions 3 of a part separate two neighboring useful cells 1 and secondly have a function spacer to guarantee proper positioning of the slabs 10a, 10b. Each useful cell 1 is adjacent to a conditioning cell 2. It is separated by a barrier 4 whose height is partially less than the gap between the two tiles 10a, 10b. A conditioning cell 2 is defined by the intersection of one of the electrodes 11a which also serves to define a useful cell 1 and a conditioning electrode 5.

A discharge of conditioning 6 which occurs in conditioning cell 2 and which precedes a useful discharge 7 which occurs in the useful cell 1 on the right. The conditioning discharge 6 is hidden from the observer (diagrammatically by one eye), because the slab 10b facing the observer carries a black network 8 for shield the packaging discharges 6. The discharge of conditioning 6 initiates useful discharge by pre-ionizing the gas mixture contained between the two tiles 10a, 10b.

This structure with conditioning cells requires a network of electrodes and additional electronic circuits. She results in higher power consumption and the provision of more electrical power.

Another disadvantage is that the minimum pitch between two cells useful 1 separated by a conditioning cell 2 is imposed by the size of this packaging cell 2. We lose space.

From the advantages point of view, the packaging discharges being masked from the observer, they do not introduce a background annoying light that reduces contrast.

Another advantage is that the addressing of the cells of conditioning is separated from that of the useful cells which allows not not use time devoted to addressing useful cells to the addressing of conditioning cells. Keep the fact in mind that the greater the number of lines of the panel the greater the time spent at the processing of a line must be small or more the number of lines processed at the same time must be great.

The ionization problem encountered in the panels of alternative color plasma viewing is not as crucial as in panels whose operation is of the continuous type. it does seem no need to introduce packaging cells in the vicinity of every useful cell because of all the technological complications and they induce.

It has been proposed in plasma display panels color alternative, such as those described in patent application EP-A1-0 549,275 in the name of FUJITSU to provide a non-ionization phase selective before each addressing phase. This means that this phase is applied simultaneously to all lines.

Figure 2 shows schematically the treatments applied to all lines of a display panel of this type.

During an image cycle which is the time required for display an image, all the lines are simultaneously ionized, then addressed, then maintained. These three phases of ionization, addressing and maintenance form a cycle and several cycles are repeated during a cycle image. In order to allow the display of halftones, the phases for different cycles have different durations.

This ionization phase consists of various ignitions of all panel cells, alternating ignitions with various extinctions of all the cells in the panel.

The ionization phase is represented with hatching, that is crossed out and the maintenance line is dotted.

Besides the fact that the cycle time is lengthened, these phases ionization create a relatively large luminous background on the screen the contrast between cells on and cells off being around 100.

In alternative plasma display panels in color in which the scans are interlaced, it is not possible to set up this non-selective phase of ionization simultaneously on all lines since, the addressing and maintenance phases are temporally mixed. At a given moment, all the lines are not not treated in the same way.

The present invention provides a method for controlling a alternative color display panel with a phase of preionization compatible with interlaced scans, this process to minimize the background light and to avoid a reduction in the time allocated to addressing.

More specifically, the present invention relates to the method of control of an alternative color display panel defined in claim 1.

The maintenance signal has bearings connected by fronts serving as a transition. Preferably if you don't want to increase the time allocated to addressing, preconditioning registration is carried out by a pulse superimposed on a level, just after a transition, on a when a cell level maintenance discharge would occur registered on this line in the absence of preconditioning registration.

If the time is not critical, it is of course possible to place the preconditioning pulse at another location on the bearing.

To reduce the luminous background provided by this inscription of preconditioning, we arrange for it to come closest possible an erase operation applied to the second set. It is however preferable that the preconditioning registration takes place at minus one maintenance cycle before this erasing operation so as not to disrupt its effects.

A registration operation is also carried out by an impulse superimposed on a bearing, in order to minimize the number of maintenance cycles between the preconditioning registration and the erasure operation, it is possible to give different amplitudes to the pulse of preconditioning and registration impulse.

In order to display halftones, each set is subject to several successive treatments, a treatment consisting of addressing followed by at least one maintenance cycle, each treatment being associated with a control bit whose weight is representative of the duration of the processing.

To simplify the control of the panel, it is possible that the two sets are treated following the other by the same bit.

In order not to increase the light background of the panel too much, it is possible to perform preconditioning registration only during one or a few treatments of the first set, these treatments being preferably associated with least significant bits.

It is advantageous to homogenize the light background that the registered line of the second set changes according to the processing bit of the first set. This change can be done within the same second set of lines, for example by permutation within the lines of the second set.

This change can also be made within several sets of lines.

To further improve the ionization of the panel at the edge of the image, especially if it is large, and without increasing the bottom bright, we can foresee that signals keep lit in permanently at least one additional line of the panel display, located on an edge. This line is hidden from an observer and is only used for this function.

The present invention also relates to the display panel defined in claim 16.

• un générateur de signaux délivrant des signaux des trois types,
• des moyens pour délivrer d'une part chaque signai accompagné d'une identification d'un circuit de commande destinataire et d'autre part chaque signal accompagné d'une identification d'une ou plusieurs sorties à activer de circuit de commande ligne,
• des premiers moyens pour transmettre séquentiellement, à un instant choisi, chaque signal accompagné de l'identification du circuit de commande destinataire vers ledit circuit de commande destinataire,
• des seconds moyens pour transmettre séquentiellement, au même instant choisi, un signal de même type accompagné de l'identification de ladite ou de lesdites sorties à activer vers la ou lesdites sorties à activer de tous les circuits de commande ligne destinataires possédant une ou de telles sorties.

The addressing circuit can include;

• a signal generator delivering signals of the three types,
• means for delivering on the one hand each signal accompanied by an identification of a destination control circuit and on the other hand each signal accompanied by an identification of one or more outputs to be activated from the line control circuit,
• first means for sequentially transmitting, at a selected time, each signal accompanied by the identification of the destination control circuit to said destination control circuit,
• second means for sequentially transmitting, at the same chosen instant, a signal of the same type accompanied by the identification of said one or more outputs to be activated to said one or more outputs to be activated from all the destination line control circuits having one or more such exits.

A line control circuit will then validate the transmission of a signal received from second sequential transmission means to the line corresponding to the output to activate, when it has received at the same time a signal of the same type from the first means of transmission sequential.

• un générateur de signaux délivrant des signaux des trois types,
• des moyens pour délivrer d'une part chaque signal accompagné d'une identification d'un circuit de commande destinataire et d'autre part chaque signal accompagné d'une identification d'une ou plusieurs sorties à activer de circuit de commande ligne,
• des moyens pour transmettre séquentiellement, à un instant choisi, chaque signal accompagné de l'identification du circuit de commande 5 destinataire vers ledit circuit de commande destinataire,
• des moyens pour aiguiller simultanément, par paquets de trois de types différents, les signaux accompagnés de l'identification de ladite ou lesdites sorties à activer vers ladite ou lesdites sorties à activer du circuit de commande destinataire.

According to a variant which saves time, the addressing circuit can comprise:

• a signal generator delivering signals of the three types,
• means for delivering on the one hand each signal accompanied by an identification of a destination control circuit and on the other hand each signal accompanied by an identification of one or more outputs to be activated from the line control circuit,
• means for sequentially transmitting, at a selected time, each signal accompanied by the identification of the destination control circuit 5 to said destination control circuit,
• means for simultaneously routing, by packets of three of different types, the signals accompanied by the identification of said one or more outputs to be activated to said one or more outputs to be activated from the destination control circuit.

A line control circuit will validate the transmission of a signal received on one of its outputs, to the corresponding line, at the selected time where it will receive a signal of the same type from the means of transmission sequential.

• la figure 1 (déjà décrite) : la structure d'un panneau de visualisation à plasma continu ;
• la figure 2 (déjà décrite) : les différents traitements appliqués à un panneau de visualisation alternatif dans lequel toutes les lignes subissent le même traitement en même temps;
• la figure 3a : un chronogramme montrant les instants d'adressage de quelques lignes d'un panneau de visualisation alternatif commandé classiquement avec des balayages entrelacés;
• la figure 3b : le principe des balayages entrelacés;
• la figure 4 : un chronogramme montrant le traitement de quelques lignes d'un panneau de visualisation commandé par le procédé conforme à l'invention ;
• les figures 5a, 5b : deux modes de réalisation d'un panneau de visualisation commandé par le procédé de l'invention ;
• les figures 6a, 6b; des chronogrammes montrant les signaux appliqués aux lignes des deux panneaux de visualisation des figures 5a, 5b

Other characteristics and advantages of the invention will appear on reading the description of the exemplary embodiments illustrated in the appended figures which represent:

• Figure 1 (already described): the structure of a continuous plasma display panel;
• FIG. 2 (already described): the different treatments applied to an alternative display panel in which all the lines undergo the same treatment at the same time;
• FIG. 3a: a timing diagram showing the times of addressing of a few lines of an alternative display panel conventionally controlled with interlaced scans;
• FIG. 3b: the principle of interlaced scans;
• Figure 4: a timing diagram showing the processing of a few lines of a display panel controlled by the method according to the invention;
• Figures 5a, 5b: two embodiments of a display panel controlled by the method of the invention;
• Figures 6a, 6b; timing diagrams showing the signals applied to the lines of the two display panels in FIGS. 5a, 5b

In all the description and the claims the lines and columns of the display panels can be swapped.

FIG. 3a represents a timing diagram showing the instants for addressing the lines of an alternative color display panel conventionally controlled with interlaced scans and susceptible to be controlled by the method according to the invention.

A maintenance signal formed of a succession of EN maintenance cycles in time slots. It has the effect of maintaining each cell in the state assigned to it during addressing.

The addressing is done set of lines by set of lines. A set has one or more lines, if the panel is large size each set preferably includes several. In the example describes each set E1, E2, E3 has four lines Y1-Y4, Y5-Y8, Y9-Y12.

Addressing consists in modifying the voltage across the cells to erase or register them. It involves a semi-selective operation consisting for example in extinguishing all the cells of a set followed by a selective operation consisting for example of registering only those to be registered. The selective operation allows differentiate the different cells of a line to act only on certain between them. In the following we assume that the erasure is semi-selective and selective registration. It is also possible that the deletion is selective and semi-selective registration.

The operation of erasing lines Y1-Y4 from a set E1 consists of superimposing an impulse lE on the maintenance slots EN that receives this set E1. The operation of registering certain cells of a line Y2 consists of superimposing a pulse 112 on the slots of maintenance EN that this line Y2 receives but also to apply on columns corresponding to the cells of the row not to be entered, pulses and nothing on the columns corresponding to the cells in front be registered. We can then differentiate the different cells of the line.

An IM2 pulse on an X1 column masks the voltage II2, applied to line Y2 for the cell located at the intersection of the row Y2 and column X1 and the cell remains off.

In Figure 3a we can notice that since the lines are treated four by four, an EN niche maintenance cycle has a relatively short low level bp followed by a longer high level ph. A transition f separates two successive high and low landings.

The erase pulse lE takes place during a low plateau pb it is unique for all lines Y1, Y2, Y3, Y4 of the addressed set.

On the other hand, during the next high ph level, several pulses II1, II2, II3, II4 aimed at registration are generated successively, the first II1 is applied on line Y1, the second II2 is applied on line Y2 etc ... We find the same impulses II5 to II12 aiming at the inscription on lines Y5 to Y12. The erase impulse could take place on a landing high and the pulses contributing to the inscription on the low bearings.

These impulses aimed at enrollment combine with those received in synchronism by the columns. We assume in the example of the Figure 3a that only the cell located at the intersection of line Y1 and column X1 will be entered. Those located at the intersection of column X1 and lines Y2 to Y12 will be off, they receive IM2 pulses at IM12 at column X1 in synchronism with pulses II2 to III2.

We can also notice that it is planned between the beginning of the landing high ph and the first pulse II1 aimed at registration, an interval of free time t, During this free time interval t no addressing is fact. The duration of this free time interval t corresponds approximately to that an impulse aimed at registration. This free time t represents the time necessary for establishing cell maintenance discharges inscribed from the panel belonging to another set than the one addressed. Maintenance discharges occur at the end of a transition f leading at an extreme high ph or low pb level.

We don't take the risk of applying an impulse to a column during this time interval t, this pulse would disrupt all the cells of this column which are, at this moment maintained.

Figure 3b shows schematically on a timing diagram the known principle of interlaced scans used to obtain halftone.

It is assumed, in the example described, that the panel has eight lines. that it displays eight halftone 2 ³ and that a line set has only one line. To display these halftones, each of the lines must be processed three times during the image cycle, each processing starting with an addressing which takes place at correctly chosen instants. These different treatments starting with addressing make it possible to modulate the duration of lighting of the panel cells. To display a complete image, 24 treatments starting with addressing will be required. They are numbered in the diagram from 1 to 24.

For a set of lines, each treatment starting with a addressing is associated with a control bit whose weight is representative the duration of ignition of the cells lit by this addressing.

In the example described, 3 bits B0, B1, B2 are used. We have represented the addressing operations as punctual without separating the deletion of the registration.

The addressing time of a cell is the same for all the bits whatever their weight, what changes is the duration of treatment is say the duration of keeping the cell on or off. So the treatment by bit B0 lasts T / 7, processing by bit B1 lasts 2T / 7 and processing by bit B2 lasts 4T / 7. Recall that T represents the duration of a cycle image.

A sequencing algorithm makes it possible to address all lines 3 times, respecting between two successive addresses of the same line the weight of the bit concerned.

So while the first line is processed by bit B0, the eighth line is processed by bit B1, then the sixth line by bit B2 then the second line by bit B0.

Note that the same time interval T separates two successive addressing of two sets of lines processed by the same bit, whatever the bit weight.

Let tad be the time interval between two addresses successive of two sets of lines by different bits, the interval of time τ = ntad with n equal to the number of bits used for halftones.

We now refer to Figure 4 which similarly shows so that in FIG. 3a, the processing of several lines by the method according to the invention. Now a set E1, E2, E3, ... Em of lines has two lines and the four sets E1, E2, E3, ... Em shown correspond to eight lines Y1 to Y6, Yn-1, Yn.

After a semi-selective operation relating to the first set E1 of lines, we carry out a preconditioning inscription JP of cells of at least one row Y3 of the second set E2, whatever the state cells of line Y3. This IP preconditioning registration takes place out of an address time of the second set and out of the operation which follows the semi-selective operation of the first set E1.

This IP preconditioning registration performs ionization of the panel and improves the response time of the panel cells during a registration or an interview.

In the example described, the IP preconditioning registration of the line Y3 takes place during the processing relating to bit B1 of the first set E1.

The second set E2 is close to the first and it is processed just after the first E1 for the same bit B1 which means that the range of time τ 'during which the IP preconditioning registration can take is the same whatever the bit weight; which is simple to set up artwork. It is of course possible to enter a line from any other set of lines.

The Y3 line preconditioning registration is initialized by a preconditioning pulse which is superimposed on EN maintenance slots received by this line Y3. For the sake of clarity the preconditioning pulse carries the IP reference because it is it which is visible in the figure. The same is true for the erase pulses and registration when addressing. This IP preconditioning pulse has an appropriate amplitude. By placing the preconditioning pulse IP during a free interval t at the start of the high plateau ph of the signal maintenance, we are sure not to disturb the condition of other cells lines since no other registration is initialized at this time. In fact, the position of this preconditioning pulse IP during a free interval t at the beginning of the upper plateau ph is that which allows a secure registration of the entire line without changing the time allocated for addressing. If the addressing time is not critical, it is possible to locate the impulse at another place in the upper bearing ph.

An IP preconditioning registration can also be found on lines Y4, Y5, Y6 at appropriate times. On line Y5, the inscription IP preconditioning takes place at the end of the plateau.

However, if a large number of lines participate in the ionization, we may have a strong bright background, which is annoying. If more always the same lines which participate in the ionization, the luminous background will be not very homogeneous because these lines contributing to the ionization will appear highlighted.

To reduce this luminous background and improve its homogeneity, several solutions are possible. They can be used separately or in combination, everything depends in particular on the size of the panel, the number of lines per set, the number of bits, the quality of the dielectric layer.

One of the solutions to reduce the light background is to only carry out this preconditioning inscription only for a single bit of halftone or some of them, preferably for those of low weight because the ionization defects are no longer present on cells treated with bits affected by these weights. Under these conditions, the duration of ignition of the line contributing to ionization since the duration of the ignition of preconditioning is directly proportional to the number of bits affected by preconditioning. In Figure 4, no inscription of preconditioning is not carried out during the processing relating to bit B3 of the set E1 of lines.

Another solution to reduce the background light is to start registration of preconditioning as late as possible. Free described in Figure 4, between the erasure of the lines of the set E1 and the erasure of the lines of the E2 assembly, three maintenance cycles elapse EN and we therefore have three successive high levels ph1, ph2, ph3 for welcome the IP pulse initializing the preconditioning registration of the line Y3. To reduce the ignition time of line Y3, it would be possible to place this IP pulse on the third high level ph3, the one closest to the erase pulse IE of the lines in the second set E2.

However, it is more prudent not to place the IP pulse of preconditioning of line Y3 at the start of this last high plateau ph3 if we do not want to risk disturbing the erasure of certain cells of this line Y3.

When we generate a registration pulse, we exchange loads between the two facing tiles, when performing a discharge maintenance there is also an exchange of charges between the two slabs but the number of charges put into play during registration is different from that put involved during the interview. An effective erasure can only take place if it follows at least one maintenance cycle to stabilize discharges. In our example it is best to place the IP preconditioning pulse on the penultimate high level ph2. The choice of the IP pulse position of preconditioning is restricted in the example but in the panels displaying a large number of halftones the choice is much wider.

One way to minimize the number of maintenance cycles between pre-conditioning registration and deletion consists, for example, in adapt the amplitude of the preconditioning pulse by giving it a voltage value different from that of the selective enrollment pulse.

To make the background light brought by the lighting of lines contributing to more homogeneous ionization, it is possible not to, for a given set E1 of lines, always light the same line of the second set E2.

So in our example in Figure 4, during relative processing at bit B1 of the first set E1, it is line Y3 which contributes to the ionization while during the processing relating to the bit B2 it is the line Y4. A permutation among lines Y3, Y4 of the second set E3 can be performed according to the bit processing the first set E1. So at an even bit B2 processing the first set E1 of lines can correspond to an even line Y4 of the second set E2 of lines and at an odd bit B1 an odd line Y1. A permutation among all the lines of the second set improves appreciably the homogeneity of the light background obtained. Other choices are possible, the main one being to change lines contributing to ionization. The line change can also be done within several sets of lines.

To further improve the ionization of the panel without increase of the light background, we can consider combining this control process with preconditioning inscription with the light on permanence during the operation of the panel, one or more additional lines located outside its useful area, these lines being masked from an observer. We assume that the lines Yc1, Yc2 visible in Figure 5a fall into this category

Or a color display panel using 10 bits to the display of halftones.

If during a picture cycle, the same line of a second together contributes to ionization during all treatments of a first together, if the first and second sets are treated successively by the same bit and if the line contributing to the ionization is lit during the maximum time, it will stay on for 100 maintenance cycles per image cycle. It will be very bright.

If it is only on for a quarter of the maximum time, it will remain on for approximately 25 maintenance cycles per image cycle.

If the second set of lines has four lines and you performs a permutation of the lines of this set contributing to ionization, each of them will only stay on for 6 cycles maintenance by image cycle. The light background will be spread in the second group

If now ionization is not necessary for all bits of the first set but for half of them, each line contributing to ionization will only stay on for 3 cycles maintenance by image cycle. This duration is practically not noticeable to the eye.

The following example shows that the contrast C is good in a display panel controlled by the method according to the invention.

The value of the contrast C is equal to: C = Lup / Luf

Ixb/a avec :

I nombre de lignes du panneau de visualisation,

b nombre de bits utilisés pour l'affichage des demi-teintes,

a nombre d'adressages pendant un cycle d'image,

Lup represents the maximum luminance of the panel and is proportional to:

Ixb / a with:

I number of lines of the display panel,

b number of bits used for displaying halftone,

has number of addresses during an image cycle,

nxbxf/a avec:

n nombre de cycles d'entretien pendant lesquels une ligne contribuant à l'ionisation reste allumée,

f rapport du nombre de bits utilisant cette aide à l'ionisation au nombre de bit total.

Luf represents the luminance of the light background introduced by the lighting of the lines contributing to the ionization and is proportional to:

nxbxf / a with:

n number of maintenance cycles during which a line contributing to ionization remains on,

f ratio of the number of bits using this ionization aid to the total number of bits.

By simplifying we obtain: C = I / nxf

If I = 500, ns ≤ 3 and f = 0, 5 we then obtain a contrast C ≥ 300 which is a very acceptable value, hardly perceptible and in any case much lower than that obtained in the display panels where all the lines are treated simultaneously in the same way, such as that described in Figure 3b.

This contrast value is the result of a compromise between the number of lines of the display panel, the number of bits for which ionization assistance applies and the number of maintenance cycles during which the lines contributing to the ionization are on.

Figures 5a and 5b which are now referred to illustrate two variants of plasma panels implementing the method of addressing command according to the invention.

The plasma panel has a useful screen 10 formed using a network of line or line electrodes Y1 to Y6 crossed with a second array of column or column electrodes X1 to X6.

At each line and column intersection is a cell C1 to C36. In the figures, there are only six rows and six columns but one plasma panel for television application may have more than one 1000 and define more than a million cells.

Each line Y1 to Y6 is connected to an output SY1 to SY6 of a row management device 20, and each column X1 to X6 at an output SX1 to SX6 of a column management device 210.

The function of the column management device 210 is in particular to apply the masking pulses to columns X1 to X6 IM2, IM3 ... applied to certain columns during addressing such as shows figure 3a.

The line management device 20 comprises one or more line 22, 23 control circuits called 'line driver' by specialists of the domain. Each line control circuit has a number of outputs S1, S2, S3, all these outputs forming the outputs of the line management 20. Each of the line control circuits 22, 23 receives in permanent maintenance signal EN issued by one or more generators maintenance 21 and this maintenance signal is transmitted simultaneously on all lines Y1 to Y6 of the display panel.

In the example shown, there are two line control circuits 22, 23 which each have three outputs S1, S2, S3 each connected to a line Y1 at Y3 and Y4 at Y6.

The line management device 20 also includes, cooperating with the maintenance generator 21, an addressing device 200 This addressing device 200 will transmit erasure signals IE, II registration and IP preconditioning registration at the right times, on outputs to activate good line control circuits, these signals superimposed on the EN maintenance signals.

The maintenance generator 21 is in itself conventional and is not not described.

In FIG. 5a, the addressing device 200 operates in mode parallel while in Figure 5b it operates in serial mode.

In FIG. 5a also appear, outside the useful screen 10, two additional lines Yc1, Yc2 which are hidden from an observer. During the operation of the panel they are permanently on to improve ionization at the edge of the image as mentioned previously. They are connected for this purpose to an AC device delivering a conditioning signal.

The addressing device 200 of FIG. Sa comprises a GS signal generator which delivers signals of three types: erase signals IE, write signals II, signals IP preconditioning registration to a GD data generator. The GD data generator delivers each of the signals it receives accompanied by an identification of a line 22, 23 control circuit recipient. The signals it delivers bear the references IEC, IIC, IPC. They arrive on a SEQ sequencer controlled by a control device COM. These IEC, IIC, IPC signals including the identification of a recipient line command transmitted sequentially, each to a selected instant, towards the control circuit 22, 23 destination line.

The GD data generator also delivers to a device selection of active output DS, each of the signals it receives accompanied by an identification of one or more circuit outputs line command to activate. The signals it delivers are referenced IES, IIS, IPS.

The erase signals IE apply simultaneously to several outputs when the addressing is done set of lines by set of lines and that each set of lines has multiple lines, while those of registration II and IP preconditioning apply to a single output.

IES, IIS, IPS signals including the identification of said or said outputs to be activated arrive in parallel mode to an AIG switch and are referred simultaneously, in bundles of three different types, each to said one or more outputs to be activated from the line control circuit recipient. For this, the AIG switch also receives the IEC, IIC, IPC signals. including the identification of the destination line control circuit. This packet transmission of three signals of different types saves time.

A line control circuit 22, 23 validates the transmission of a signal present on one of its outputs, to the corresponding line Y1 to Y6, at the chosen instant when it receives a signal of the same type coming from the SEQ sequencer.

The control circuits 22, 23 can also receive a control circuit 25 for additional signals adapted to their needs.

In Figure 5b, we find the signal generator GS delivering signals of the three types IE, II, IP, the GD data generator delivering signals of the three types including identification of the addressee line command, signals of three types including the identification of the line control circuit output (s) to be activated. There is also the control circuit 25 and the sequencer SEQ which transmits sequentially, at selected times, the signals including the identification of the destination line control circuit to said circuit recipient line command. The difference is in the differentiation of the output (s) to activate line control circuits 22, 23.

IES, IIS, IPS signals including the identification of said or said outputs to be activated arrive on a second sequencer SEQ ' ordered in synchronism with the first SEQ sequencer. The second SEQ 'sequencer transmits sequentially, at the same selected times, signals of the same type as those transmitted by the first sequencer SEQ but including said one or more outputs to activate towards all the circuits of command line 22, 23 having one or such outputs to activate.

A line control circuit 22, 23 validates the transmission of a signal received from the second sequencer SEQ 'to the line corresponding to the output to activate when it has received a signal of the same type at the same time from the first SEQ sequencer.

As an example, the GS signal generator can be produced by a counter, the GD data generator and the selection device DS by memories, the SEQ, SEQ 'by the switches three inputs, one output and the switcher by a multiplexer.

FIGS. 6a, 6b show timing diagrams of the IEC signals, IIC, IPC, IES, IIS, IPS arriving on line control circuits respectively in parallel mode and in serial mode with for each figure shows the signals received on a line.

The advantage of parallel mode is that it saves time for load data into components which is particularly sought when the panel to be ordered has a large number of rows and columns and that it is used for television application.

Claims (20)

1. Method for controlling a colour alternating display panel comprising cells arranged at the crossing of row electrodes and column electrodes, these cells having two states one written and the other extinguished, the rows forming at least two sets (E1, E2, ... Em), each set comprising at least one row (Y1, ..., Yn), the method comprising the following steps:

   application to the rows of a sustain signal (EN) formed of a succession of sustain cycles and generating sustain discharges at the level of the written cells, and

   addressing at appropriate instants of the sets of rows (E1, E2, E3, En), the addressing being performed set of rows by set of rows and comprising a so-called semi-selective operation (IE), acting on all the cells of a set, followed by a so-called selective operation (II), acting on predetermined cells of the set, one of the operations being a write (II) and the other an erase,

      characterized in that after at least one semi-selective operation relating to the first set (E1) it consists in carrying out a preconditioning write (IP) of the cells of at least one row (Y3) of the second set (E2), regardless of the state of the cells of the row (Y3), this preconditioning write (IP) taking place outside an addressing time of the second set (E2) and outside the selective operation which follows the semi-selective operation relating to the first set (E1).
2. Method of controlling a display panel, according to Claim 1, characterized in that the sustain signal comprises porches (pb, ph) linked by transitions (f), and the preconditioning write (IP) is carried out by a pulse superimposed on a porch.
3. Method of controlling a display panel according to Claim 2, characterized in that the preconditioning pulse (IP) takes place just after a transition (f) at an instant at which a sustain discharge should occur at the level of written cells in the absence of any preconditioning pulse (IP).
4. Method of controlling a display panel according to one of Claims 1 to 3, characterized in that the semi-selective and selective operations are the one an erase and the other a write, and the preconditioning write (IP) occurs as close as possible to an erase (IE) of the row (Y3, Y4) of the second set (E2), in such a way as to reduce the time for writing this row.
5. Method of controlling a display panel according to Claim 4, characterized in that the preconditioning write (IP) occurs at least one sustain cycle before the erase (IE) of the row (Y3, Y4) of the second set (E2).
6. Method of controlling a display panel according to one of Claims 1 to 5, characterized in that with a view to displaying an image with half-tones, each set is subjected to several successive processings, a processing consisting in an addressing followed by at least one sustain cycle, each processing being associated with a control bit whose weight is representative of the duration of the processing.
7. Method of controlling a display panel according to Claim 6, characterized in that the two sets are processed successively by the same bit.
8. Method of controlling a display panel according to one of Claims 6 or 7, characterized in that the preconditioning write (IP) is carried out during at least one processing of the first set (E1).
9. Method of controlling a display panel according to Claim 8, characterized in that the processing is associated with a bit of low weight.
10. Method of controlling a display panel according to one of Claims 6 to 9, characterized in that the row of the second set (E2) written by the preconditioning write changes according to the control bit processing the first set (E1).
11. Method of controlling a display panel according to Claim 10, characterized in that the change takes place within the same second set (E2).
12. Method of controlling a display panel according to one of Claims 10 or 11, characterized in that the change consists of a permutation among the rows of the second set (E2).
13. Method of controlling a display panel according to Claim 10, characterized in that the change takes place within several sets of rows (E2, E3).
14. Method of controlling a display panel according to one of Claim 2 or 3, characterized in that the write operation is carried out by a pulse superimposed on a porch, and the pulse carrying out the preconditioning write has a different amplitude from the pulse carrying out the write.
15. Method of controlling a display panel according to one of Claims 1 to 14, characterized in that it consists in keeping one or more additional rows (Y_C1, Y_C2) of the panel permanently written, these rows being masked to an observer.
16. Colour alternating display panel implementing the method according to one of Claims 1 to 15, comprising:

    cells (C1-C36) placed at the crossing of at least one array of row electrodes or rows (Y1-Y6) with at least one array of column electrodes or columns (X1 to X6), the rows forming at least two sets (E1-E2) of at least one row,

    a row management device (20) and a column management device (210) delivering signals to the rows (Y1-Y6) and to the columns (X1-X6), the row management device (20) comprising:

    at least one sustain generator (21) delivering sustain signals (EN) to all the rows by way of at least one row control circuit (22, 23), each row (Y1-Y6) being linked to an output of the row control circuit (22, 23) and

    an addressing device (200) delivering to the rows via an output to be activated of a destination row control circuit, after enabling of the row control circuit, signals (IE, II, IP) of three types which are superimposed on the sustain signals among which: erase signals (IE) and write signals (II), these signals forming the one a so-called semi-selective operation, acting on all the cells of a set, the other a so-called selective operation, acting on predetermined cells of the set, an addressing consisting in a semi-selective operation (IE) followed by a selective operation (II), the signals (II, IE) corresponding to an addressing being delivered to the rows of the sets, set by set, and preconditioning write signals (IP)

    characterized in that:
    the addressing device (200), after a semi-selective operation relating to the first set (E1) delivers these preconditioning write signals (JP) to the cells of at least one row of the second set, regardless of the state of the cells of the row and doing so outside the addressing time of the second set and outside the selective operation of the first set.
17. Display panel according to Claim 16, characterized in that the addressing device (200) comprises:

    a signals generator (GS) delivering signals (IE, II, IP) of the three types,

    means (GD) for delivering on the one hand each signal accompanied by an identification of a destination row control circuit (IEC, IIC, IPC) and on the other hand each signal accompanied by the identification of one or more outputs to be activated of a row control circuit (IES, IIS, IPS),

    means (SEQ) for sequentially transmitting, at a chosen instant, each signal accompanied by the identification of the destination control circuit (IEC, TIC, IPC) to the said destination row control circuit (22, 23),

    means (AIG) for simultaneously routing, in packets of three, of different types, the signals accompanied by the identification of the said output or outputs to be activated (IES, IIS, IPS) to the said output or outputs to be activated of the destination row control circuit.
18. Display panel according to Claim 17, characterized in that a row control circuit (22, 23) enables the transmission of a signal received on one of its outputs, to the corresponding row, at the chosen instant at which it receives a signal of the same type from the means (SEQ) of sequential transmission.
19. Display panel according to Claim 16, characterized in that the addressing device comprises:

    a signals generator (GS) delivering signals of the three types,

    means (GD) for delivering on the one hand each signal accompanied by an identification of a destination control circuit (IEC, IIC, IPC) and on the other hand each signal accompanied by an identification of one or more outputs to be activated of a row control circuit (IES, IIS, IPS),

    first means (SEQ) for sequentially transmitting, at a chosen instant, each signal accompanied by the identification of the destination control circuit to the said destination row control circuit,

    second means (SEQ') for sequentially transmitting, at the same chosen instant, a signal of the same type accompanied by the identification of the said output or outputs to be activated to the said output or outputs to be activated of all the destination row control circuits possessing one or such outputs.
20. Display panel according to Claim 19, characterized in that a row control circuit (22, 23) enables the transmission of a signal received from the second means (SEQ') of sequential transmission to the row corresponding to the output to be activated when it has received at the same instant a signal of the same type originating from the first means (SEQ) of sequential transmission.

Images