EP0877999B1 - Display panel control process and display device using such process - Google Patents

Display panel control process and display device using such process Download PDF

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Publication number
EP0877999B1
EP0877999B1 EP97901133A EP97901133A EP0877999B1 EP 0877999 B1 EP0877999 B1 EP 0877999B1 EP 97901133 A EP97901133 A EP 97901133A EP 97901133 A EP97901133 A EP 97901133A EP 0877999 B1 EP0877999 B1 EP 0877999B1
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EP
European Patent Office
Prior art keywords
signal
addressing
vref
extreme
sustain
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EP97901133A
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German (de)
French (fr)
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EP0877999A1 (en
Inventor
Serge Thomson-CSF S.C.P.I. SALAVIN
André Thomson-CSF S.C.P.I. DUNAND
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Vantiva SA
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Thomson SA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/297—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using opposed discharge type panels

Definitions

  • the present invention relates to a control method a memory effect display panel and especially those of large cut. It aims to increase the speed of image renewal.
  • the display panels have a large number of cells arranged in matrix form in rows and columns.
  • Each cell consists of the gas space located at the intersection of two electrodes belonging to two networks of orthogonal electrodes and are found subject to control signals constituted by the difference of voltages applied to the two electrodes between which it is located.
  • a signal is applied to all the lines of alternative maintenance substantially in niches. It has the effect of maintaining each cell in the state previously assigned to it by a signal addressing. It generates at the level of the cells in the registered state a discharge maintenance.
  • Addressing is generally done by line-by-line scanning. All cells in a selected row are ordered simultaneously by a more or less complex semi-selective operation to be “erased” and this operation is followed by a selective operation during which cells of the line can be "registered". The operation semi-selective followed by the selective operation is accomplished with a time shift from one line to another.
  • T 20 ms t ⁇ 20 8X1000 ⁇ 2.5 ⁇ s
  • This duration is close to the physical limits of the duration necessary for the discharge.
  • the discharge current is limited by a capacitor in series with each cell to avoid destruction of the display panel if the source power supply is not limited by current.
  • This capacitor is generally achieved by covering the electrode network with a layer enamel dielectric for example.
  • Erasing a cell consists of deleting the charges stored on the dielectric at the level of the cells of the line considered.
  • the maintenance signals are generally a succession of voltage slots, between two extreme high and low levels with possibly a median level.
  • the semi-selective address signal of erasure in the form of a voltage pulse, of suitable amplitude to create an erasure discharge, which is superimposed on the slots of the maintenance signal.
  • This semi-selective erase addressing signal comes in increases the duration of a maintenance cycle compared to that required for maintenance only.
  • Patent application EP-A1-0 337 833 illustrates the case where the erasure signal increases the duration of the maintenance cycle compared to that required for maintenance.
  • Figures 1a, 1b, 1c show timing diagrams of the signal and the semi-selective erase address signal in different cases currently used. The selective addressing signal registration is not shown.
  • the maintenance signal Vref comprises a level median of duration tmb located between two low landings of duration tb1b, tb2b.
  • the semi-selective erase addressing signal is a pulse superimposed on the maintenance signal Vref, generated during this stage median. Its amplitude Vpb is less than that Vpa represented on the Figure 1a.
  • tcb tb1b + tmb + tb2b + thb
  • the maintenance signal Vref comprises a level median of duration tcm between a low level of duration tbc and an upper level of duration thc.
  • the semi-selective erase addressing signal is a amplitude pulse Vpc generated from this median level.
  • the amplitude Vpc is less than that of Figure 1a.
  • the configuration where the erase pulse is generated from downstairs has one drawback.
  • the amplitude of the pulse to generate remains important and this impulse can only be generated from a relatively expensive specific circuit.
  • the present invention therefore proposes to integrate the time of semi-selective erasure addressing in the maintenance cycle without as much to increase the duration.
  • the present invention is a control method a display panel comprising cells defined at the intersection of two networks of crossed electrodes, these cells comprising two states, one registered, the other deleted. It involves applying to all cells a maintenance signal substantially in slots on both sides of a median potential, aimed at producing a maintenance discharge at the level cells in the state registered at the end of the fronts leading to an extreme plateau and applying an addressing signal superimposed on the maintenance signal successively to the electrodes of a network.
  • the addressing signal includes a semi-selective erasure signal which generates for the cells to the state registers an erasure discharge.
  • the erasure discharge occurs at the end of a leading front at an extreme level of the maintenance signal. This erasure discharge inhibits the maintenance discharge that should have been generated by the signal maintenance only.
  • FIG. 2 schematically represents a device for image display to which the method according to the invention applies.
  • This display device includes a PAP display panel to plasma and control means.
  • the PAP display panel has a first network of line electrodes Y1 to Y4 crossed with a second network of electrodes columns X1 to X4. Each cell crossing corresponds to a cell This.
  • the cells are arranged in a matrix.
  • Each Y1 line electrode at Y4 is connected to a line addressing circuit ADL1, ADL2 or "line driver".
  • Each column electrode X1 to X4 is connected to a circuit column addressing ADC1, ADC2 or "driver-column". There are two on the example shown.
  • Column addressing circuits generate pulses that mask those generated by the selective addressing signal in writing on a selected line, at the Ce cells of this line not to be entered.
  • Line addressing circuits ADL1, ADL2 receive the signal Vref maintenance of a GSE maintenance signal generator and the signal Vad addressing superimposed on the maintenance signal Vref of a generator GSA addressing signals.
  • Figures 3a, 3c show a timing diagram of the signals received by two lines of the PAP panel of figure 2, selected successively, referenced I1, I2.
  • the PAP panel is controlled by the process according to the invention.
  • Figure 3b is a timing diagram of discharges occurring on line I1.
  • All the electrodes of a network here all the electrodes of line simultaneously receive the maintenance signal Vref (shown in lines full).
  • This signal Vref is substantially in time slots, with steps extreme high Ph at potential V2 and low Pb at potential V1 located on the other side and other median bearings Pm, at the median potential V0.
  • the duration of middle stops is relatively short.
  • the middle bearings Pm can be absent from the maintenance signal Vref.
  • the extreme bearings Ph, Pb are separated by rising fm and falling fd edges.
  • the maintenance signal Vref causes Iden maintenance discharges at Ce cells at the registered state. These Iden discharges occur after an interval of time ⁇ t after the start of an extreme plateau Ph, Pb. In the panels to color viewing plasma, the time interval ⁇ t is worth a few hundreds of nanoseconds.
  • the addressing signal Vad (shown in dotted lines) superimposed on the maintenance signal Vref is applied to the electrodes of a network each in turn.
  • the addressing signal Vad (shown in dotted lines) superimposed on the maintenance signal Vref is applied to the electrodes of a network each in turn.
  • the line electrodes It is conceivable that it will be applied to column electrodes.
  • the maintenance signal Vref could also be applied to the column electrodes.
  • the addressing signal Vad is broken down into a semi-selective erasing signal and a selective registration signal which does not interest us for the moment.
  • the semi-selective erase address signal is an erase pulse Ie of amplitude Vp generated from an extreme plateau Pb, Ph of the maintenance signal Vref after a time interval ⁇ t1 after the start of the plateau extreme Pb, Ph. This time interval is such that: 0 ⁇ t1 ⁇ t
  • the pulse le of the addressing signal Vad is generated from an extreme low level Pb of the maintenance signal Vref.
  • the erase pulse generates an erase discharge Idef at the level of all Ce cells of the row selected in the report registered and this Idef discharge inhibits the Iden discharge which should have been generated by the maintenance signal Vref only.
  • the erase pulse can last up to the next rising edge fm of the maintenance signal Vref or be more short.
  • the values of the time interval ⁇ t1 and the amplitude Vp of the erasure pulse are chosen so that the charges stored opposite on the dielectric covering the electrodes of the Ce cells in the state subscribed from the selected line leave their support and recombine in gas space.
  • the amplitude Vp represented is substantially equal to the half that of the maintenance signal Vref.
  • the erase pulse is generated from a extreme low level Pb, it can be generated from an extreme high level Ph. In both cases, it has a bearing which is closer to the median potential V0 as the extreme stages Ph, Pb of the maintenance signal They are not.
  • an erasure pulse le is generated from the first low landing Pb of the maintenance signal Vref while on the Figure 3c it is generated from the next low level Pb.
  • the signal selective registration addressing can take place, in a conventional manner, for a line selected from the upper level Ph following that during which the semi-selective erase signal intervened.
  • FIG. 4a schematically represents a module of the output stage of an ADL line addressing circuit as well as the currents flowing through it when the display panel to which it is connected is conventionally controlled.
  • Figure 4b shows the same module to which the method according to the invention applies.
  • the ADL line addressing circuit generally supplying several lines, has an output stage comprising as many modules, like that of Figures 4, that lines.
  • Each module has a pair of switches T1, T2 having a common point A which is connected to the line electrode of line I1 corresponding.
  • the line is electrically equivalent to a capacity Cp.
  • One of the switches T2 receives the maintenance signal Vref and the other T1 receives the addressing signal Vad superimposed on the maintenance signal Vref.
  • the switches T1, T2 are generally MOS transistors. They are switched alternately. When the Vref signal applies T1 switch is blocked and the T2 conductive switch is the reverse which occurs when the signal Vad superimposed on the signal Vref applies.
  • a diode d1 is mounted in parallel with the switch T1, a diode d2 with the switch T2.
  • the cathode of diode d2 and the anode diode d1 are connected to the common point A.
  • the signal semi-selective erasing address Vad superimposed on the maintenance signal is applied to a selected line for times when the signal maintenance Vref alone does not generate a discharge on the other lines.
  • the semi-selective addressing signal Vad delete superimposed on the maintenance signal Vref applies on a line selected while the maintenance signal Vref alone generates maintenance discharges on other lines controlled by the same circuit line addressing.
  • the maintenance discharge current iden1 generated during an extreme low level on lines not selected for addressing semi-selective erasure can no longer go through diode d1 because of the presence of the addressing signal Vad superimposed on the signal at this instant of maintenance Vref on the cathode of diode d1.
  • the Iden1 maintenance discharge current flows through the switch T2 receiving the maintenance signal Vref alone and which is driver. Consequently, the switch T2 will be sized to withstand this Iden1 maintenance discharge current (see Figure 4b).
  • the Iden2 maintenance discharge current generated during a extreme high stage passes through diode d2 as in FIG. 4a.
  • switch T2 At the level of the module supplying the line selected for erasure, switch T2 is conductive and switch T1 is blocked. Erase discharge current Idef flows through the switch T2 and is interrupted when the switch T1 is switched to make raise the signal to the middle level (see figure 3a).
  • FIG. 5a represents a timing diagram of the maintenance signal Vref and the semi-selective erase addressing signal Vad superimposed on the maintenance signal and applied to a selected electrode of a panel display controlled by a variant of the method according to the invention.
  • the semi-selective erase addressing signal Vad comprises a decreasing slope portion Vpd, generated from a potential Vd intermediate, referenced with respect to the potential V1 of the extreme bearing and between the potential V1 and the median potential V0 of the maintenance signal Vref, this portion Vpd ending at a residual potential Vi referenced by relation to potential V1 between said potential V1 and the potential intermediate Vd.
  • the residual potential Vi can be zero.
  • This Vpd portion to decreasing slope begins at the beginning of said extreme plateau.
  • This portion Vpd of decreasing slope signal inhibits the maintenance discharge which would have must have been generated by the maintenance signal Vref in the absence of a signal semi-selective Vad addressing.
  • This portion Vpd of signal to slope decreasing produces an erasure discharge at the cell level of the selected line.
  • the portion Vpd of signal with decreasing slope starts at the same time as an extreme low stop of the maintenance signal Vref.
  • the semi-selective erase addressing signal Vad comprises before the Vpd portion of signal with decreasing slope a portion which follows the signal Vref with Vd offset.
  • the semi-selective addressing signal erase begins during the edge fd of the maintenance signal Vref which leads at the extreme low level Pb during which the erasure discharge goes appear.
  • the variation of the slope of the Vpd portion of signal to slope decreasing is adjustable so as to stop the maintenance discharge well which should occur in the absence of the addressing signal.
  • Vpd Using the decreasing slope signal portion Vpd allows to better adapt the voltage triggering the erasure discharge to all cells display panel as in the variant shown in Figure 3a. Because, inevitably, a panel of visualization is not homogeneous, that is to say that the voltage which produces a discharge is not necessarily the same from one cell to another.
  • Figure 6a shows schematically a circuit GSA electronics for generating a Vad addressing signal superimposed on the maintenance signal Vref such as that shown in FIG. 5a.
  • This circuit includes a voltage source Vd referenced by relation to the potential of the maintenance signal Vref.
  • the maintenance signal Vref is generated by a circuit for generating the conventional GSE maintenance signal.
  • the output voltage of the voltage source Vd supplies all the circuits line ADL1, ADL2, ... ADLn of the PAP panel which receive on the other hand the maintenance signal Vref.
  • line addressing circuits ADL1, ADL2, ... ADLn are electrically equivalent each to a capacity c.
  • the capacities of line addressing circuits ALD1, ADL2, are connected in parallel.
  • the addressing circuits ADL1, ADL2, ... ADLn are each linked to several PAP panel electrodes.
  • a switch I1 is mounted between the output of the voltage Vd and the line addressing circuits ADL1, ADL2, ... ADLn.
  • the signal supplied by the voltage source Vd follows the signal of maintenance Vref with an offset of Vd.
  • a current regulating device Reg is mounted in series with switch I1, the assembly being mounted in parallel with the source voltage Vd.
  • This Reg device can be realized either by a potentiometer which allows you to adjust the time constant of the Vpd portion of the signal to decreasing slope either by a current generator which allows the adjustment of the slope.
  • the decreasing slope signal portion Vpd is generated by discharging the capacitors c of the line addressing circuits ADL1, ADL1, ... ADLn and this discharge is obtained by blocking the switch I1.
  • the addressing signal Vad superimposed on the maintenance signal Vref applied to the selected line to be deleted then has the following value: Vref + Vd - 1 sc ⁇ idt
  • Capacities c must be loaded beforehand.
  • the charging is obtained by setting the switch I1 to the conductive state.
  • Capacity c can be loaded at different times.
  • the signal portion corresponding to the loading of capacities c carries the reference Vc.
  • the selected line receives the addressing signal Vad superimposed on the maintenance signal Vref which is worth Vref + Vd. It is offset by Vd with respect to the maintenance signal Vref.
  • the discharge of capacities begins when the maintenance signal Vref alone reaches the level Pb.
  • the line which has just been erased can receive the maintenance signal Vref by switching on the switch T2 and blocking of the T1 switch for example and / or adjustment of the residual potential Vi equal to V1.
  • the line selected for registration receives the signal addressing Vad superimposed on the maintenance signal Vref which is equal to Vref + Vd, capacity loading c occurred at the start of the extreme plateau Ph the maintenance signal Vref during which the registration takes place.
  • the impulses registration are obtained by the cutting means integrated in the addressing circuits ADL1, ADL2, ... ADLn.
  • the line selected for erasure can receive the addressing signal Vad superimposed on the maintenance signal Vref, that is to say Vref + Vd since the capacities are always loaded. It is enough to switch the switches T1, T2 of the pair belonging to the module connected to this line.
  • the other lines only receive the maintenance signal Vref by adequate switching of the pair of module switches which is associated.
  • Switch I2 is kept blocked during erasure but as soon as the capacities c are loaded at the start of the extreme stage of the maintenance signal Vref, it can be activated. By making it alternately conductor and blocked, the registration pulses are obtained.
  • An advantage of the process according to the invention is that it does not require a maintenance signal with a median level, hence the possibility of remove the circuit generating this median level.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Description

La présente invention est relative à un procédé de commande d'un panneau de visualisation à effet mémoire et notamment ceux de grande taille. Elle a pour but d'augmenter la vitesse de renouvellement d'image.The present invention relates to a control method a memory effect display panel and especially those of large cut. It aims to increase the speed of image renewal.

Les développements récents des panneaux de visualisation à plasma de grande taille ou pour la télévision haute définition conduisent à une plus grande résolution et à une vitesse de renouvellement de l'image de plus en plus grande.Recent developments in display panels at large plasma or for high definition television lead to higher resolution and at a faster image renewal bigger and bigger.

Les panneaux de visualisation comportent un grand nombre de cellules disposées sous forme matricielle en lignes et colonnes. Chaque cellule est constituée par l'espace gazeux situé à l'intersection de deux électrodes appartenant à deux réseaux d'électrodes orthogonaux et se trouve soumise à des signaux de commande constitués par la différence des tensions appliquées aux deux électrodes entre lesquelles elle est située.The display panels have a large number of cells arranged in matrix form in rows and columns. Each cell consists of the gas space located at the intersection of two electrodes belonging to two networks of orthogonal electrodes and are found subject to control signals constituted by the difference of voltages applied to the two electrodes between which it is located.

Le principe de fonctionnement des panneaux à effet mémoire est généralement le suivant. On applique à l'ensemble des lignes un signal d'entretien alternatif sensiblement en créneaux. Il a pour effet de maintenir chaque cellule dans l'état qui lui a été assigné auparavant par un signal d'adressage. Il génère au niveau des cellules à l'état inscrit une décharge d'entretien.The operating principle of memory effect panels is usually the following. A signal is applied to all the lines of alternative maintenance substantially in niches. It has the effect of maintaining each cell in the state previously assigned to it by a signal addressing. It generates at the level of the cells in the registered state a discharge maintenance.

L'adressage se fait généralement par balayage ligne par ligne. Toutes les cellules d'une ligne sélectionnée sont commandées simultanément par une opération semi-sélective plus ou moins complexe pour être "effacées" et cette opération est suivie d'une opération sélective durant laquelle des cellules de la ligne peuvent être "inscrites". L'opération semi-sélective suivie de l'opération sélective est accomplie avec un décalage de temps d'une ligne à l'autre.Addressing is generally done by line-by-line scanning. All cells in a selected row are ordered simultaneously by a more or less complex semi-selective operation to be "erased" and this operation is followed by a selective operation during which cells of the line can be "registered". The operation semi-selective followed by the selective operation is accomplished with a time shift from one line to another.

Pour obtenir 2a demi-teintes, il faut balayer a fois l'écran pendant la durée T d'une image complète. Si n est le nombre de lignes de l'écran et t la durée pendant laquelle une ligne est adressée, on a la condition : n.t.a≤ T To obtain 2 to half-tones, it is necessary to scan the screen once during the duration T of a complete image. If n is the number of lines on the screen and t is the duration for which a line is addressed, we have the condition: nta≤ T

Par exemple, dans un panneau de type télévision haute définition fonctionnant à 50 Hz avec 8 niveaux de demi-teintes et 1 000 lignes : T = 20 ms t ≈ 208X1000 ≈ 2,5 µs For example, in a high definition television type panel operating at 50 Hz with 8 levels of halftone and 1,000 lines: T = 20 ms t ≈ 20 8X1000 ≈ 2.5 µs

Cette durée est proche des limites physiques de la durée nécessaire à la réalisation d'une décharge.This duration is close to the physical limits of the duration necessary for the discharge.

Si le nombre de lignes et/ou le nombre de demi-teintes doit encore augmenter, un gain dans le temps d'adressage devient primordial pour satisfaire à cette augmentation de la vitesse de renouvellement d'image.If the number of lines and / or the number of halftones must further increase, a gain in addressing time becomes essential to meet this increase in renewal speed image.

Dans un panneau de visualisation à plasma, de type alternatif, le courant de décharge est limité par un condensateur en série avec chaque cellule pour éviter une destruction du panneau de visualisation si la source d'alimentation n'est pas limitée en courant. Ce condensateur est généralement réalisé en recouvrant le réseau d'électrodes d'une couche diélectrique en émail par exemple.In an alternative plasma display panel, the discharge current is limited by a capacitor in series with each cell to avoid destruction of the display panel if the source power supply is not limited by current. This capacitor is generally achieved by covering the electrode network with a layer enamel dielectric for example.

L'effacement d'une cellule consiste à supprimer les charges stockées sur le diélectrique au niveau des cellules de la ligne considérée.Erasing a cell consists of deleting the charges stored on the dielectric at the level of the cells of the line considered.

Pour obtenir l'effacement, on applique généralement sur l'électrode formant la ligne correspondante une tension qui engendre une décharge dont l'intensité est choisie de manière que les charges stockées en vis-à-vis se recombinent entre elles pour s'annuler. L'effacement d'une cellule crée un courant de décharge dont l'intensité est sensiblement égale à la moitié de celle du courant d'entretien car il y a transfert d'environ la moitié des charges habituelles d'entretien.To obtain the erasure, we generally apply on the electrode forming the corresponding line a voltage which generates a discharge, the intensity of which is chosen so that the charges stored vis-à-vis recombine them to cancel each other out. Erasing a cell creates a discharge current whose intensity is substantially equal to half of that of the maintenance current because there is transfer of about half usual maintenance costs.

Actuellement l'opération semi-sélective d'effacement s'effectue de différentes manières.Currently the semi-selective erasure operation is carried out from different ways.

Les signaux d'entretien sont généralement une succession de créneaux de tension, entre deux paliers extrêmes haut et bas avec éventuellement un palier médian. Le signal d'adresse semi-sélectif d'effacement a la forme d'une impulsion de tension, d'amplitude convenable pour créer une décharge d'effacement, qui se superpose aux créneaux du signal d'entretien. Ce signal d'adressage semi-sélectif d'effacement vient en fait augmenter la durée d'un cycle d'entretien par rapport à celle nécessaire pour assurer uniquement l'entretien. La demande de brevet EP-A1-0 337 833 illustre le cas où le signal d'effacement vient augmenter la durée du cycle d'entretien par rapport à celle nécessaire pour assurer l'entretien.The maintenance signals are generally a succession of voltage slots, between two extreme high and low levels with possibly a median level. The semi-selective address signal of erasure in the form of a voltage pulse, of suitable amplitude to create an erasure discharge, which is superimposed on the slots of the maintenance signal. This semi-selective erase addressing signal comes in increases the duration of a maintenance cycle compared to that required for maintenance only. Patent application EP-A1-0 337 833 illustrates the case where the erasure signal increases the duration of the maintenance cycle compared to that required for maintenance.

Les figures 1a, 1b, 1c montrent des chronogrammes du signal d'entretien et du signal d'adressage semi-sélectif d'effacement dans différents cas utilisés actuellement. Le signal d'adressage sélectif d'inscription n'est pas représenté.Figures 1a, 1b, 1c show timing diagrams of the signal and the semi-selective erase address signal in different cases currently used. The selective addressing signal registration is not shown.

Sur la figure 1a, le signal d'entretien Vref en traits pleins comporte deux paliers extrêmes l'un correspondant au potentiel V1 bas (négatif) et l'autre au potentiel V2 haut (positif), ces paliers étant établis de part et d'autre d'un potentiel médian ou de référence V0 qui est souvent le potentiel de la masse. Ce signal d'entretien Vref génère des décharges au niveau des cellules à l'état inscrit juste après une inversion de polarité, c'est-à-dire après un front conduisant à un palier extrême. Le signal d'adressage semi-sélectif d'effacement est une impulsion de tension représentée en traits pointillés, superposée au signal d'entretien. L'impulsion d'effacement est générée au cours d'un palier bas. La durée du cycle d'entretien vaut alors : tca = tb1a + tma + tb2a + tha avec :

  • tb1a durée du palier bas avant l'impulsion d'effacement,
  • tma durée de l'impulsion d'effacement,
  • tb2a durée du palier bas après l'impulsion d'effacement,
  • tha durée du palier haut.
In FIG. 1a, the maintenance signal Vref in solid lines comprises two extreme stages, one corresponding to the low potential V1 (negative) and the other to the high potential V2 (these stages being established on both sides). another of a median or reference potential V0 which is often the potential of the mass. This maintenance signal Vref generates discharges at the level of the cells in the written state just after an inversion of polarity, that is to say after an edge leading to an extreme plateau. The semi-selective erase addressing signal is a voltage pulse represented by dotted lines, superimposed on the maintenance signal. The erase pulse is generated during a low plateau. The duration of the maintenance cycle is then worth: tca = tb1a + tma + tb2a + tha with:
  • tb1a duration of the low plateau before the erase pulse,
  • tma duration of the erase pulse,
  • tb2a duration of the low plateau after the erase pulse,
  • tha duration of the upper stage.

Sur la figure 1b, le signal d'entretien Vref comporte un palier médian de durée tmb situé entre deux paliers bas de durée tb1b, tb2b.In FIG. 1b, the maintenance signal Vref comprises a level median of duration tmb located between two low landings of duration tb1b, tb2b.

Le signal d'adressage semi-sélectif d'effacement est une impulsion superposée au signal d'entretien Vref, générée pendant ce palier médian. Son amplitude Vpb est moindre que celle Vpa représentée sur la figure 1a.The semi-selective erase addressing signal is a pulse superimposed on the maintenance signal Vref, generated during this stage median. Its amplitude Vpb is less than that Vpa represented on the Figure 1a.

La durée tcb du cycle d'entretien vaut alors : tcb = tb1b + tmb + tb2b + thb The duration tcb of the maintenance cycle is then worth: tcb = tb1b + tmb + tb2b + thb

Sur la figure 1c, le signal d'entretien Vref comporte un palier médian de durée tcm entre un palier bas de durée tbc et un palier haut de durée thc. Le signal d'adressage semi-sélectif d'effacement est une impulsion d'amplitude Vpc générée à partir de ce palier médian. L'amplitude Vpc est moindre que celle de la figure 1a.In FIG. 1c, the maintenance signal Vref comprises a level median of duration tcm between a low level of duration tbc and an upper level of duration thc. The semi-selective erase addressing signal is a amplitude pulse Vpc generated from this median level. The amplitude Vpc is less than that of Figure 1a.

La durée tcc du cycle d'entretien vaut alors : tcc = tbc + tmc + thc The duration tcc of the maintenance cycle is then worth: tcc = tbc + tmc + thc

L'inconvénient de ce type d'opération est que la durée du cycle d'entretien est plus longue que celle qui est normalement suffisante pour assurer l'entretien. Dans les cas représentés aux figures 1a, 1b, 1c cette durée est augmentée de la durée tma, tmb, tmc, respectivement.The disadvantage of this type of operation is that the duration of the cycle is longer than is normally sufficient for provide maintenance. In the cases shown in Figures 1a, 1b, 1c this duration is increased by duration tma, tmb, tmc, respectively.

La configuration où l'impulsion d'effacement est générée à partir d'un palier médian possède un inconvénient lié à la présence du palier médian pendant le cycle d'entretien. Des charges peuvent disparaítre pendant ce palier médian, cette disparition entraíne une perte partielle de la mémoire du panneau.The configuration where the erase pulse is generated from of a median level has a drawback linked to the presence of the level median during the maintenance cycle. Charges may disappear during this median plateau, this disappearance results in a partial loss of panel memory.

De plus, la génération du palier médian nécessite un circuit spécifique.In addition, the generation of the median level requires a circuit specific.

La configuration où l'impulsion d'effacement est générée à partir du palier bas possède un inconvénient. L'amplitude de l'impulsion à générer reste importante et cette impulsion ne peut être générée qu'à partir d'un circuit spécifique relativement coûteux.The configuration where the erase pulse is generated from downstairs has one drawback. The amplitude of the pulse to generate remains important and this impulse can only be generated from a relatively expensive specific circuit.

La présente invention propose donc d'intégrer le temps de l'adressage semi-sélectif d'effacement dans le cycle d'entretien sans pour autant en augmenter la durée.The present invention therefore proposes to integrate the time of semi-selective erasure addressing in the maintenance cycle without as much to increase the duration.

Pour cela, la présente invention est un procédé de commande d'un panneau de visualisation comportant des cellules définies à l'intersection de deux réseaux d'électrodes croisées, ces cellules comportant deux états l'un inscrit, l'autre effacé. Il consiste à appliquer à toutes les cellules un signal d'entretien sensiblement en créneaux de part et d'autre d'un potentiel médian, visant à produire une décharge d'entretien au niveau des cellules à l'état inscrit à l'issu des fronts conduisant à un palier extrême et à appliquer un signal d'adressage se superposant au signal d'entretien successivement aux électrodes d'un réseau. Le signal d'adressage comprend un signal semi-sélectif d'effacement qui génère pour les cellules à l'état inscrit une décharge d'effacement.For this, the present invention is a control method a display panel comprising cells defined at the intersection of two networks of crossed electrodes, these cells comprising two states, one registered, the other deleted. It involves applying to all cells a maintenance signal substantially in slots on both sides of a median potential, aimed at producing a maintenance discharge at the level cells in the state registered at the end of the fronts leading to an extreme plateau and applying an addressing signal superimposed on the maintenance signal successively to the electrodes of a network. The addressing signal includes a semi-selective erasure signal which generates for the cells to the state registers an erasure discharge.

La décharge d'effacement se produit à l'issu d'un front conduisant à un palier extrême du signal d'entretien. Cette décharge d'effacement inhibe la décharge d'entretien qui aurait dû être générée par le signal d'entretien seul.The erasure discharge occurs at the end of a leading front at an extreme level of the maintenance signal. This erasure discharge inhibits the maintenance discharge that should have been generated by the signal maintenance only.

L'invention sera mieux comprise à la lecture de la description qui suit de modes de réalisation, donnés à titre d'exemples non limitatifs et illustrés par les figures jointes qui représentent :

  • les figures 1a, 1b, 1c (déjà décrites) : des chronogrammes des signaux d'entretien et d'adressage semi-sélectif d'effacement appliqués à un panneau de visualisation commandé de manière conventionnelle,
  • la figure 2 : un dispositif de visualisation auquel s'applique le procédé selon l'invention,
  • les figures 3a, 3c : des chronogrammes des signaux d'entretien et d'adressage semi-sélectif d'effacement appliqués sur deux lignes d'un panneau de visualisation commandé par le procédé de l'invention,
  • la figure 3b : un chronogramme des courants de décharge apparaissant sur la ligne recevant les signaux de la figure 3a,
  • les figures 4a, 4b : les sens des courants de décharge circulant dans un module d'étage de sortie d'un circuit d'adressage auquel s'applique un procédé de commande conventionnel et le procédé selon l'invention,
  • les figures 5a, 5b : des chronogrammes des signaux d'entretien et d'adressage appliqués sur une ligne d'un panneau de visualisation commandé par deux variantes du procédé selon l'invention,
  • les figures 6a, 6b : des dispositifs de visualisation auxquels s'appliquent les variantes du procédé selon l'invention.
The invention will be better understood on reading the following description of embodiments, given by way of nonlimiting examples and illustrated by the attached figures which represent:
  • FIGS. 1a, 1b, 1c (already described): chronograms of the maintenance and semi-selective erasing addressing signals applied to a display panel controlled in a conventional manner,
  • FIG. 2: a display device to which the method according to the invention applies,
  • FIGS. 3a, 3c: chronograms of the maintenance and semi-selective erasure addressing signals applied to two lines of a display panel controlled by the method of the invention,
  • FIG. 3b: a chronogram of the discharge currents appearing on the line receiving the signals of FIG. 3a,
  • FIGS. 4a, 4b: the directions of the discharge currents flowing in an output stage module of an addressing circuit to which a conventional control method and the method according to the invention apply,
  • FIGS. 5a, 5b: chronograms of the maintenance and addressing signals applied to a line of a display panel controlled by two variants of the method according to the invention,
  • FIGS. 6a, 6b: display devices to which the variants of the method according to the invention apply.

La figure 2 représente de manière schématique un dispositif de visualisation d'image auquel s'applique le procédé selon l'invention. Ce dispositif de visualisation comporte un panneau de visualisation PAP à plasma et des moyens de commande. FIG. 2 schematically represents a device for image display to which the method according to the invention applies. This display device includes a PAP display panel to plasma and control means.

Le panneau de visualisation PAP comporte un premier réseau d'électrodes lignes Y1 à Y4 croisé avec un second réseau d'électrodes colonnes X1 à X4. A chaque croisement d'électrodes correspond une cellule Ce. Les cellules sont disposées matriciellement. Chaque électrode ligne Y1 à Y4 est reliée à un circuit d'adressage ligne ADL1, ADL2 ou "driver-ligne".The PAP display panel has a first network of line electrodes Y1 to Y4 crossed with a second network of electrodes columns X1 to X4. Each cell crossing corresponds to a cell This. The cells are arranged in a matrix. Each Y1 line electrode at Y4 is connected to a line addressing circuit ADL1, ADL2 or "line driver".

Pour de grands panneaux, il y en a généralement plusieurs. Sur l'exemple représenté il y en a deux qui alimentent chacun un groupe de lignes en signaux d'entretien et d'adressage.For large panels, there are usually several. Sure the example shown there are two that each feed a group of lines in maintenance and addressing signals.

Chaque électrode colonne X1 à X4 est reliée à un circuit d'adressage colonne ADC1, ADC2 ou "driver-colonne". Il y en a deux sur l'exemple représenté. Les circuits d'adressage colonne génèrent des impulsions qui masquent celles générées par le signal d'adressage sélectif en inscription sur une ligne sélectionnée, au niveau des cellules Ce de cette ligne ne devant pas être inscrites.Each column electrode X1 to X4 is connected to a circuit column addressing ADC1, ADC2 or "driver-column". There are two on the example shown. Column addressing circuits generate pulses that mask those generated by the selective addressing signal in writing on a selected line, at the Ce cells of this line not to be entered.

Les circuits d'adressage ligne ADL1, ADL2 reçoivent le signal d'entretien Vref d'un générateur de signaux d'entretien GSE et le signal d'adressage Vad superposé au signal d'entretien Vref d'un générateur de signaux d'adressage GSA.Line addressing circuits ADL1, ADL2 receive the signal Vref maintenance of a GSE maintenance signal generator and the signal Vad addressing superimposed on the maintenance signal Vref of a generator GSA addressing signals.

Les figures 3a, 3c montrent un chronogramme des signaux reçus par deux lignes du panneau PAP de la figure 2, sélectionnées successivement, référencées I1, I2. Le panneau PAP est commandé par le procédé conforme à l'invention. La figure 3b est un chronogramme des décharges se produisant sur la ligne I1.Figures 3a, 3c show a timing diagram of the signals received by two lines of the PAP panel of figure 2, selected successively, referenced I1, I2. The PAP panel is controlled by the process according to the invention. Figure 3b is a timing diagram of discharges occurring on line I1.

Toutes les électrodes d'un réseau, ici toutes les électrodes de ligne reçoivent simultanément le signal d'entretien Vref (représenté en traits pleins). Ce signal Vref est sensiblement en créneaux, avec des paliers extrêmes hauts Ph au potentiel V2 et bas Pb au potentiel V1 situés de part et d'autre de paliers médians Pm, au potentiel médian V0. La durée des paliers médians est relativement courte. Les paliers médians Pm peuvent être absents du signal d'entretien Vref. Les paliers extrêmes Ph, Pb sont séparés par des fronts montant fm et descendant fd. Le signal d'entretien Vref provoque des décharges d'entretien Iden au niveau des cellules Ce à l'état inscrit. Ces décharges Iden se produisent au bout d'un intervalle de temps Δt après le début d'un palier extrême Ph, Pb. Dans les panneaux à plasma de visualisation en couleurs, l'intervalle de temps Δt vaut quelques centaines de nanosecondes.All the electrodes of a network, here all the electrodes of line simultaneously receive the maintenance signal Vref (shown in lines full). This signal Vref is substantially in time slots, with steps extreme high Ph at potential V2 and low Pb at potential V1 located on the other side and other median bearings Pm, at the median potential V0. The duration of middle stops is relatively short. The middle bearings Pm can be absent from the maintenance signal Vref. The extreme bearings Ph, Pb are separated by rising fm and falling fd edges. The maintenance signal Vref causes Iden maintenance discharges at Ce cells at the registered state. These Iden discharges occur after an interval of time Δt after the start of an extreme plateau Ph, Pb. In the panels to color viewing plasma, the time interval Δt is worth a few hundreds of nanoseconds.

Selon le procédé conforme à l'invention, le signal d'adressage Vad (représenté en pointillés) superposé au signal d'entretien Vref est appliqué aux électrodes d'un réseau chacune leur tour. Dans l'exemple, il est appliqué aux électrodes ligne. Il est envisageable qu'il soit appliqué aux électrodes colonne. Le signal d'entretien Vref pourrait aussi être appliqué aux électrodes colonnes.According to the method according to the invention, the addressing signal Vad (shown in dotted lines) superimposed on the maintenance signal Vref is applied to the electrodes of a network each in turn. In the example, is applied to the line electrodes. It is conceivable that it will be applied to column electrodes. The maintenance signal Vref could also be applied to the column electrodes.

Le signal d'adressage Vad se décompose en un signal semi-sélectif d'effacement et un signal sélectif d'inscription qui ne nous intéresse pas pour l'instant. Le signal d'adressage semi-sélectif d'effacement est une impulsion d'effacement le d'amplitude Vp générée depuis un palier extrême Pb, Ph du signal d'entretien Vref au bout d'un intervalle de temps Δt1 après le début du palier extrême Pb, Ph. Cet intervalle de temps est tel que : 0 < Δt1 < Δt The addressing signal Vad is broken down into a semi-selective erasing signal and a selective registration signal which does not interest us for the moment. The semi-selective erase address signal is an erase pulse Ie of amplitude Vp generated from an extreme plateau Pb, Ph of the maintenance signal Vref after a time interval Δt1 after the start of the plateau extreme Pb, Ph. This time interval is such that: 0 <Δt1 <Δt

Sur les figures 3, l'impulsion le du signal d'adressage Vad est générée depuis un palier extrême bas Pb du signal d'entretien Vref.In FIGS. 3, the pulse le of the addressing signal Vad is generated from an extreme low level Pb of the maintenance signal Vref.

L'impulsion d'effacement le génère une décharge d'effacement Idef au niveau de toutes les cellules Ce de la ligne sélectionnée à l'état inscrit et cette décharge Idef inhibe celle Iden qui aurait dû être générée par le signal d'entretien Vref seul. L'impulsion d'effacement le peut durer jusqu'au front montant fm suivant du signal d'entretien Vref ou être plus courte.The erase pulse generates an erase discharge Idef at the level of all Ce cells of the row selected in the report registered and this Idef discharge inhibits the Iden discharge which should have been generated by the maintenance signal Vref only. The erase pulse can last up to the next rising edge fm of the maintenance signal Vref or be more short.

Les valeurs de l'intervalle de temps Δt1 et de l'amplitude Vp de l'impulsion d'effacement sont choisies pour que les charges stockées en vis-à-vis sur le diélectrique recouvrant les électrodes des cellules Ce à l'état inscrit de la ligne sélectionnée quittent leur support et se recombinent dans l'espace gazeux. L'amplitude Vp représentée est sensiblement égale à la moitié de celle du signal d'entretien Vref.The values of the time interval Δt1 and the amplitude Vp of the erasure pulse are chosen so that the charges stored opposite on the dielectric covering the electrodes of the Ce cells in the state subscribed from the selected line leave their support and recombine in gas space. The amplitude Vp represented is substantially equal to the half that of the maintenance signal Vref.

Au lieu que l'impulsion d'effacement le soit générée depuis un palier extrême bas Pb, elle peut être générée depuis un palier extrême haut Ph. Dans les deux cas, elle possède un palier qui est plus proche du potentiel médian V0 que les paliers extrêmes Ph, Pb du signal d'entretien Vref ne le sont.Instead of the erase pulse being generated from a extreme low level Pb, it can be generated from an extreme high level Ph. In both cases, it has a bearing which is closer to the median potential V0 as the extreme stages Ph, Pb of the maintenance signal They are not.

Sur la figure 3a, une impulsion d'effacement le est générée depuis le premier palier bas Pb du signal d'entretien Vref tandis que sur la figure 3c elle est générée depuis le palier bas Pb suivant. Le signal d'adressage sélectif d'inscription peut avoir lieu, de manière classique, pour une ligne sélectionnée depuis le palier haut Ph suivant celui pendant lequel le signal semi-sélectif d'effacement est intervenu.In FIG. 3a, an erasure pulse le is generated from the first low landing Pb of the maintenance signal Vref while on the Figure 3c it is generated from the next low level Pb. The signal selective registration addressing can take place, in a conventional manner, for a line selected from the upper level Ph following that during which the semi-selective erase signal intervened.

La figure 4a représente de manière schématique un module d'étage de sortie d'un circuit d'adressage ligne ADL ainsi que les sens des courants qui le traversent lorsque le panneau de visualisation auquel il est connecté est commandé de manière classique. La figure 4b représente le même module auquel s'applique le procédé selon l'invention.FIG. 4a schematically represents a module of the output stage of an ADL line addressing circuit as well as the currents flowing through it when the display panel to which it is connected is conventionally controlled. Figure 4b shows the same module to which the method according to the invention applies.

Le circuit d'adressage ligne ADL alimentant généralement plusieurs lignes, possède un étage de sortie comportant autant de modules, comme celui des figures 4, que de lignes.The ADL line addressing circuit generally supplying several lines, has an output stage comprising as many modules, like that of Figures 4, that lines.

Chaque module comporte une paire de commutateurs T1, T2 ayant un point commun A qui est relié à l'électrode ligne de la ligne I1 correspondante. La ligne est équivalente électriquement à une capacité Cp.Each module has a pair of switches T1, T2 having a common point A which is connected to the line electrode of line I1 corresponding. The line is electrically equivalent to a capacity Cp.

L'un des commutateurs T2 reçoit le signal d'entretien Vref et l'autre T1 reçoit le signal d'adressage Vad superposé au signal d'entretien Vref. Les commutateurs T1, T2 sont généralement des transistors MOS. Ils sont commutés en alternance. Lorsque le signal Vref s'applique le commutateur T1 est bloqué et le commutateur T2 conducteur, c'est l'inverse qui se produit lorsque le signal Vad superposé au signal Vref s'applique.One of the switches T2 receives the maintenance signal Vref and the other T1 receives the addressing signal Vad superimposed on the maintenance signal Vref. The switches T1, T2 are generally MOS transistors. They are switched alternately. When the Vref signal applies T1 switch is blocked and the T2 conductive switch is the reverse which occurs when the signal Vad superimposed on the signal Vref applies.

Une diode d1 est montée en parallèle avec le commutateur T1, une diode d2 avec le commutateur T2. La cathode de la diode d2 et l'anode de la diode d1 sont reliées au point commun A.A diode d1 is mounted in parallel with the switch T1, a diode d2 with the switch T2. The cathode of diode d2 and the anode diode d1 are connected to the common point A.

Dans le cas de la commande classique d'effacement, le signal d'adressage Vad semi-sélectif d'effacement superposé au signal d'entretien est appliqué sur une ligne sélectionnée pendant des instants où le signal d'entretien Vref seul ne génère pas de décharge sur les autres lignes.In the case of the classic erase command, the signal semi-selective erasing address Vad superimposed on the maintenance signal is applied to a selected line for times when the signal maintenance Vref alone does not generate a discharge on the other lines.

Le courant de décharge Iden1 généré par le signal d'entretien Vref pendant un palier extrême bas Pb passe par la diode d1 et le courant de décharge Iden2 généré pendant un palier extrême haut Ph passe par la diode d2 (voir figure 4a).The discharge current Iden1 generated by the maintenance signal Vref during an extreme low plateau Pb goes through diode d1 and the current Iden2 discharge generated during an extreme high plateau Ph goes through the diode d2 (see figure 4a).

Lorsque le panneau de visualisation est commandé par le procédé selon l'invention, le signal d'adressage Vad semi-sélectif d'effacement superposé au signal d'entretien Vref s'applique sur une ligne sélectionnée pendant que le signal d'entretien Vref seul génère des décharges d'entretien sur les autres lignes commandées par le même circuit d'adressage ligne. Le courant de décharge d'entretien iden1 généré pendant un palier extrême bas sur les lignes non sélectionnées pour l'adressage semi-sélectif d'effacement ne peut plus passer par la diode d1 à cause de la présence à cet instant du signal d'adressage Vad superposé au signal d'entretien Vref sur la cathode de la diode d1.When the display panel is controlled by the method according to the invention, the semi-selective addressing signal Vad delete superimposed on the maintenance signal Vref applies on a line selected while the maintenance signal Vref alone generates maintenance discharges on other lines controlled by the same circuit line addressing. The maintenance discharge current iden1 generated during an extreme low level on lines not selected for addressing semi-selective erasure can no longer go through diode d1 because of the presence of the addressing signal Vad superimposed on the signal at this instant of maintenance Vref on the cathode of diode d1.

Le courant de décharge d'entretien Iden1 circule à travers le commutateur T2 recevant le signal d'entretien Vref seul et qui est conducteur. En conséquence, le commutateur T2 sera dimensionné pour supporter ce courant de décharge d'entretien Iden1 (voir figure 4b).The Iden1 maintenance discharge current flows through the switch T2 receiving the maintenance signal Vref alone and which is driver. Consequently, the switch T2 will be sized to withstand this Iden1 maintenance discharge current (see Figure 4b).

Le courant de décharge d'entretien Iden2 généré pendant un palier extrême haut passe par la diode d2 comme sur la figure 4a.The Iden2 maintenance discharge current generated during a extreme high stage passes through diode d2 as in FIG. 4a.

A cause du courant parasite qui apparaít inévitablement lorsque l'on commute des commutateurs, il est préférable de séparer dans le temps les commutations des deux commutateurs T1, T2 de la paire pour éviter un courant de double conduction dans les deux commutateurs.Because of the stray current that inevitably appears when we switch switches, it is better to separate in time the switches of the two switches T1, T2 of the pair to avoid a double conduction current in the two switches.

Au niveau du module alimentant la ligne sélectionnée pour l'effacement, le commutateur T2 est conducteur et le commutateur T1 est bloqué. Le courant de décharge d'effacement Idef traverse le commutateur T2 et est interrompu lorsque l'on commute le commutateur T1 pour faire remonter le signal au palier médian (voir figure 3a).At the level of the module supplying the line selected for erasure, switch T2 is conductive and switch T1 is blocked. Erase discharge current Idef flows through the switch T2 and is interrupted when the switch T1 is switched to make raise the signal to the middle level (see figure 3a).

La figure 5a représente un chronogramme du signal d'entretien Vref et du signal d'adressage Vad semi-sélectif d'effacement superposé au signal d'entretien et appliqué à une électrode sélectionnée d'un panneau de visualisation commandé par une variante du procédé selon l'invention.FIG. 5a represents a timing diagram of the maintenance signal Vref and the semi-selective erase addressing signal Vad superimposed on the maintenance signal and applied to a selected electrode of a panel display controlled by a variant of the method according to the invention.

Le signal d'adressage Vad semi-sélectif d'effacement comporte une portion Vpd à pente décroissante, générée à partir d'un potentiel Vd intermédiaire, référencé par rapport au potentiel V1 du palier extrême et compris entre le potentiel V1 et le potentiel médian V0 du signal d'entretien Vref, cette portion Vpd se terminant à un potentiel résiduel Vi référencé par rapport au potentiel V1 compris entre ledit potentiel V1 et le potentiel intermédiaire Vd. Le potentiel résiduel Vi peut être nul. Cette portion Vpd à pente décroissante commence au début dudit palier extrême. Cette portion Vpd de signal à pente décroissante inhibe la décharge d'entretien qui aurait dû être générée par le signal d'entretien Vref en l'absence de signal d'adressage Vad semi-sélectif. Cette portion Vpd de signal à pente décroissante produit une décharge d'effacement au niveau des cellules inscrites de la ligne sélectionnée.The semi-selective erase addressing signal Vad comprises a decreasing slope portion Vpd, generated from a potential Vd intermediate, referenced with respect to the potential V1 of the extreme bearing and between the potential V1 and the median potential V0 of the maintenance signal Vref, this portion Vpd ending at a residual potential Vi referenced by relation to potential V1 between said potential V1 and the potential intermediate Vd. The residual potential Vi can be zero. This Vpd portion to decreasing slope begins at the beginning of said extreme plateau. This portion Vpd of decreasing slope signal inhibits the maintenance discharge which would have must have been generated by the maintenance signal Vref in the absence of a signal semi-selective Vad addressing. This portion Vpd of signal to slope decreasing produces an erasure discharge at the cell level of the selected line.

Sur la figure 5a, la portion Vpd de signal à pente décroissante débute en même temps qu'un palier extrême bas du signal d'entretien Vref. Le signal d'adressage Vad semi-sélectif d'effacement comporte avant la portion Vpd de signal à pente décroissante une portion qui suit le signal d'entretien Vref avec le décalage de Vd. Le signal d'adressage semi-sélectif d'effacement débute pendant le front fd du signal d'entretien Vref qui conduit au palier extrême bas Pb pendant lequel la décharge d'effacement va apparaítre.In FIG. 5a, the portion Vpd of signal with decreasing slope starts at the same time as an extreme low stop of the maintenance signal Vref. The semi-selective erase addressing signal Vad comprises before the Vpd portion of signal with decreasing slope a portion which follows the signal Vref with Vd offset. The semi-selective addressing signal erase begins during the edge fd of the maintenance signal Vref which leads at the extreme low level Pb during which the erasure discharge goes appear.

A l'issu de la portion Vpd de signal à pente décroissante, lorsque la pente tend vers zéro, seul le signal d'entretien Vref s'applique sur la ligne qui vient d'être effacée. A l'issu du front montant suivant du signal d'entretien Vref peut alors débuter l'adressage sélectif en inscription de manière classique. Cet adressage n'est pas représenté sur la figure 5a.At the end of the decreasing slope signal portion Vpd, when the slope tends towards zero, only the maintenance signal Vref applies on the line which has just been deleted. At the end of the next rising edge of the maintenance signal Vref can then start selective addressing in registration so classic. This addressing is not shown in FIG. 5a.

La variation de la pente de la portion Vpd de signal à pente décroissante est ajustable de manière à bien stopper la décharge d'entretien qui devrait se produire en l'absence du signal d'adressage.The variation of the slope of the Vpd portion of signal to slope decreasing is adjustable so as to stop the maintenance discharge well which should occur in the absence of the addressing signal.

Le fait d'utiliser la portion Vpd de signal à pente décroissante permet de mieux adapter la tension déclenchant la décharge d'effacement à toutes les cellules panneau de visualisation que dans la variante représentée à la figure 3a. Car, de manière inévitable, un panneau de visualisation n'est pas homogène, c'est-à-dire que la tension qui produit une décharge n'est pas forcément la même d'une cellule à une autre.Using the decreasing slope signal portion Vpd allows to better adapt the voltage triggering the erasure discharge to all cells display panel as in the variant shown in Figure 3a. Because, inevitably, a panel of visualization is not homogeneous, that is to say that the voltage which produces a discharge is not necessarily the same from one cell to another.

La figure 6a montre de manière schématique un circuit électronique GSA permettant de générer un signal d'adressage Vad superposé au signal d'entretien Vref tel que celui représenté sur la figure 5a. Figure 6a shows schematically a circuit GSA electronics for generating a Vad addressing signal superimposed on the maintenance signal Vref such as that shown in FIG. 5a.

Ce circuit comporte une source de tension Vd référencée par rapport au potentiel du signal d'entretien Vref. Le signal d'entretien Vref est généré par un circuit de génération du signal d'entretien GSE classique. La tension de sortie de la source de tension Vd alimente tous les circuits d'adressage ligne ADL1, ADL2, ... ADLn du panneau PAP qui reçoivent d'autre part le signal d'entretien Vref.This circuit includes a voltage source Vd referenced by relation to the potential of the maintenance signal Vref. The maintenance signal Vref is generated by a circuit for generating the conventional GSE maintenance signal. The output voltage of the voltage source Vd supplies all the circuits line ADL1, ADL2, ... ADLn of the PAP panel which receive on the other hand the maintenance signal Vref.

Ces circuits d'adressage ligne ADL1, ADL2, ... ADLn sont équivalents électriquement chacun à une capacité c. Les capacités c des circuits d'adressage ligne ALD1, ADL2, sont montées en parallèle. Les circuits d'adressage ADL1, ADL2, ... ADLn sont reliés chacun à plusieurs électrodes du panneau PAP.These line addressing circuits ADL1, ADL2, ... ADLn are electrically equivalent each to a capacity c. The capacities of line addressing circuits ALD1, ADL2, are connected in parallel. The addressing circuits ADL1, ADL2, ... ADLn are each linked to several PAP panel electrodes.

Un commutateur I1 est monté entre la sortie de la source de tension Vd et les circuits d'adressage ligne ADL1, ADL2, ... ADLn.A switch I1 is mounted between the output of the voltage Vd and the line addressing circuits ADL1, ADL2, ... ADLn.

Le signal fourni par la source de tension Vd suit le signal d'entretien Vref avec un décalage de Vd.The signal supplied by the voltage source Vd follows the signal of maintenance Vref with an offset of Vd.

Un dispositif de régulation de courant Reg est monté en série avec le commutateur I1, l'ensemble étant monté en parallèle avec la source de tension Vd. Ce dispositif Reg peut être réalisé soit par un potentiomètre qui permet d'ajuster la constante de temps de la portion Vpd de signal à pente décroissante soit par un générateur de courant qui permet le réglage de la pente.A current regulating device Reg is mounted in series with switch I1, the assembly being mounted in parallel with the source voltage Vd. This Reg device can be realized either by a potentiometer which allows you to adjust the time constant of the Vpd portion of the signal to decreasing slope either by a current generator which allows the adjustment of the slope.

La portion Vpd de signal à pente décroissante est générée par décharge des condensateurs c des circuits d'adressage ligne ADL1, ADL1, ... ADLn et cette décharge est obtenue par blocage du commutateur I1. Le signal d'adressage Vad superposé au signal d'entretien Vref appliqué sur la ligne sélectionnée à effacer vaut alors : Vref + Vd -1Σc ∫ idt The decreasing slope signal portion Vpd is generated by discharging the capacitors c of the line addressing circuits ADL1, ADL1, ... ADLn and this discharge is obtained by blocking the switch I1. The addressing signal Vad superimposed on the maintenance signal Vref applied to the selected line to be deleted then has the following value: Vref + Vd - 1 sc ∫ idt

Les capacités c doivent être chargées au préalable. Le chargement est obtenu par la mise à l'état conducteur du commutateur I1.Capacities c must be loaded beforehand. The charging is obtained by setting the switch I1 to the conductive state.

Le chargement des capacités c peut intervenir à différents moments. Capacity c can be loaded at different times.

Sur le chronogramme de la figure 5a, le chargement des capacités c a lieu pendant un front descendant fd du signal d'entretien.On the timing diagram of Figure 5a, the loading of capacitances c takes place during a falling edge fd of the maintenance signal.

Dans un premier temps, pendant ce front descendant fd, toutes les lignes reçoivent le signal d'entretien Vref. Puis la ligne sélectionnée pour l'effacement va recevoir le signal d'adressage Vad semi-sélectif d'effacement superposé au signal d'entretien Vref. Il suffit de bloquer le commutateur T2 du module de l'étage de sortie relié à cette ligne, de rendre conducteur le commutateur T1 et de rendre conducteur le commutateur I1 du circuit GSA. Le chargement des capacités c commence. Le temps mort au niveau des commutateurs T1, T2 de la paire n'est pas nécessaire car la commutation s'effectue avant que le chargement des capacités c ne 'soit terminé.At first, during this falling front fd, all the lines receive the maintenance signal Vref. Then the line selected for the erasure will receive the semi-selective Vad addressing signal erase superimposed on the maintenance signal Vref. Just block the switch T2 of the output stage module connected to this line, to make conductor the switch T1 and make the switch I1 conductive GSA circuit. The loading of the capacities c begins. Time out at level of switches T1, T2 of the pair is not necessary because the switching takes place before capacity c is loaded finished.

Sur la figure 5a, la portion de signal correspondant au chargement des capacités c porte la référence Vc. Lorsque le chargement est terminé, la ligne sélectionnée reçoit le signal d'adressage Vad superposé au signal d'entretien Vref ce qui vaut Vref + Vd. Il est décalé de Vd par rapport au signal d'entretien Vref.In FIG. 5a, the signal portion corresponding to the loading of capacities c carries the reference Vc. When loading is finished, the selected line receives the addressing signal Vad superimposed on the maintenance signal Vref which is worth Vref + Vd. It is offset by Vd with respect to the maintenance signal Vref.

La décharge des capacités débute lorsque le signal d'entretien Vref seul atteint le palier Pb.The discharge of capacities begins when the maintenance signal Vref alone reaches the level Pb.

Lorsque la pente de la portion Vpd de signal à pente décroissante tend vers zéro, la ligne qui vient d'être effacée peut recevoir de nouveau le signal d'entretien Vref par mise en conduction du commutateur T2 et blocage du commutateur T1 par exemple et/ou réglage du potentiel résiduel Vi égal à V1.When the slope of the decreasing slope signal portion Vpd tends towards zero, the line which has just been erased can receive the maintenance signal Vref by switching on the switch T2 and blocking of the T1 switch for example and / or adjustment of the residual potential Vi equal to V1.

Il est aussi possible que la ligne qui vient d'être effacée continue à recevoir le signal d'adressage Vad superposé au signal d'entretien Vref ce qui correspond à Vref + Vi.It is also possible that the line just deleted continues to receive the addressing signal Vad superimposed on the maintenance signal Vref ce which corresponds to Vref + Vi.

Il est envisageable que le chargement des capacités c ait lieu pendant un palier extrême du signal d'entretien Vref au lieu d'avoir lieu pendant un front. Cette variante est illustrée à la figure 5b qui montre un chronogramme du signal d'entretien Vref et du signal d'adressage Vad superposé au signal d'entretien Vref.It is possible that the loading of the capacities c takes place during an extreme plateau of the maintenance signal Vref instead of taking place during a front. This variant is illustrated in Figure 5b which shows a timing diagram of the maintenance signal Vref and the addressing signal Vad superimposed on the maintenance signal Vref.

Cette variante est intéressante lorsque les circuits d'adressage ligne ADL1, ADL2, ... ADLn sont équipés de moyens de découpage spécifiques pour réaliser, par exemple, des impulsions d'inscription multiples. Ces moyens de découpage sont connus en soit.This variant is interesting when the addressing circuits line ADL1, ADL2, ... ADLn are equipped with cutting means specific to carry out, for example, registration pulses multiple. These cutting means are known per se.

La ligne sélectionnée pour l'inscription reçoit le signal d'adressage Vad superposé au signal d'entretien Vref ce qui vaut Vref + Vd, le chargement des capacités c est intervenu au début du palier extrême Ph du signal d'entretien Vref pendant lequel a lieu l'inscription. Les impulsions d'inscription sont obtenues par les moyens de découpage intégrés aux circuits d'adressage ADL1, ADL2, ... ADLn. A l'issu du palier extrême, la ligne sélectionnée pour l'effacement peut recevoir le signal d'adressage Vad superposé au signal d'entretien Vref c'est-à-dire Vref + Vd puisque les capacités sont toujours chargées. Il suffit de commuter convenablement les commutateurs T1, T2 de la paire appartenant au module relié à cette ligne.The line selected for registration receives the signal addressing Vad superimposed on the maintenance signal Vref which is equal to Vref + Vd, capacity loading c occurred at the start of the extreme plateau Ph the maintenance signal Vref during which the registration takes place. The impulses registration are obtained by the cutting means integrated in the addressing circuits ADL1, ADL2, ... ADLn. At the end of the extreme landing, the line selected for erasure can receive the addressing signal Vad superimposed on the maintenance signal Vref, that is to say Vref + Vd since the capacities are always loaded. It is enough to switch the switches T1, T2 of the pair belonging to the module connected to this line.

Les autres lignes reçoivent uniquement le signal d'entretien Vref par commutation adéquate de la paire de commutateurs du module qui leur est associé.The other lines only receive the maintenance signal Vref by adequate switching of the pair of module switches which is associated.

Lorsque le signal d'entretien Vref atteint le palier extrême Pb qui suit celui où a eu lieu l'inscription, le commutateur I1 est bloqué ce qui engendre la décharge des capacités c, c'est-à-dire la portion de signal Vpd à pente décroissante.When the maintenance signal Vref reaches the extreme plateau Pb which follows the one where the registration took place, the switch I1 is blocked which generates the discharge of the capacitances c, that is to say the signal portion Vpd with decreasing slope.

Si les circuits d'adressage-ligne ADL1, ... ADLn ne sont pas équipés de moyens de découpage, il est possible que le circuit GSA générant le signal d'adressage Vad superposé au signal d'entretien Vref comporte ces moyens de découpage. La figure 6b illustre ce cas. Un second commutateur I2 est utilisé. Il est monté en parallèle avec le dispositif de régulation de courant Reg.If the line-addressing circuits ADL1, ... ADLn are not equipped with cutting means, it is possible that the GSA circuit generating the address signal Vad superimposed on the maintenance signal Vref includes these cutting means. Figure 6b illustrates this case. A second I2 switch is used. It is mounted in parallel with the current regulation Reg.

Le commutateur I2 est maintenu bloqué pendant l'effacement mais dès que les capacités c sont chargées en début du palier extrême du signal d'entretien Vref, il peut être actionné. En le rendant alternativement conducteur et bloqué on obtient les impulsions d'inscription.Switch I2 is kept blocked during erasure but as soon as the capacities c are loaded at the start of the extreme stage of the maintenance signal Vref, it can be activated. By making it alternately conductor and blocked, the registration pulses are obtained.

Un avantage du procédé selon l'invention est de ne pas nécessiter un signal d'entretien avec un palier médian d'où la possibilité de supprimer le circuit générant ce palier médian.An advantage of the process according to the invention is that it does not require a maintenance signal with a median level, hence the possibility of remove the circuit generating this median level.

Claims (13)

  1. Process for controlling a display panel (PDP) comprising cells (Ce) defined by the intersection of two networks of crossed electrodes (X1, X2) (Y1, Y2), these cells possessing two states, one written, the other erased, the process consisting:
    in applying a substantially square-wave sustain signal (Vref) on either side of a middle potential (V0) to all the cells (Ce), with the aim of producing a sustain discharge (Iden) with regard to the cells in the written state, at the termination of the edges (fn, fd) leading to an extreme porch (Pb, Ph),
    and in applying an addressing signal (Vad), superimposed on the sustain signal (Vref), in succession to the electrodes (Y1, Y2) of a network, this addressing signal comprising a semi-selective erase signal, generating, in respect of the cells (Ce) in the written state and which are linked to the selected electrode (Y1), an erase discharge (Idef),
    characterized in that the erase discharge (Idef) occurs at the termination of an edge (fd) leading to an extreme porch (Pb) of the sustain signal (Vref) alone, this erase discharge (Idef) disabling the sustain discharge (Iden) which should have occurred at the termination of this edge (fd) leading to the extreme porch of the sustain signal (Vref) alone.
  2. Process for controlling a display panel according to Claim 1, characterized in that the semi-selective erase addressing signal (Vad) is a voltage pulse (Ie) generated from an extreme porch (Pb) of the sustain signal (Vref), starting early enough to disable the sustain discharge (Iden).
  3. Process for controlling a display panel according to Claim 1, characterized in that the semi-selective erase addressing signal (Vad) comprises a signal portion (Vdp) with decreasing slope starting at the start of the extreme porch (Pb) of the sustain signal (Vref), based on an intermediate potential (Vd), referenced with respect to the potential (V1) of the extreme porch (Pb), lying between the potential (V1) of the extreme porch (Pb) and the middle potential (V0) and ending at a residual potential (Vi), referenced to the potential (V1) of the extreme porch, lying between the potential (V1) of the extreme porch and the intermediate potential (Vd).
  4. Process according to Claim 3, characterized in that the signal portion (Vpd) with decreasing slope is preceded by a signal portion which follows the edge (fd) leading to the extreme porch (Pb) of the sustain signal (Vref) offset by the intermediate potential (Vd).
  5. Control process according to one of Claims 3 or 4, the electrodes of a network receiving the sustain and addressing signals of one or more addressing circuits (ADL1, ADL2) which are equivalent to capacitances (c), characterized in that the signal portion (Vpd) with decreasing slope is obtained by discharging the capacitances (c).
  6. Control process according to Claim 5, characterized in that the signal portion (Vpd) with decreasing slope has an adjustable time constant.
  7. Control process according to one of Claims 5 or 6, characterized in that the charging of the capacitances (c) is performed during the edge (fd) leading to the extreme porch (Pb) of the sustain signal (Vref).
  8. Control process according to one of Claims 5 or 6, characterized in that the charging of the capacitances (c) is performed during the extreme porch (Ph) of the sustain signal (Vref) which precedes that during which the signal portion (Vpd) with decreasing slope takes place.
  9. Control process according to Claim 8, characterized in that the addressing signal (Vad) comprises a write-selective signal comprising one or more pulses produced by the charging of the capacitances (c).
  10. Image display device to which the process according to one of Claims 1 to 9 is applied, comprising:
    a display panel (PDP) whose cells (Ce) are situated at the intersection of two crossed networks of electrodes (Y1, Y2, X1, X2),
    one or more addressing circuits (ADL1, ADL2) linked to the electrodes (Y1, Y2) of a network, each circuit comprising an output stage comprising a pair of switches (T1, T2) per electrode to which it is linked, one of these switches (T2) receiving the sustain signal (Vref), the other (T1) the addressing signal (Vad) superimposed on the sustain signal (Vref),
    a generator of sustain signals (GSE) feeding the addressing circuits (ADL1, ADL2),
    a generator of addressing signals (GSA) feeding the addressing circuits (ADL1, ADL2),
    characterized in that the switch (T2) receiving the sustain signal (Vref) is dimensioned so as to be able to carry the sustain discharge current (Iden).
  11. Display device according to Claim 10, characterized in that the generator of addressing signals (GSA) comprises:
    a voltage source (Vd) referenced with respect to the sustain signal (Vref),
    a switch (I1) and a current regulation circuit (Reg) in series, which are connected across the terminals of the voltage source (Vd), the switch (I1) being connected to the output of the voltage source (Vd),
    the addressing circuits (ADL1, ADL2) equivalent to capacitances (c) being mounted in parallel with the current regulation circuit (Reg),
    the switch I1 being on in order to charge the capacitances (c) and off in order to discharge them.
  12. Display device according to Claim 11, characterized in that the generator of addressing signals (GSA) is equipped with means (I2) for producing multiple write pulses.
  13. Display device according to Claim 12, characterized in that the means (I2) for producing the multiple write pulses comprise a switch (I2) mounted in parallel with the current regulation circuit (Reg).
EP97901133A 1996-01-30 1997-01-21 Display panel control process and display device using such process Expired - Lifetime EP0877999B1 (en)

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FR9601060A FR2744275B1 (en) 1996-01-30 1996-01-30 METHOD FOR CONTROLLING A VIEWING PANEL AND VIEWING DEVICE USING THE SAME
FR9601060 1996-01-30
PCT/FR1997/000115 WO1997028526A1 (en) 1996-01-30 1997-01-21 Display panel control process and display device using such process

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FR2769115B1 (en) 1997-09-30 1999-12-03 Thomson Tubes Electroniques CONTROL PROCESS OF AN ALTERNATIVE DISPLAY PANEL INTEGRATING IONIZATION
FR2795218B1 (en) * 1999-06-04 2001-08-17 Thomson Plasma METHOD FOR ADDRESSING A MEMORY EFFECT VIEWING PANEL
US6963174B2 (en) * 2001-08-06 2005-11-08 Samsung Sdi Co., Ltd. Apparatus and method for driving a plasma display panel

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JPS60221796A (en) * 1984-04-18 1985-11-06 富士通株式会社 Driving of gas discharge panel
FR2572805A1 (en) 1984-11-06 1986-05-09 Thomson Csf METHOD FOR MEASURING THE CENTERING OF A CYLINDRICAL BAR IN A TRANSPARENT CYLINDRICAL COATING AND DEVICE FOR IMPLEMENTING SAID METHOD
FR2629245A1 (en) * 1988-03-25 1989-09-29 Thomson Csf METHOD FOR POINT-BY-POINT CONTROL OF A PLASMA PANEL
FR2635902B1 (en) 1988-08-26 1990-10-12 Thomson Csf VERY FAST CONTROL METHOD BY SEMI-SELECTIVE ADDRESSING AND SELECTIVE ADDRESSING OF AN ALTERNATIVE PLASMA PANEL WITH COPLANARITY MAINTENANCE
FR2635901B1 (en) 1988-08-26 1990-10-12 Thomson Csf METHOD OF LINE BY LINE CONTROL OF A PLASMA PANEL OF THE ALTERNATIVE TYPE WITH COPLANAR MAINTENANCE
FR2635900B1 (en) 1988-08-30 1990-10-12 Thomson Csf PLASMA PANEL WITH INCREASED ADDRESSABILITY
FR2648953A1 (en) 1989-06-23 1990-12-28 Thomson Tubes Electroniques PLASMA PANELS WITH DELIMITED DISCHARGES AREA
US5247288A (en) * 1989-11-06 1993-09-21 Board Of Trustees Of University Of Illinois High speed addressing method and apparatus for independent sustain and address plasma display panel
FR2662292B1 (en) 1990-05-15 1992-07-24 Thomson Tubes Electroniques METHOD FOR ADJUSTING THE BRIGHTNESS OF VISUALIZATION SCREENS.
JP3025598B2 (en) * 1993-04-30 2000-03-27 富士通株式会社 Display driving device and display driving method
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EP0877999A1 (en) 1998-11-18
DE69725706D1 (en) 2003-11-27
JP2000504123A (en) 2000-04-04
FR2744275B1 (en) 1998-03-06

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