EP0877999A1

EP0877999A1 - Display panel control process and display device using such process

Info

Publication number: EP0877999A1
Application number: EP97901133A
Authority: EP
Inventors: Serge Thomson-CSF S.C.P.I. SALAVIN; André Thomson-CSF S.C.P.I. DUNAND
Original assignee: Thomson CSF SA
Current assignee: Technicolor SA
Priority date: 1996-01-30
Filing date: 1997-01-21
Publication date: 1998-11-18
Anticipated expiration: 2017-01-21
Also published as: DE69725706D1; US6191763B1; JP2000504123A; FR2744275A1; EP0877999B1; WO1997028526A1; FR2744275B1; DE69725706T2

Abstract

The present invention relates to a display panel control process comprising cells defined by the intersection of two networks of crossed electrodes, said cells having two status, one inscribed the other one erased. The process comprises the application to all cells of a maintaining signal (Vref) which is crenelated on either side of a medial potential (V0) aimed at producing a maintain discharge at the cells in the inscribed status, at the end of fronts leading to an extreme step (Pb) and applying an addressing signal (Vad) superposed to the maintaining signal (Vref) successively at the electrodes of a network. The addressing signal comprises a semi-selective signal in the erasing mode which generates at the cells connected to the selected electrode an erasing discharge at the end of a front leading to an extreme step of the maintaining signal (Vref) which inhibits the maintaining discharge generated by the maintaining signal (Vref) alone. Application particularly to plasma display panel control.

Description

METHOD FOR CONTROLLING A VIEWING PANEL AND VIEWING DEVICE USING THE SAME

The present invention relates to a method for controlling a display panel with a memory effect and in particular those of large size. Its purpose is to increase the speed of image renewal.

Recent developments in large-size plasma display panels or for high-definition television have led to higher resolution and an increasingly rapid image renewal rate.

The display panels have a large number of cells arranged in a matrix form in rows and columns. Each cell is formed by the gas space located at the intersection of two electrodes belonging to two networks of orthogonal electrodes and is subjected to control signals formed by the difference of the voltages applied to the two electrodes between which it is located.

The operating principle of memory effect panels is generally as follows. An alternative maintenance signal is applied to all of the lines, substantially in time slots. It has the effect of maintaining each cell in the state which has been previously assigned to it by an addressing signal. It generates a maintenance discharge at the level of the cells in the registered state.

Addressing is generally done by line-by-line scanning. All the cells of a selected row are controlled simultaneously by a more or less complex semi-selective operation to be "erased" and this operation is followed by a selective operation during which cells of the row can be "registered". The semi-selective operation followed by the selective operation is accomplished with a time offset from one line to another.

To obtain 2 ^to half-tones, it is necessary to scan the screen once during the duration T of a complete image. If n is the number of lines on the screen and t is the duration during which a line is addressed, we have the condition:

nta≤ T For example, in a high definition television type panel operating at 50 Hz with 8 levels of halftone and 1000 lines:

T = 20 ms

This duration is close to the physical limits of the duration necessary for the realization of a discharge. If the number of lines and / or the number of halftones has to increase further, a gain in addressing time becomes essential to satisfy this increase in the speed of image renewal.

In an alternating type plasma display panel, the discharge current is limited by a capacitor in series with each cell to avoid destruction of the display panel if the power source is not limited in current. This capacitor is generally produced by covering the network of electrodes with an enamel dielectric layer for example. The deletion of a cell consists in removing the charges stored on the dielectric at the level of the cells of the line considered.

To obtain erasure, a voltage is generally applied to the electrode forming the corresponding line, which generates a discharge, the intensity of which is chosen so that the charges stored opposite recombine with one another to cancel each other out. The deletion of a cell creates a discharge current whose intensity is substantially equal to half that of the maintenance current because there is transfer of about half of the usual maintenance charges.

Currently the semi-selective erasure operation is carried out in different ways.

The maintenance signals are generally a succession of voltage slots, between two extreme high and low levels with possibly a median level. The semi-selective erase address signal has the form of a voltage pulse, of suitable amplitude to create an erasure discharge, which is superimposed on the slots of the maintenance signal. This semi-selective erase addressing signal actually increases the duration of a maintenance cycle compared to that necessary to ensure only maintenance.

FIGS. 1a, 1b, 1c show timing diagrams of the maintenance signal and of the semi-selective erasure addressing signal in various cases currently used. The selective registration addressing sign is not shown.

In FIG. 1a, the maintenance signal Vref in solid lines comprises two extreme stages, one corresponding to the low potential V1 (negative) and the other to the high potential V2 (these stages being established on both sides). another of a median or reference VO potential which is often the potential of the mass. This maintenance signal Vref generates discharges at the level of the cells in the state entered just after an inversion of polarity, that is to say after an edge leading to an extreme plateau. The semi-selective erase addressing signal is a voltage pulse represented by dotted lines, superimposed on the maintenance signal. The erase pulse is generated during a low plateau. The duration of the maintenance cycle is then worth:

tca = tbla + tma + tb2a + tha

with:

- tbla duration of the low plateau before the erase pulse,

- tma duration of the erase pulse, - tb2a duration of the low plateau after the erase pulse,

- tha duration of the upper stage.

In FIG. 1b, the maintenance signal Vref comprises a median level of duration tmb situated between two low levels of duration tb1 b, tb2b. The erasure semi-selective addressing signal is a pulse superimposed on the maintenance signal Vref, generated during this median level. Its amplitude Vpb is less than that Vpa shown in FIG. 1a.

The duration tcb of the maintenance cycle is then worth: tcb = tb1b + tmb + tb2b + thb

In FIG. 1c, the maintenance signal Vref comprises a median level of duration tcm between a low level of duration tbc and a high level of duration the. The erasure semi-selective addressing signal is a pulse of amplitude Vpc generated from this median level. The amplitude

Vpc is less than that of Figure 1a.

The duration tec of the maintenance cycle is then worth:

tec = tbc + tmc + the

The disadvantage of this type of operation is that the duration of the maintenance cycle is longer than that which is normally sufficient to ensure maintenance. In the cases represented in FIGS. 1a, 1b, 1c this duration is increased by the duration tma, tmb, tmc, respectively.

The configuration where the erasure pulse is generated from a middle level has a drawback linked to the presence of the middle level during the maintenance cycle. Charges can disappear during this median level, this disappearance involves a partial loss of the memory of the panel.

In addition, the generation of the median level requires a specific circuit.

The configuration where the erase pulse is generated from the bottom bearing has a drawback. The amplitude of the pulse to be generated remains high and this pulse can only be generated from a relatively expensive specific circuit.

The present invention therefore proposes to integrate the time of the semi-selective erasure addressing in the maintenance cycle without increasing the duration thereof. For this, the present invention is a method of controlling a display panel comprising cells defined at the intersection of two networks of crossed electrodes, these cells comprising two states, one written, the other erased. It consists in applying to all the cells a maintenance signal substantially in time slots on either side of a median potential, aiming to produce a maintenance discharge at the level cells in the state registered at the end of the fronts leading to an extreme plateau and applying an addressing signal superimposed on the maintenance signal successively to the electrodes of a network. The addressing signal comprises a semi-selective erasure signal which generates for the cells in the written state an erasure discharge.

The erasure discharge occurs at the end of a front leading to an extreme plateau of the maintenance signal. This erasure discharge inhibits the maintenance discharge which should have been generated by the maintenance signal alone. The invention will be better understood on reading the following description of embodiments, given by way of nonlimiting examples and illustrated by the attached figures which represent:

FIGS. 1a, 1b, 1c (already described): chronograms of the maintenance and semi-selective erasing addressing signals applied to a display panel controlled in a conventional manner,

FIG. 2: a display device to which the method according to the invention applies,

FIGS. 3a, 3c: chronograms of the maintenance and semi-selective erasure addressing signals applied to two lines of a display panel controlled by the method of the invention,

FIG. 3b: a chronogram of the discharge currents appearing on the line receiving the signals of FIG. 3a,

FIGS. 4a, 4b: the directions of the discharge currents flowing in an output stage module of an addressing circuit to which a conventional control method and the method according to the invention apply,

FIGS. 5a, 5b: chronograms of the maintenance and addressing signals applied to a line of a display panel controlled by two variants of the method according to the invention,

- Figures 6a, 6b: display devices to which the variants of the method according to the invention apply.

FIG. 2 schematically represents an image display device to which the method according to the invention applies. This display device comprises a PAP plasma display panel and control means. The PAP display panel comprises a first array of row electrodes Y1 to Y4 crossed with a second array of column electrodes X1 to X4. Each electrode crossing corresponds to a Ce cell. The cells are arranged in a matrix. Each line electrode Y1 to Y4 is connected to a line addressing circuit ADL1, ADL2 or "driver-line". For large panels, there are usually several. In the example shown, there are two which each supply a group of lines with maintenance and addressing signals.

Each column electrode X1 to X4 is connected to a column addressing circuit ADC1, ADC2 or "driver-column". There are two in the example shown. The column addressing circuits generate pulses which mask those generated by the selective addressing signal when writing on a selected line, at the cells Ce of this line which must not be written. The line addressing circuits ADL1, ADL2 receive the maintenance signal Vref from a generator of maintenance signals GSE and the addressing signal Vad superimposed on the maintenance signal Vref from a generator of addressing signals GSA .

Figures 3a, 3c show a timing diagram of the signals received by two lines of the PAP panel of Figure 2, selected successively, referenced M, 12. The PAP panel is controlled by the method according to the invention. FIG. 3b is a chronogram of the discharges occurring on line 11.

All the electrodes of a network, here all the line electrodes simultaneously receive the maintenance signal Vref (shown in solid lines). This signal Vref is substantially in time slots, with extreme high bearings Ph at potential V2 and low Pb at potential V1 located on either side of median bearings Pm, at median potential VO. The duration of the middle stops is relatively short. The middle bearings Pm may be absent from the maintenance signal Vref. The extreme bearings Ph, Pb are separated by rising edges fm and falling fd. The maintenance signal Vref causes iden maintenance discharges at the level of cells Ce in the registered state. These Iden discharges occur at the end of a time interval Δt after the start of an extreme plateau Ph, Pb. In the panels to color viewing plasma, the time interval Δt is a few hundred nanoseconds.

According to the method according to the invention, the addressing signal Vad (shown in dotted lines) superimposed on the maintenance signal Vref is applied to the electrodes of a network each in turn. In the example, it is applied to the line electrodes. It is conceivable that it is applied to the column electrodes. The maintenance signal Vref could also be applied to the column electrodes.

The addressing signal Vad is broken down into a semi-selective erasing signal and a selective registration signal which does not interest us for the moment. The semi-selective erase addressing signal is an erase pulse the amplitude Vp generated from an extreme plateau Pb, Ph of the maintenance signal Vref at the end of a time interval Δt1 after the start of the payier extreme Pb, Ph. This time interval is such that:

0 <Δt1 <Δt

In FIGS. 3, the pulse I1 of the addressing signal Vad is generated from an extreme low level Pb of the maintenance signal Vref. The erase pulse generates an erase discharge

Idef at the level of all cells Ce of the selected line in the registered state and this discharge Idef inhibits that iden which should have been generated by the maintenance signal Vref alone. The erase pulse le may last until the rising edge fm following the maintenance signal Vref or be shorter.

The values of the time interval Δt1 and of the amplitude Vp of the erasure pulse are chosen so that the charges stored opposite on the dielectric covering the electrodes of the cells Ce in the registered state of the selected line leave their support and recombine in the gas space. The amplitude Vp represented is substantially equal to half that of the maintenance signal Vref.

Instead of the erasure pulse being generated from an extreme low level Pb, it can be generated from an extreme high level Ph. In both cases, it has a payer which is closer to the median potential VO that the extreme stages Ph, Pb of the maintenance signal Vref are not.

In FIG. 3a, an erase pulse 1c is generated from the first low plateau Pb of the maintenance signal Vref while in FIG. 3c it is generated from the next low plateau Pb. The selective registration addressing signal can take place, in a conventional manner, for a line selected from the high level Ph following that during which the semi-selective erasure signal intervened.

FIG. 4a schematically represents an output stage module of an ADL line addressing circuit as well as the directions of the currents which flow through it when the display panel to which it is connected is conventionally controlled. FIG. 4b represents the same module to which the method according to the invention applies.

The line addressing circuit ADL generally supplying several lines, has an output stage comprising as many modules, like that of FIGS. 4, as there are lines.

Each module comprises a pair of switches T1, T2 having a common point A which is connected to the line electrode of the corresponding line 11. The line is electrically equivalent to a capacity Cp. One of the switches T2 receives the maintenance signal Vref and the other T1 receives the addressing signal Vad superimposed on the maintenance signal Vref. The switches T1, T2 are generally MOS transistors. They are switched alternately. When the signal Vref applies the switch T1 is blocked and the switch T2 conductor, the reverse occurs when the signal Vad superimposed on the signal Vref applies.

A diode d1 is mounted in parallel with the switch T1, a diode d2 with the switch T2. The cathode of diode d2 and the anode of diode d1 are connected to common point A.

In the case of the conventional erase command, the semi-selective erase addressing signal Vad superimposed on the maintenance signal is applied to a selected line for times when the maintenance signal Vref alone does not generate discharge on the other lines.

The discharge current Idenl generated by the maintenance signal Vref during an extreme low plateau Pb passes through the diode d1 and the current Iden2 discharge generated during an extreme high plateau Ph passes through diode d2 (see Figure 4a).

When the display panel is controlled by the method according to the invention, the semi-selective erasing address signal Vad superimposed on the maintenance signal Vref applies to a selected line while the maintenance signal Vref alone generates maintenance discharges on the other lines controlled by the same line addressing circuit. The maintenance discharge current Idenl generated during an extreme low plateau on the lines not selected for the semi-selective erasing addressing can no longer pass through the diode d1 because of the presence at this instant of the addressing signal. Vad superimposed on the maintenance signal Vref on the cathode of diode d1.

The maintenance discharge current Idenl flows through the switch T2 receiving the maintenance signal Vref alone and which is conductive. Consequently, the switch T2 will be dimensioned to support this Idenl maintenance discharge current (see FIG. 4b).

The maintenance discharge current Iden2 generated during an extreme high plateau passes through the diode d2 as in FIG. 4a.

Because of the parasitic current which inevitably appears when one switches switches, it is preferable to separate in time the commutations of the two switches T1, T2 of the pair to avoid a current of double conduction in the two switches.

At the level of the module supplying the line selected for erasure, the switch T2 is conductive and the switch T1 is blocked. Erase discharge current Idef flows through the switch

T2 and is interrupted when the switch T1 is switched to send the signal back to the median pay (see Figure 3a).

FIG. 5a represents a timing diagram of the maintenance signal

Vref and the semi-selective erasing address signal Vad superimposed on the maintenance signal and applied to a selected electrode of a display panel controlled by a variant of the method according to the invention.

The semi-selective erasing address signal Vad comprises a decreasing slope portion Vpd, generated from an intermediate potential Vd, referenced with respect to the potential V1 of the extreme plateau and comprised between the potential V1 and the median potential VO maintenance signal Vref, this portion Vpd ending at a residual potential Vi referenced with respect to the potential V1 between said potential V1 and the intermediate potential Vd. The residual potential Vi can be zero. This decreasing slope portion Vpd begins at the start of said extreme plateau. This portion Vpd of decreasing slope signal inhibits the maintenance discharge which should have been generated by the maintenance signal Vref in the absence of a semi-selective addressing signal Vad. This portion Vpd of decreasing slope signal produces an erasure discharge at the level of the registered cells of the selected line. In FIG. 5a, the portion Vpd of signal with decreasing slope begins at the same time as an extreme low level of the maintenance signal Vref. The semi-selective erase address signal Vad comprises, before the decreasing slope signal portion Vpd, a portion which follows the maintenance signal Vref with the offset of Vd. The semi-selective erase address signal begins during the front fd of the maintenance signal Vref which leads to the extreme low plateau Pb during which the erasure discharge will appear.

At the end of the portion Vpd of decreasing slope signal, when the slope tends towards zero, only the maintenance signal Vref applies to the line which has just been erased. At the end of the next rising edge of the maintenance signal Vref can then begin selective addressing in registration in a conventional manner. This addressing is not shown in FIG. 5a.

The variation of the slope of the decreasing slope signal portion Vpd is adjustable so as to effectively stop the maintenance discharge which should occur in the absence of the addressing signal.

The fact of using the portion Vpd of decreasing slope signal makes it possible to better adapt the voltage triggering the erasure discharge to all the display panel cells than in the variant shown in FIG. 3a. Because, inevitably, a display panel is not homogeneous, that is to say that the voltage which produces a discharge is not necessarily the same from one cell to another.

FIG. 6a schematically shows an electronic circuit GSA making it possible to generate an addressing signal Vad superimposed on the maintenance signal Vref such as that shown in FIG. 5a. This circuit includes a voltage source Vd referenced with respect to the potential of the maintenance signal Vref. The maintenance signal Vref is generated by a circuit for generating the conventional GSE maintenance signal. The output voltage of the voltage source Vd supplies all the line addressing circuits ADL1, ADL2, ... ADLn of the PAP panel which also receive the maintenance signal Vref.

These line addressing circuits ADL1, ADL2, ... ADLn are electrically equivalent each to a capacity c. The capacities c of the line addressing circuits ALD1, ADL2, are connected in parallel. The addressing circuits ADL1, ADL2, ... ADLn are each connected to several electrodes of the PAP panel.

A switch 11 is mounted between the output of the voltage source Vd and the line addressing circuits ADL1, ADL2, ... ADLn.

The signal supplied by the voltage source Vd follows the maintenance signal Vref with an offset of Vd.

A current regulating device Reg is mounted in series with the switch 11, the assembly being mounted in parallel with the voltage source Vd. This Reg device can be produced either by a potentiometer which makes it possible to adjust the time constant of the portion Vpd of signal with decreasing slope either by a current generator which allows the adjustment of the slope.

The portion Vpd of decreasing slope signal is generated by discharging the capacitors c of the line addressing circuits ADL1, ADL1,

... ADLn and this discharge is obtained by blocking the switch 11. The addressing signal Vad superimposed on the maintenance signal Vref applied to the selected line to be deleted then has the value:

Vref + V d - = ^ - I idt ∑ ^c

Capacities c must be loaded beforehand. The loading is obtained by putting the switch 11 in the conducting state.

The loading of the capacities c can take place at different times. On the timing diagram of FIG. 5a, the loading of the capacities takes place during a falling edge fd of the maintenance signal.

Initially, during this falling edge fd, all the lines receive the maintenance signal Vref. Then the line selected for erasure will receive the semi-selective erasing address signal Vad superimposed on the maintenance signal Vref. It suffices to block the switch T2 of the module of the output stage connected to this line, to make the switch T1 conductive and to make the switch 11 of the GSA circuit conductive. The loading of the capacities c begins. The dead time at the switches T1, T2 of the pair is not necessary because the switching takes place before the loading of the capacitances c is completed.

In FIG. 5a, the signal portion corresponding to the loading of the capacities c carries the reference Vc. When the loading is finished, the selected line receives the addressing signal Vad superimposed on the maintenance signal Vref which is equal to Vref + Vd. It is offset by

Vd with respect to the maintenance signal Vref.

The discharge of capacities begins when the maintenance signal

Vref alone reaches the Pb cashier. When the slope of the decreasing slope signal portion Vpd tends towards zero, the line which has just been erased can again receive the maintenance signal Vref by switching on the switch T2 and blocking of the T1 switch for example and / or adjustment of the residual potential

Vi equal to VL li is also possible that the line which has just been erased continues to receive the addressing signal Vad superimposed on the maintenance signal Vref which corresponds to Vref + Vi.

It is conceivable that the loading of the capacities c takes place during an extreme plateau of the maintenance signal Vref instead of taking place during an edge. This variant is illustrated in FIG. 5b which shows a timing diagram of the maintenance signal Vref and of the addressing signal Vad superimposed on the maintenance signal Vref.

This variant is advantageous when the line addressing circuits ADL1, ADL2, ... ADLn are equipped with cutting means. specific to carry out, for example, multi-registration pulses. These cutting means are known per se.

The line selected for registration receives the addressing signal Vad supeφosed to the maintenance signal Vref which is worth Vref + Vd, the loading of the capacities c occurred at the start of the extreme plateau Ph of the maintenance signal Vref during which place the registration. The recording pulses are obtained by the chopping means integrated into the addressing circuits ADL1, ADL2, ... ADLn. At the end of the extreme plateau, the line selected for erasure can receive the addressing signal Vad supeφosed to the maintenance signal Vref, that is to say Vref + Vd since the capacities are always loaded. It suffices to switch the switches T1, T2 of the pair belonging to the module connected to this line properly.

The other lines receive only the maintenance signal Vref by adequate switching from the pair of switches of the module associated with them.

When the maintenance signal Vref reaches the extreme level Pb which follows that at which the registration took place, the switch 11 is blocked which generates the discharge of the capacities c, that is to say the signal portion Vpd to decreasing slope. If the line-addressing circuits ADL1,... ADLn are not equipped with cutting means, it is possible that the GSA circuit generating the addressing signal Vad supeφosed to the maintenance signal Vref includes these cutting means. Figure 6b illustrates this case. A second switch 12 is used. It is mounted in parallel with the Reg current control device.

The switch 12 is kept blocked during erasure but as soon as the capacities c are loaded at the start of the extreme plateau of the maintenance signal Vref, it can be actuated. By making it alternately conductive and blocked, the registration pulses are obtained. An advantage of the method according to the invention is that it does not require a maintenance signal with a middle landing, hence the possibility of eliminating the circuit generating this middle landing.

Claims

1. Method for controlling a display panel (PAP) comprising cells (Ce) defined by the intersection of two crossed electrode networks (X1, X2) (Y1, Y2), these cells having two states l ' one registered, the other deleted, the process consisting in: - applying to all cells (Ce) a maintenance signal (Vref) substantially in slots on either side of a median potential (VO), aiming at produce a maintenance discharge (Iden) at the level of the cells in the registered state, at the end of the fronts (fn, fd) leading to an extreme plateau (Pb, Ph), - and to apply an addressing signal (Vad) superimposed on the maintenance signal (Vref), successively on the electrodes (Y1, Y2) of a network, this addressing signal comprising a semi-selective erasure signal, generating for the cells (Ce) to the registered state connected to the selected electrode (Y1) an erasure discharge (Idef), characterized in that the erasure discharge (Idef) is produced at the end of a front (fd) leading to an extreme plateau (Pb) of the maintenance signal (Vref) alone, this erasure discharge (Idef) inhibiting the maintenance discharge (Iden) which should have occur at the end of this front (fd) leading to the extreme plateau of the maintenance signal (Vref) alone.

2. Method for controlling a display panel according to claim 1, characterized in that the semi-selective erasing addressing signal (Vad) is a voltage pulse (le) generated from an extreme level (Pb) of the maintenance signal (Vref), starting early enough to inhibit the maintenance discharge (Iden).

3. Method for controlling a display panel according to claim 1, characterized in that the semi-selective erasure addressing signal (Vad) comprises a portion (Vdp) of signal with decreasing slope starting at the start of the extreme plateau (Pb) of the maintenance signal (Vref), from an intermediate potential (Vd), referenced with respect to the potential (V1) of the extreme plateau (Pb), between the potential (V1) of the extreme plateau (Pb) ) and the median potential (VO) and ending at a potential residual (Vi), referenced to the potential (V1) of the extreme plateau, between the potential (V1) of the extreme plateau and the intermediate potential (Vd).

4. Method according to claim 3, characterized in that the portion (Vpd) of decreasing slope signal is preceded by a portion of signal which follows the front (fd) leading to the extreme plateau (Pb) of the maintenance signal (Vref ) offset from the intermediate potential (Vd).

5. Control method according to one of claims 3 or 4, the electrodes of a network receiving the maintenance and addressing signals from one or more addressing circuits (ADL1, ADL2) equivalent to capacities ( c), characterized in that the portion (Vpd) of decreasing slope signal is obtained by the discharge of the capacitors (c).

6. Control method according to claim 5, characterized in that the signal portion (Vpd) with decreasing slope has an adjustable time constant.

7. Control method according to one of claims 5 or 6, characterized in that the charging of the capacities (c) takes place during the front

(fd) leading to the extreme plateau (Pb) of the maintenance signal (Vref).

8. Control method according to one of claims 5 or 6, characterized in that the charging of the capacities (c) takes place during the extreme plateau (Ph) of the maintenance signal (Vref) which precedes that during which a place the portion (Vpd) of signal with decreasing slope.

9. Control method according to claim 8, characterized in that the addressing signal (Vad) comprises a selective signal in writing comprising one or more pulses produced from the load of the capacitors (c).

10. Image display device to which the method according to one of claims 1 to 9 applies, comprising: - a display panel (PAP) whose cells (Ce) are located at the intersection of two crossed electrode networks (Y1, Y2, X1, X2),

- one or more addressing circuits (ADL1, ADL2) connected to the electrodes (Y1, Y2) of a network, each circuit comprising an output stage comprising a pair of switches (T1, T2) per electrode to which it is connected , one of the switches (T2) receiving the maintenance signal (Vref), the other (T1) the addressing signal (Vad) superimposed on the maintenance signal (Vref), - a signal generator maintenance (GSE) supplying the addressing circuits (ADL1, ADL2),

- an address signal generator (GSA) supplying the address circuits (ADL1, ADL2), characterized in that the switch (T2) receiving the maintenance signal (Vref) is dimensioned to support the discharge current ( Iden) maintenance.

11. Display device according to claim 10, characterized in that the addressing signal generator (GSA) comprises: - a voltage source (Vd) referenced with respect to the maintenance signal (Vref),

- a switch (11) and a current regulation circuit (Reg) in series, mounted across the voltage source (Vd), the switch (11) being connected to the output of the voltage source (Vd), - the addressing circuits (ADL1, ADL2) equivalent to capacities

(c) being mounted in parallel with the current regulation circuit (Reg),

the switch 11 being conductive for charging the capacities (c) and blocked for discharging them.

12. Display device according to claim 11, characterized in that the addressing signal generator (GSA) is equipped with means (12) for producing multiple writing pulses.

13. Display device according to claim 12, characterized in that the means (12) for producing the multiple pulses registration include a switch (12) mounted in parallel with the current regulation circuit (Reg).