EP0877999B1 - Ansteuerungsverfahren für eine anzeigetafel und anzeigevorrichtung, die dieses verfahren verwendet - Google Patents

Ansteuerungsverfahren für eine anzeigetafel und anzeigevorrichtung, die dieses verfahren verwendet Download PDF

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Publication number
EP0877999B1
EP0877999B1 EP97901133A EP97901133A EP0877999B1 EP 0877999 B1 EP0877999 B1 EP 0877999B1 EP 97901133 A EP97901133 A EP 97901133A EP 97901133 A EP97901133 A EP 97901133A EP 0877999 B1 EP0877999 B1 EP 0877999B1
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EP
European Patent Office
Prior art keywords
signal
addressing
vref
extreme
sustain
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EP97901133A
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English (en)
French (fr)
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EP0877999A1 (de
Inventor
Serge Thomson-CSF S.C.P.I. SALAVIN
André Thomson-CSF S.C.P.I. DUNAND
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Technicolor SA
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Thomson SA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/297—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using opposed discharge type panels

Definitions

  • the present invention relates to a control method a memory effect display panel and especially those of large cut. It aims to increase the speed of image renewal.
  • the display panels have a large number of cells arranged in matrix form in rows and columns.
  • Each cell consists of the gas space located at the intersection of two electrodes belonging to two networks of orthogonal electrodes and are found subject to control signals constituted by the difference of voltages applied to the two electrodes between which it is located.
  • a signal is applied to all the lines of alternative maintenance substantially in niches. It has the effect of maintaining each cell in the state previously assigned to it by a signal addressing. It generates at the level of the cells in the registered state a discharge maintenance.
  • Addressing is generally done by line-by-line scanning. All cells in a selected row are ordered simultaneously by a more or less complex semi-selective operation to be “erased” and this operation is followed by a selective operation during which cells of the line can be "registered". The operation semi-selective followed by the selective operation is accomplished with a time shift from one line to another.
  • T 20 ms t ⁇ 20 8X1000 ⁇ 2.5 ⁇ s
  • This duration is close to the physical limits of the duration necessary for the discharge.
  • the discharge current is limited by a capacitor in series with each cell to avoid destruction of the display panel if the source power supply is not limited by current.
  • This capacitor is generally achieved by covering the electrode network with a layer enamel dielectric for example.
  • Erasing a cell consists of deleting the charges stored on the dielectric at the level of the cells of the line considered.
  • the maintenance signals are generally a succession of voltage slots, between two extreme high and low levels with possibly a median level.
  • the semi-selective address signal of erasure in the form of a voltage pulse, of suitable amplitude to create an erasure discharge, which is superimposed on the slots of the maintenance signal.
  • This semi-selective erase addressing signal comes in increases the duration of a maintenance cycle compared to that required for maintenance only.
  • Patent application EP-A1-0 337 833 illustrates the case where the erasure signal increases the duration of the maintenance cycle compared to that required for maintenance.
  • Figures 1a, 1b, 1c show timing diagrams of the signal and the semi-selective erase address signal in different cases currently used. The selective addressing signal registration is not shown.
  • the maintenance signal Vref comprises a level median of duration tmb located between two low landings of duration tb1b, tb2b.
  • the semi-selective erase addressing signal is a pulse superimposed on the maintenance signal Vref, generated during this stage median. Its amplitude Vpb is less than that Vpa represented on the Figure 1a.
  • tcb tb1b + tmb + tb2b + thb
  • the maintenance signal Vref comprises a level median of duration tcm between a low level of duration tbc and an upper level of duration thc.
  • the semi-selective erase addressing signal is a amplitude pulse Vpc generated from this median level.
  • the amplitude Vpc is less than that of Figure 1a.
  • the configuration where the erase pulse is generated from downstairs has one drawback.
  • the amplitude of the pulse to generate remains important and this impulse can only be generated from a relatively expensive specific circuit.
  • the present invention therefore proposes to integrate the time of semi-selective erasure addressing in the maintenance cycle without as much to increase the duration.
  • the present invention is a control method a display panel comprising cells defined at the intersection of two networks of crossed electrodes, these cells comprising two states, one registered, the other deleted. It involves applying to all cells a maintenance signal substantially in slots on both sides of a median potential, aimed at producing a maintenance discharge at the level cells in the state registered at the end of the fronts leading to an extreme plateau and applying an addressing signal superimposed on the maintenance signal successively to the electrodes of a network.
  • the addressing signal includes a semi-selective erasure signal which generates for the cells to the state registers an erasure discharge.
  • the erasure discharge occurs at the end of a leading front at an extreme level of the maintenance signal. This erasure discharge inhibits the maintenance discharge that should have been generated by the signal maintenance only.
  • FIG. 2 schematically represents a device for image display to which the method according to the invention applies.
  • This display device includes a PAP display panel to plasma and control means.
  • the PAP display panel has a first network of line electrodes Y1 to Y4 crossed with a second network of electrodes columns X1 to X4. Each cell crossing corresponds to a cell This.
  • the cells are arranged in a matrix.
  • Each Y1 line electrode at Y4 is connected to a line addressing circuit ADL1, ADL2 or "line driver".
  • Each column electrode X1 to X4 is connected to a circuit column addressing ADC1, ADC2 or "driver-column". There are two on the example shown.
  • Column addressing circuits generate pulses that mask those generated by the selective addressing signal in writing on a selected line, at the Ce cells of this line not to be entered.
  • Line addressing circuits ADL1, ADL2 receive the signal Vref maintenance of a GSE maintenance signal generator and the signal Vad addressing superimposed on the maintenance signal Vref of a generator GSA addressing signals.
  • Figures 3a, 3c show a timing diagram of the signals received by two lines of the PAP panel of figure 2, selected successively, referenced I1, I2.
  • the PAP panel is controlled by the process according to the invention.
  • Figure 3b is a timing diagram of discharges occurring on line I1.
  • All the electrodes of a network here all the electrodes of line simultaneously receive the maintenance signal Vref (shown in lines full).
  • This signal Vref is substantially in time slots, with steps extreme high Ph at potential V2 and low Pb at potential V1 located on the other side and other median bearings Pm, at the median potential V0.
  • the duration of middle stops is relatively short.
  • the middle bearings Pm can be absent from the maintenance signal Vref.
  • the extreme bearings Ph, Pb are separated by rising fm and falling fd edges.
  • the maintenance signal Vref causes Iden maintenance discharges at Ce cells at the registered state. These Iden discharges occur after an interval of time ⁇ t after the start of an extreme plateau Ph, Pb. In the panels to color viewing plasma, the time interval ⁇ t is worth a few hundreds of nanoseconds.
  • the addressing signal Vad (shown in dotted lines) superimposed on the maintenance signal Vref is applied to the electrodes of a network each in turn.
  • the addressing signal Vad (shown in dotted lines) superimposed on the maintenance signal Vref is applied to the electrodes of a network each in turn.
  • the line electrodes It is conceivable that it will be applied to column electrodes.
  • the maintenance signal Vref could also be applied to the column electrodes.
  • the addressing signal Vad is broken down into a semi-selective erasing signal and a selective registration signal which does not interest us for the moment.
  • the semi-selective erase address signal is an erase pulse Ie of amplitude Vp generated from an extreme plateau Pb, Ph of the maintenance signal Vref after a time interval ⁇ t1 after the start of the plateau extreme Pb, Ph. This time interval is such that: 0 ⁇ t1 ⁇ t
  • the pulse le of the addressing signal Vad is generated from an extreme low level Pb of the maintenance signal Vref.
  • the erase pulse generates an erase discharge Idef at the level of all Ce cells of the row selected in the report registered and this Idef discharge inhibits the Iden discharge which should have been generated by the maintenance signal Vref only.
  • the erase pulse can last up to the next rising edge fm of the maintenance signal Vref or be more short.
  • the values of the time interval ⁇ t1 and the amplitude Vp of the erasure pulse are chosen so that the charges stored opposite on the dielectric covering the electrodes of the Ce cells in the state subscribed from the selected line leave their support and recombine in gas space.
  • the amplitude Vp represented is substantially equal to the half that of the maintenance signal Vref.
  • the erase pulse is generated from a extreme low level Pb, it can be generated from an extreme high level Ph. In both cases, it has a bearing which is closer to the median potential V0 as the extreme stages Ph, Pb of the maintenance signal They are not.
  • an erasure pulse le is generated from the first low landing Pb of the maintenance signal Vref while on the Figure 3c it is generated from the next low level Pb.
  • the signal selective registration addressing can take place, in a conventional manner, for a line selected from the upper level Ph following that during which the semi-selective erase signal intervened.
  • FIG. 4a schematically represents a module of the output stage of an ADL line addressing circuit as well as the currents flowing through it when the display panel to which it is connected is conventionally controlled.
  • Figure 4b shows the same module to which the method according to the invention applies.
  • the ADL line addressing circuit generally supplying several lines, has an output stage comprising as many modules, like that of Figures 4, that lines.
  • Each module has a pair of switches T1, T2 having a common point A which is connected to the line electrode of line I1 corresponding.
  • the line is electrically equivalent to a capacity Cp.
  • One of the switches T2 receives the maintenance signal Vref and the other T1 receives the addressing signal Vad superimposed on the maintenance signal Vref.
  • the switches T1, T2 are generally MOS transistors. They are switched alternately. When the Vref signal applies T1 switch is blocked and the T2 conductive switch is the reverse which occurs when the signal Vad superimposed on the signal Vref applies.
  • a diode d1 is mounted in parallel with the switch T1, a diode d2 with the switch T2.
  • the cathode of diode d2 and the anode diode d1 are connected to the common point A.
  • the signal semi-selective erasing address Vad superimposed on the maintenance signal is applied to a selected line for times when the signal maintenance Vref alone does not generate a discharge on the other lines.
  • the semi-selective addressing signal Vad delete superimposed on the maintenance signal Vref applies on a line selected while the maintenance signal Vref alone generates maintenance discharges on other lines controlled by the same circuit line addressing.
  • the maintenance discharge current iden1 generated during an extreme low level on lines not selected for addressing semi-selective erasure can no longer go through diode d1 because of the presence of the addressing signal Vad superimposed on the signal at this instant of maintenance Vref on the cathode of diode d1.
  • the Iden1 maintenance discharge current flows through the switch T2 receiving the maintenance signal Vref alone and which is driver. Consequently, the switch T2 will be sized to withstand this Iden1 maintenance discharge current (see Figure 4b).
  • the Iden2 maintenance discharge current generated during a extreme high stage passes through diode d2 as in FIG. 4a.
  • switch T2 At the level of the module supplying the line selected for erasure, switch T2 is conductive and switch T1 is blocked. Erase discharge current Idef flows through the switch T2 and is interrupted when the switch T1 is switched to make raise the signal to the middle level (see figure 3a).
  • FIG. 5a represents a timing diagram of the maintenance signal Vref and the semi-selective erase addressing signal Vad superimposed on the maintenance signal and applied to a selected electrode of a panel display controlled by a variant of the method according to the invention.
  • the semi-selective erase addressing signal Vad comprises a decreasing slope portion Vpd, generated from a potential Vd intermediate, referenced with respect to the potential V1 of the extreme bearing and between the potential V1 and the median potential V0 of the maintenance signal Vref, this portion Vpd ending at a residual potential Vi referenced by relation to potential V1 between said potential V1 and the potential intermediate Vd.
  • the residual potential Vi can be zero.
  • This Vpd portion to decreasing slope begins at the beginning of said extreme plateau.
  • This portion Vpd of decreasing slope signal inhibits the maintenance discharge which would have must have been generated by the maintenance signal Vref in the absence of a signal semi-selective Vad addressing.
  • This portion Vpd of signal to slope decreasing produces an erasure discharge at the cell level of the selected line.
  • the portion Vpd of signal with decreasing slope starts at the same time as an extreme low stop of the maintenance signal Vref.
  • the semi-selective erase addressing signal Vad comprises before the Vpd portion of signal with decreasing slope a portion which follows the signal Vref with Vd offset.
  • the semi-selective addressing signal erase begins during the edge fd of the maintenance signal Vref which leads at the extreme low level Pb during which the erasure discharge goes appear.
  • the variation of the slope of the Vpd portion of signal to slope decreasing is adjustable so as to stop the maintenance discharge well which should occur in the absence of the addressing signal.
  • Vpd Using the decreasing slope signal portion Vpd allows to better adapt the voltage triggering the erasure discharge to all cells display panel as in the variant shown in Figure 3a. Because, inevitably, a panel of visualization is not homogeneous, that is to say that the voltage which produces a discharge is not necessarily the same from one cell to another.
  • Figure 6a shows schematically a circuit GSA electronics for generating a Vad addressing signal superimposed on the maintenance signal Vref such as that shown in FIG. 5a.
  • This circuit includes a voltage source Vd referenced by relation to the potential of the maintenance signal Vref.
  • the maintenance signal Vref is generated by a circuit for generating the conventional GSE maintenance signal.
  • the output voltage of the voltage source Vd supplies all the circuits line ADL1, ADL2, ... ADLn of the PAP panel which receive on the other hand the maintenance signal Vref.
  • line addressing circuits ADL1, ADL2, ... ADLn are electrically equivalent each to a capacity c.
  • the capacities of line addressing circuits ALD1, ADL2, are connected in parallel.
  • the addressing circuits ADL1, ADL2, ... ADLn are each linked to several PAP panel electrodes.
  • a switch I1 is mounted between the output of the voltage Vd and the line addressing circuits ADL1, ADL2, ... ADLn.
  • the signal supplied by the voltage source Vd follows the signal of maintenance Vref with an offset of Vd.
  • a current regulating device Reg is mounted in series with switch I1, the assembly being mounted in parallel with the source voltage Vd.
  • This Reg device can be realized either by a potentiometer which allows you to adjust the time constant of the Vpd portion of the signal to decreasing slope either by a current generator which allows the adjustment of the slope.
  • the decreasing slope signal portion Vpd is generated by discharging the capacitors c of the line addressing circuits ADL1, ADL1, ... ADLn and this discharge is obtained by blocking the switch I1.
  • the addressing signal Vad superimposed on the maintenance signal Vref applied to the selected line to be deleted then has the following value: Vref + Vd - 1 sc ⁇ idt
  • Capacities c must be loaded beforehand.
  • the charging is obtained by setting the switch I1 to the conductive state.
  • Capacity c can be loaded at different times.
  • the signal portion corresponding to the loading of capacities c carries the reference Vc.
  • the selected line receives the addressing signal Vad superimposed on the maintenance signal Vref which is worth Vref + Vd. It is offset by Vd with respect to the maintenance signal Vref.
  • the discharge of capacities begins when the maintenance signal Vref alone reaches the level Pb.
  • the line which has just been erased can receive the maintenance signal Vref by switching on the switch T2 and blocking of the T1 switch for example and / or adjustment of the residual potential Vi equal to V1.
  • the line selected for registration receives the signal addressing Vad superimposed on the maintenance signal Vref which is equal to Vref + Vd, capacity loading c occurred at the start of the extreme plateau Ph the maintenance signal Vref during which the registration takes place.
  • the impulses registration are obtained by the cutting means integrated in the addressing circuits ADL1, ADL2, ... ADLn.
  • the line selected for erasure can receive the addressing signal Vad superimposed on the maintenance signal Vref, that is to say Vref + Vd since the capacities are always loaded. It is enough to switch the switches T1, T2 of the pair belonging to the module connected to this line.
  • the other lines only receive the maintenance signal Vref by adequate switching of the pair of module switches which is associated.
  • Switch I2 is kept blocked during erasure but as soon as the capacities c are loaded at the start of the extreme stage of the maintenance signal Vref, it can be activated. By making it alternately conductor and blocked, the registration pulses are obtained.
  • An advantage of the process according to the invention is that it does not require a maintenance signal with a median level, hence the possibility of remove the circuit generating this median level.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Claims (13)

  1. Verfahren zur Steuerung eines Wiedergabeschirms (PAP) mit Zellen (Ce), die durch den Schnittpunkt von zwei Netzen aus einander kreuzenden Elektroden (X1, X2) (Y1, Y2) definiert sind und diese Zellen zwei Zustände, einen für das Schreiben, den anderen zum Löschen, enthalten, mit:
    Zuführung eines im Wesentlichen rechteckförmigen Haltesignals zu beiden Seiten eines mittleren Potentials (VO) zu allen Zellen (Ce), mit dem Zweck der Erzeugung einer Halteentladung (Iden) für die Zellen beim Schreibzustand am Ende der zu einer äußersten Schulter (Pb, Ph) führenden Kanten (fn, fd),
    und Zuführung eines Adressiersignals (Vad), das dem Haltesignal (Vref) überlagert ist, nacheinander zu den Elektroden (Y1, Y2) eines Netzes, wobei dieses Adressiersignal ein halbselektives Löschsignal enthält, Erzeugung einer Löschentladung (Idef) für die Zellen (Ce) in dem geschriebenen Zustand, die mit der gewählten Elektrode (Y1) verbunden sind,
    dadurch gekennzeichnet, dass
    die Löschentladung (Idef) am Ende einer Kante (fd) erfolgt, die zu einer äußersten Schulter (Pb) des Haltesignals (Vref) allein führt, und diese Löschentladung (Idef) die Halteentladung sperrt, die bei der Beendigung dieser zu der äußersten Schulter des Haltesignals (Vref) allein führenden Kante erfolgt wäre.
  2. Verfahren zur Steuerung eines Wiedergabeschirms nach Anspruch 1, dadurch gekennzeichnet, dass das halbselektive Löschadressiersignal (Vad) ein Spannungsimpuls (le) ist, der aus einer äußersten Schulter (Pb) des Haltesignals (Vref) erzeugt wird, der früh genug beginnt, um die Halteentladung (Iden) zu verhindern.
  3. Verfahren zur Steuerung eines Wiedergabeschirms nach Anspruch 1, dadurch gekennzeichnet, dass das halbselektive Löschadressiersignal (Vad) einen Signalanteil (Vdp) mit zunehmender Steigung enthält, der zu Beginn der äußersten Schulter (Pb) des Haltesignals (Vref) beginnt, aus einem mittleren Potential (Vd), bezogen auf das Potential (V1) der äußersten Schulter (Pb), die zwischen dem Potential (V1) der äußersten Schulter (Pb) und dem mittleren Potential (V0) liegt und bei einer Restspannung (Vi) endet, bezogen auf das Potential (V1) der äußersten Schulter, die zwischen dem Potential (V1) der äußersten Schulter und dem mittleren Potential (Vb) liegt.
  4. Verfahren nach Anspruch 3, dadurch gekennzeichnet, dass dem Signalteil (Vpd) mit abnehmender Steilheit ein Signalteil vorausgeht, der auf die Kante (fd) folgt, die zu der äußersten Schulter (Pb) des Haltesignals führt, das durch das mittlere Potential versetzt ist.
  5. Verfahren zur Steuerung nach einem der Ansprüche 3 oder 4, wobei die Elektroden eines Netzes Halte- und Adressiersignale einer oder mehrerer Adressierschaltungen (ADL1, ADL2) empfangen, die zu den Kapazitäten (c) äquivalent sind, dadurch gekennzeichnet, dass der Signalteil (Vpd) mit abnehmender Steigung durch Entladung der Kapazitäten (c) gewonnen wird.
  6. Verfahren zur Steuerung nach Anspruch 5, dadurch gekennzeichnet, dass der Signalteil (Vpd) mit abnehmender Steigung eine einstellbare Zeitkonstante aufweist.
  7. Verfahren zur Steuerung nach einem der Ansprüche 5 oder 6, dadurch gekennzeichnet, dass die Ladung der Kapazitäten (c) während der Anstiegsflanke (fd) zu der äußersten Schulter (Pb) des Haltesignals (Vref) erfolgt.
  8. Verfahren zur Steuerung nach einem der Ansprüche 5 oder 6, dadurch gekennzeichnet, dass die Ladung der Kapazitäten (c) während der äußersten Schulter (Pb) des Haltesignals (Vref) erfolgt, die derjenigen vorangeht, während der der Signalteil (Vpd) mit abnehmender Steigung stattfindet.
  9. Verfahren zur Steuerung nach Anspruch 8, dadurch gekennzeichnet, dass das Adressiersignal (Vad) ein schreib-selektives Signal mit einem oder mehreren Impulsen enthält, die durch die Ladung der Kapazitäten (c) erzeugt werden.
  10. Bildwiedergabevorrichtung, bei der das Verfahren gemäß einem der Ansprüche 1 bis 9 angewendet wird, mit:
    einem Wiedergabeschirm (PAP), dessen Zellen (Ce) bei dem Schnittpunkt von zwei gekreuzten Elektrodennetzen (Y1, Y2, X1, X2) liegen,
    einer oder mehreren Adressierschaltungen (ADL1, ADL2), die mit den Elektroden (Y1, Y2) eines Netzes verbunden sind, wobei jede Schaltung eine Ausgangsstufe mit einem Paar von Schaltern (T1, T2) je Elektrode enthält, mit der einer dieser Schalter (T2) verbunden ist, der das Haltesignal (Vref) empfängt, und der andere (T1) das Adressiersignal (Vad) empfängt, das dem Haltesignal (Vref) überlagert ist,
    einem Generator für Haltesignale (GSE), die die Adressierschaltungen (ADL1, ADL2) speisen,
    einem Generator für Adressiersignale (GSA), die die Adressierschaltungen (ADL1, ADL2) speisen,
    dadurch gekennzeichnet, dass der Schalter (T2) das Haltesignal (Vref) empfängt und dafür bemessen ist, dass er den Halteentladestrom (Iden) übertragen kann.
  11. Wiedergabevorrichtung nach Anspruch 10, dadurch gekennzeichnet, dass der Generator für die Adressiersignale (GSA) folgendes enthält:
    eine Spannungsquelle (Vd), bezogen auf das Haltesignal (Vref),
    einen Schalter (I1) und eine Stromregelschaltung (Reg) in Reihe über den Anschlussklemmen der Spannungsquelle (Vd), wobei der Schalter (I1) mit dem Ausgang der Spannungsquelle (Vd) verbunden ist,
    die zu den Kapazitäten (c) äquivalenten Adressierschaltungen (ADL1, ADL2), die parallel zu der Stromregelschaltung (Reg) liegen,
    wobei der Schalter (I1) zur Ladung der Kapazitäten eingeschaltet und zu ihrer Entladung abgeschaltet ist.
  12. Wiedergabevorrichtung nach Anspruch 11, dadurch gekennzeichnet, dass der Generator für die Adressiersignale (GSA) mit Mitteln (I2) für die Erzeugung der mehrfachen Schreibimpulse versehen ist.
  13. Wiedergabevorrichtung nach Anspruch 12, dadurch gekennzeichnet, dass die Mittel (I2) zum Erzeugen der mehrfachen Schreibimpulse einem Schalter (I2) enthalten, der parallel zu der Stromregelschaltung (Reg) liegt.
EP97901133A 1996-01-30 1997-01-21 Ansteuerungsverfahren für eine anzeigetafel und anzeigevorrichtung, die dieses verfahren verwendet Expired - Lifetime EP0877999B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9601060A FR2744275B1 (fr) 1996-01-30 1996-01-30 Procede de commande d'un panneau de visualisation et dispositif de visualisation utilisant ce procede
FR9601060 1996-01-30
PCT/FR1997/000115 WO1997028526A1 (fr) 1996-01-30 1997-01-21 Procede de commande d'un panneau de visualisation et dispositif de visualisation utilsant ce procede

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EP0877999A1 EP0877999A1 (de) 1998-11-18
EP0877999B1 true EP0877999B1 (de) 2003-10-22

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EP (1) EP0877999B1 (de)
JP (1) JP2000504123A (de)
DE (1) DE69725706T2 (de)
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WO (1) WO1997028526A1 (de)

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Publication number Priority date Publication date Assignee Title
FR2769115B1 (fr) * 1997-09-30 1999-12-03 Thomson Tubes Electroniques Procede de commande d'un panneau de visualisation alternatif integrant une ionisation
FR2795218B1 (fr) * 1999-06-04 2001-08-17 Thomson Plasma Procede d'adressage d'un panneau de visualisation a effet memoire
US6963174B2 (en) * 2001-08-06 2005-11-08 Samsung Sdi Co., Ltd. Apparatus and method for driving a plasma display panel

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Publication number Priority date Publication date Assignee Title
JPS60221796A (ja) * 1984-04-18 1985-11-06 富士通株式会社 ガス放電パネルの駆動方法
FR2572805A1 (fr) 1984-11-06 1986-05-09 Thomson Csf Procede de mesure du centrage d'un barreau cylindrique dans un revetement transparent cylindrique et dispositif de mise en oeuvre
FR2629245A1 (fr) * 1988-03-25 1989-09-29 Thomson Csf Procede de commande point par point d'un panneau a plasma
FR2635902B1 (fr) 1988-08-26 1990-10-12 Thomson Csf Procede de commande tres rapide par adressage semi-selectif et adressage selectif d'un panneau a plasma alternatif a entretien coplanaire
FR2635901B1 (fr) * 1988-08-26 1990-10-12 Thomson Csf Procede de commande ligne par ligne d'un panneau a plasma du type alternatif a entretien coplanaire
FR2635900B1 (fr) 1988-08-30 1990-10-12 Thomson Csf Panneau a plasma a adressabilite accrue
FR2648953A1 (fr) 1989-06-23 1990-12-28 Thomson Tubes Electroniques Panneaux a plasma a zones de decharges delimitees
US5247288A (en) * 1989-11-06 1993-09-21 Board Of Trustees Of University Of Illinois High speed addressing method and apparatus for independent sustain and address plasma display panel
FR2662292B1 (fr) 1990-05-15 1992-07-24 Thomson Tubes Electroniques Procede de reglage de la luminosite d'ecrans de visualisation.
JP3025598B2 (ja) * 1993-04-30 2000-03-27 富士通株式会社 表示駆動装置及び表示駆動方法
FR2741468B1 (fr) * 1995-11-17 1997-12-12 Thomson Tubes Electroniques Procede de commande d'un ecran de visualisation et dispositif de visualisation mettant en oeuvre ce procede

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FR2744275B1 (fr) 1998-03-06
EP0877999A1 (de) 1998-11-18
JP2000504123A (ja) 2000-04-04
FR2744275A1 (fr) 1997-08-01
US6191763B1 (en) 2001-02-20
DE69725706T2 (de) 2004-08-12
DE69725706D1 (de) 2003-11-27
WO1997028526A1 (fr) 1997-08-07

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