JPH03237502A - Programmable controller - Google Patents

Abstract

PURPOSE:To increase the processing speed and to reduce the burden of a processor at the time of processing by constituting a system so that a one-bit processing processor directly reads out a program instruction from a program memory and executes it. CONSTITUTION:When the sequence control operation is started, a CPU 101 starts a BPU (one-bit processing processor) 102, and the BPU 102 successively reads out a program string from a program memory 104 to execute the processing from a load instruction. When an application instruction 1 to be executed in the CPU 101 is read out in accordance with successive advance of instructions, the BPU 102 transfers the control execution right to the CPU 101. Then, the application instruction 1 is executed on the side of the CPU 101. When the processing of the application instruction 1 is terminated, the CPU 101 reports the end to the BPU 102, and the BPU 102 reads out the next instruction. Thus, it is unnecessary for the CPU 101 to successively read out program instructions to determine the control execution right.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is an FA system that efficiently controls a factory production line.
PA (Process Automation) that controls the field of Factory Automation or various industrial processes.
The field of Automation relates to programmable controllers that incorporate sequence control programs and perform input/output processing of information with various on-site intelligent devices.

More specifically, the present invention relates to a programmable controller that organically combines an information processing function of a peripheral part of a microprocessor set inside, a signal exchange function with an I10 board group, and a programming function of a sequence control program.

<Prior Art> Figures 26 to 29 are conceptual diagrams showing examples of systems using conventional programmable controllers.

A programmable controller replaces the relay switchboard used in conventional sequence control systems, and has a sequence control program built into a microprocessor to efficiently execute desired sequence operations on a controlled object.

In the system shown in FIG. 26, a programmable controller U1 controls a system S1 for each mechanical component, a programmable controller U2 performs signal input/output with a mechanical component assembly system S2 to execute control operations, and a programmable controller U1, U2 is a desktop computer D connected to bus B and having a printer P.
Notifies the operator of the system status by communicating with the TC. Furthermore, the desktop computer DTC is
In some cases, it is managed by a higher-level medium-sized or large-sized computer MC through a communication line.

That is, the programmable controllers Ul and U2 respectively perform contact input/output processing,
It performs sequence control operations such as motor drive and stop processing, component positioning processing, and lamp lighting and extinguishing processing.

Next, attention will be paid to programmable controller U1.

The programmable controller U1 has a configuration in which several board devices are attached to a back brain bus (not shown) in the unit, and the attached board devices include a power supply board PS that supplies power to the unit, A CPU board 1 that has a microprocessor and is the core of sequence control, and several I1s that serve as information transmission media between the CPU board 1 and various devices installed in the system S1 for each mechanical component.
0 board 1, basic program and R3232C
This is a communication board T on which a boat or the like is set and performs communication operations with other devices on the bus B.

In such a configuration, the CPU board 1 in the programmable controller Ul has a system S1 for each mechanical component.
A sequence system # program compatible with the I
Sequence control arithmetic processing is executed according to the system information from the I10 board C, and a control signal is transmitted to the system S1 for each mechanical component via the I10 board C to execute a desired sequence operation.

The above sequence control program is created by editing a ladder program as shown in FIG. 27 using a program creation tool, for example, the CR7 screen of the desktop computer DTC in this example, and sending it to the CPU board 1.
The CPU board 1 converts the transmitted ladder program into the format shown in FIG. 28 and executes the sequence control operation.

The schematic configuration of the CPU board 1 is as shown in factor 29.

That is, the CPU board 1 includes a CPU 11 that controls the whole;
A 1-bit processing processor BPIJ12 that executes sequence control operations, a program memory 13 that stores a sequence control program string, a data memory 14 that is used for control operation operations, and an interface I/F 15 with the I10 board 1 is an address bus ab. , data bus d
b is connected in parallel.

Then, when the CPU 11 reads an instruction from the program memory 13 and starts a sequence control program as shown in FIGS. 27 and 28, the CPU 11 recognizes that the first step instruction "LD" is a 1-bit processing instruction. Then, the address bus ab and data bus db are switched to the 1-bit processing processor BPU12 side and this instruction “LD” is executed. Thereafter, the 1-bit instructions “OR”, “OUT” and “LD” are executed in the same way. It operates to provide the data to the 1-bit processing processor BPU12.

If the next instruction to be read is an applied instruction such as a numerical comparison instruction or an arithmetic operation instruction, the CPU 11 uses the address bus ab
and data bus db to its own side, and now CP
U11 is in charge of instruction execution operations.

Thereafter, the bus switching operation is performed in the same way, and the 1-bit processing instruction and application instruction are transferred to the BPU 12 or the CPU, respectively.
Executed by U11.

The obtained control calculation result is stored in the -time data memory 14, and the CPU 11 transmits the control calculation result to the I10 board C side via the I/F 15 as necessary.

At this time, when the CPU board 1 transfers data to multiple I10 boards C, the CPU board 1 performs two types of transfer: asynchronous transfer, which transfers data by exchanging handshake signals with the I10 board performing the data transfer, and a predetermined transfer by the CPU board. The communication operation is performed using one of the synchronous transfer methods in which data is transferred according to a sequence.

In addition, the communication board T is a desktop computer DT.
Upon receiving a command from C, the data on the CPU board C is read by a basic program set internally, and the status of the unit is sent to the desktop computer DTC from a communication port such as R8232C.

The programmable controller U2 also has the same configuration as the programmable controller U1 described above, and performs the same operations.

<Problems to be Solved by the Invention> However, the CPU 11 must determine the type of instruction read from the program memory 13 and switch the control execution right for itself or the 1-bit processing processor BPU 12, and the software Up,
There is a problem with the hardware, and the CPU 11
Since the CPU 11 or BPU 12 is selected after determining the contents of the instruction read by the CPU 11, the CPU 11 or the BPU 12 has the disadvantage that there is a lot of waiting time and the processing takes a long time.

In addition, the number of input points and output points of the I10 board to be installed is determined at the time of system design, and the I10 driver for each I10 board is preset on the CPU board side, so a user-specific I10 card can be used. had the disadvantage that the I10 driver had to be redesigned for each I10 board.

For data transfer with the I10 board, either asynchronous transfer or synchronous transfer is adopted, but asynchronous transfer takes time for handshake signal transmission and reception, and synchronous transfer requires an error on the I10 board side. This method has the disadvantage that communication operations are performed without determining the state, which adversely affects the system.

Furthermore, ladder programs used as sequence control programs usually have hundreds or thousands of steps, so if an abnormality or error occurs somewhere, it is necessary to complete the entire ladder program to identify the cause of the error. This has the disadvantage that debugging is troublesome and inefficient.

In addition, the sequence control program is one sequence control program (
It takes a lot of man-hours to create a ladder program.
Moreover, it was not possible to specify that only a part of the process be executed.

The present invention aims to solve the above problems,
The purpose of the invention is to realize a programmable controller that organically combines the information processing function of the peripheral part of the microprocessor set inside the programmable controller, the signal exchange function with the I10 board, and the Siegen control programming S function. It is said that

Means for Solving the Problems> Therefore, the programmable controller of the present invention is configured as follows.

To improve processing speed by omitting extra time when reading and executing a sequence control program.

The functions of a CPU board and a communication board are combined, and Sequence processing and basic processing related to communication are processed within the same board.

To design a standard I10 driver that allows user-designed 110 boards to be freely installed even during system expansion, and allows for easy redesign of sequence control, that is, standardization.

To solve the drawbacks of the conventional device by using a new data transfer method between a CPU board and an I10 board.

When executing a ladder program, we will make it easier to find the location and time of error occurrence and debug operations when an error occurs, and also make improvements to its programming.

The specific configuration of the present invention that solves the above problems is as follows.

(1) In a programmable controller consisting of a group of I10 boards that exchange various information with a controlled object, and a processor board that executes a sequence control program and provides control signals to the controlled object via the group of I10 boards. , the processor board is a basic processor board that controls the entire system, issues part of the instructions in the sequence control program, starts and ends the sequence control program, and performs general-purpose arithmetic processing, information processing, or control operations. a processor that executes a program, and a Sequence application instruction that is directly connected to a program memory in which the sequence control program is stored, reads and executes instructions sequentially from the program memory, and that the read instructions are to be executed by the processor. A 1-bit processing processor that gives instructions to the processor; a data memory that temporarily stores data; a fixed memory that stores a self-diagnosis program; and a communication interface that is involved in communication operations with a host computer. , an I10 interface for coupling to an I10 bus that connects an I10 board that exchanges various information with the controlled object, the processor, the 1-bit processor, the data memory, the fixed memory, the communication interface, and the I10. A programmable controller with an internal bus that interconnects the interface.

(2) A claim characterized in that the processor is provided with an execution right switching control means that repeats an operation of stopping the sequence control program after executing the sequence control program for a certain period of time and executing the basic program for a certain period of time. The programmable controller according to item (1).

(3) Received an execution command from the host computer to execute either a basic language execution command, a ladder language execution command, or a basic language and ladder language execution command, and responded to the specified language execution command. The programmable controller according to claim 1, wherein the programmable controller generates a programmable controller.

(4) At startup, the I10 driver set on the processor board inputs, for each I10 board, the board ID, board interface type, number of channels, command register address and buffer address or data register address, When special processing is required, a processing definition table is set in which an address specifying the special processing is read and stored in a table format, and the processing definition table is referred to when performing data output processing. (1) The programmable controller described in (1).

(5) a strobe signal generating means is provided in the processor board and the I10 board group, and when a data transfer cycle starts, the data transfer requesting board transmits a strobe signal every time a frame is transmitted to validate the frame; 2. The programmable controller according to claim 1, wherein the data transfer request destination board transmits a strobe signal every time a data frame and a status frame are transmitted, thereby completing the data transfer cycle.

(6) Provide abnormality detection circuits corresponding to the number of types of abnormalities,
Claim (1) characterized in that the processor receives the abnormality detection signal as an interrupt signal and stores the time indicated by an internal timer function and the contents of the abnormality detection in a table format.
Programmable controller as described.

(7) A comment file that stores comments to be added to the ladder circuit in the ladder program generated in the ladder language in correspondence with the step number of the ladder circuit, and the step number of the ladder circuit and the comment. - According to claim (1), a circuit/comment table is set in which comment numbers in a file are associated with each other, so that circuit comments, step numbers, and ladder circuits can be read from a programming tool. programmable controller.

(8> Omit the input/output refresh processing in the sequence control processing routine, assign a signal name to each circuit element when creating a ladder circuit, and match the signal name and address using a preset signal name/address correspondence table. 2. The programmable controller according to claim 1, wherein for those to which detailed addresses are not assigned at the time of compilation, detailed addresses corresponding to the signal names are set in descending order of addresses.

(9) When programming a ladder program, a series of sequence control operations is divided into blocks corresponding to several steps, and the ladder circuit of the final step of each block contains an instruction specifying the next block to be executed and the corresponding 2. The programmable controller according to claim 1, further comprising: setting an instruction for specifying a block processing stop, and setting and executing a ladder program on a block-by-block basis.

(10) A processor board that processes a basic language, at least one processor board that is dedicated to sequence language processing and stores one or more block-structured Sequence control programs, and this sequence language processing board. It consists of a group of I10 boards that are installed between lower-level processor boards dedicated to processing and exchange control objects and control information, and the processor board that processes the basic language is the processor board dedicated to sequence language processing. A programmable controller characterized in that a programmable controller notifies each of the block-configured Sequence control programs in the programmable controller of a start instruction and a termination instruction.

<Operation> The programmable controller of the present invention operates as follows.

(1) 1-bit processing A processor reads out a sequence of 1liIllll program instructions one by one from the program memory and executes them, and if the read program instructions are to be processed by the processor that controls the whole, the processor provides the program instructions to the processor for processing. Execute.

(2) After executing the Siegen control program for a certain period of time, the processor switches to the basic program execution operation. After a certain period of time has elapsed, the operation returns to the Siegen control program. Thereafter, the Siegen control program processing and the basic program processing are switched and executed every time a certain period of time elapses.

(3) When the host computer specifies one of the basic language, ladder language, basic language, and ladder language, the processor generates a system table,
Generates an execution environment according to the specified programming language.

[4] When the I10 driver in the processor board starts up, it reads various information from the installed I10 board, generates and stores a processing definition table, and when transferring data, refers to this processing definition table and Execute access processing with.

(5) When transferring data between the processor and I10 board,
Data transfer Originally, synchronous transfer is performed by activating the strobe signal every time a frame is sent, and asynchronous transfer is performed between the processor and the I10 board as a whole.

(6) Set up a comment file in which comments to be added to the ladder circuit correspond to step numbers, and a circuit/comment table in which step numbers are associated with comment numbers in the comment file, and program when adjusting the circuit. - Read and output circuit comments, step numbers, and ladder circuits from the tool.

(7) Assign signal names when creating a ladder circuit, associate signal names and addresses, and automatically assign detailed addresses to those for which detailed addresses have not been defined during compilation.

(8) When an abnormality detection signal is sent from the abnormality detection circuit installed on the processor board or I10 board side,
Stores the time of abnormality occurrence and the details of the abnormality in a table format,
Read out and analyze abnormalities as necessary.

(9) When execution of the final step of the block-based ladder program corresponding to each process is started, the ladder program of the block specified in this step is executed, and the processing of the block is ended.

(10) In a system configured using a processor board that executes a basic program and a processor board that stores several sequence control programs created in block units, each ladder is activated by a startup command from the basic program. Programs are controlled in their execution.

<Example> Next, a programmable controller implementing the present invention will be described.

The external appearance of an example of a system configured using the programmable controller of the present invention is similar to the conventional Siegen control system shown in FIG. 26, but the various Ii functions set inside the programmable controller are It is a characteristic.

FIG. 1 is an internal configuration diagram of a CPU board 10 of a programmable controller according to the present invention.

In this figure, CPU 101 is a microprocessor that controls the entire CPU board 10, for example, HC680.
00 etc. are used. The CPU 101 is connected to the internal bus b1 and installed in parallel with the BPU 102 that executes 1-bit processing instructions. CPtJ gate array 103 is CPtJ gate array 103
This block controls the output of timing signals so that U 101 can be executed efficiently.

The BPU 102 is composed of a gate array to process 1-bit processing instructions at high speed, and connects an instruction bus (not shown) to a program memory (RAM 128KB) 103 that stores sequence control programs such as ladder programs. Connect directly via

Note that the internal bus b1 includes an address bus, a data bus,
It includes a control bus.

Further, various instructions to be executed by the CPU 101 for overall control are stored in the ROM (B at 256) 105, and a basic program to be described later is also stored.

Data memory (B to RAM64) 106 is CPU1
This is the work area of 01.

The I10 interface (I/F) 107 is an interface for the I10 bus bb connected to the I10 boards CI and C2. Although only two I10 boards are connected in this figure, the number may increase depending on the system configuration.

Furthermore, the real-time clock generator 108 has a clock function, and includes a communication buffer (RAM 32B) 109 which serves as a data buffer for communication, and a communication buffer (RAM 32B) 109 which is connected to this communication memory and serves as an interface with the upper-level bus B. Interface 110 is connected to internal bus b1. Also, R for communication with programming tools etc.
A 3232C boat 111 will also be installed.

The I10 bus bb includes a general register interface type I10 board CI, and a command interface type I10 that has a microprocessor and communicates with the upper programmable controller by sending and receiving commands.
A plurality of two types of boards C2 are connected. register·
The interface type I10 board C1 may have a microprocessor, but it mainly consists of an interface all with the bus bb and an interface c12 with an external contact. I10 board C2 is bus b
an interface c21 with b, a microprocessor C22 (e.g. 8-bit CPU), and a data memory C21.
23 (for example, RAM8 and B) and an external interface C24.

The features of such a CPU board 10 will be explained next.

A feature of the configuration is that the BPU 102 directly accesses the program memory 104 only through an instruction bus (not shown) without going through the internal bus b1. This section explains its operation.

FIG. 2 is a ladder program representing a sequence to be controlled, and FIG. 3 is a program instruction sequence corresponding to this ladder program.

When the sequence control operation is started, the CPU 101 activates the BPU 102, and the BPU 102 sequentially reads program sequences from the program memory 104 and executes processing from the load instruction "LD".

If the program advances to the AND instruction, OR instruction, OUT instruction, and LD instruction, and the next read program instruction is the application instruction (1) to be executed by the CPU 101, the B P U 10
2 hands over control execution rights including exclusive rights to the address bus and data bus to the CPU 101.

As a result, the application instruction (1) is executed on the CPU 101 side. When the processing of this application instruction (1) is completed, C
The P U 101 notifies the B P U 102 of the completion notification, and the B P U 102 reads the next instruction. transfers control execution authority to c p tri ioi again.

Then, since the next program instruction that the BPU 102 reads is the load instruction "LD", the BPU
At step 102, the user executes this command processing by himself.

In this way, B P which always executes sequence basic commands
The U 102 reads a program instruction string, and if the read instruction is a sequence application instruction to be executed by the CPU 101, it hands over control execution authority to the CPU 101. At this time, the program instruction string is overwhelmingly filled with sequence basic instructions. Therefore, the control operation of the BPU 102 becomes faster. After cptrioi executes the instruction, the BPU
It only sends back a notification of completion to 102.

Furthermore, if the program instruction read by the B P U 102 is an illegal instruction that is not defined in the system, the B P U 102 supplies a pseudo instruction to the CPU 11 according to the form of the illegal instruction to the c p tr ioi. This pseudo-instruction, which is set in advance to
1 is set to prevent the system from being adversely affected by executing illegal instructions as they are.

In this way, when the CPU 101 starts the sequence control process, the BPU 102 reads the program instructions from the program memory 104 and starts executing them.
Since the program instructions are subsequently read directly from the program memory 104, there is no need for the CPU 101 to read the program instructions one by one to determine the control execution right.

On the other hand, the CPU 101 is written in a basic language that controls the progress of the above-mentioned sequence and also executes very general communication operations to a host computer, general-purpose arithmetic processing, information processing, control operations, etc. The basic program is set to be executed, and the correlation between the execution of this basic program and the execution of the sequence control program described above will be explained next.

FIG. 4 shows sequence control processing SQ and basic processing R.
FIG. 3 is a conceptual diagram showing parallel operations of AS.

The sequence control process SQ is a process that executes a sequence of program instructions as shown in FIG.
The AS is a basic program such as a data reading program or a communication program arbitrarily created by the user. The execution right switching processing unit 81 and the timer 82 are CPU
This is a function set in oi. Task scheduler 8
3 is also set to CPU 101 and the basic
Although it has a function of determining the execution priority of some processes within a program, it is not directly related to the operation of the present invention.

The program sequence for sequence control processing usually consists of hundreds or thousands of sequences, and the execution time for one cycle is several + ms or several hundred ms, which varies greatly depending on the system configuration to be controlled.

Here, assume a system in which the timer 82 is set to 10 m5 in advance, for example.

First, the first step of the sequence control process SQ is to execute the load instruction "LD". Then the AND instruction AND
, OR instruction OR1 output instruction OUT, and at this point, exactly 10 ms have elapsed, and a time-up signal is given from the timer 82 to the execution right switching control section 81 as an interrupt signal. The CPU 101 inputs this interrupt signal, but the control execution right at this point is on the BPU 103 side.
CPU 101 does not accept this time-up interrupt.

As the Sequence processing progresses and the BPU 102 executes the load instruction "LD", the control execution right is transferred to the CPU 101 and the processing of the application instruction (1) is started.
P U 101 accepts the 10 ms time-up interrupt signal and thereby begins processing basic program BAS according to task scheduler 83 .

At this time, the execution of the sequence control process SQ remains stopped.

After that, when the timer 82 times up and a 10ms interrupt signal is generated, the execution right switching processing unit 81 in the CPU 101 temporarily saves the current basic progress status to the data memory 106 and restarts the stopped sequence control processing. S
Resume Q operation.

Note that regardless of the time-up signal every 10 ms, if the sequence control process SQ ends, the sequence control process SQ gives a notification of completion to the execution right switching processing unit 81, and the CP
U 101 starts basic processing 21 .

In this way, since the sequence control processing SQ and basic processing BAS are switched and operated every 10m5, it is possible to operate the sequence control processing SQ and basic processing 2 as if they were Sequence processing 21 and basic processing 2 from the outside.
2 appear to be running at the same time, and multi-processing is possible.

Note that the time set in the timer 82 is not limited to 10 m5, and may be set arbitrarily depending on the system configuration.

On the other hand, some system constructions do not require parallel operation of sequence control processing and basic processing as described above, and system changes may make either sequence control processing or basic processing unnecessary. In such a case, a program according to the flowchart shown in FIG. 5 is installed in the CPU board 10 in advance, and the following steps are taken.

After executing a self-diagnosis operation at power-on, it is checked whether the language to be used for processing has been specified from the upper side, and if the language to be used is a sequence language, the system and tables required for sequence language processing are stored in the data memory 106. If a basic language is specified, system tables necessary for basic language processing are created in the data memory 106, and if both a sequence language and a basic language are specified, system tables for sequence language processing and basic language processing are created in the data memory 106. Create the system tables needed for both.

In this way, since the program is set to create a system table corresponding to the specified language, it is easy to change the system from a host computer, such as a desktop computer.

Next, a standard I10 driver that is set on the CPU board 10 and is compatible with various types of I10 boards will be described with reference to FIG.

An access request a1 to the I10 board from a user program UP such as a basic program set on the CPU board 10, or an access request a1 from the I10 board C to the CPU
The interrupt request a2 to the board 10 side is accepted by the operation system O8 in the CPU board 10.

Then, the access request a1 from the CPU board IO is
The interrupt request a2 from the I10 board to the CPU board 10 starts the interrupt request reception processing step (2).

The standard I10 driver SD according to the present invention creates a processing definition table TBLI for each I10 board installed in each slot at the time of system startup.

TBL2. -, TBLn is generated, and in the case of I10 request reception processing (2) or interrupt request reception processing (2), access preparation is started by referring to this processing definition table TBL.

When processing starts, it is determined whether the I10 board to be accessed is a register interface type or a command interface type, and its main processing is executed. 4. Contents of main processing for register interface type and command interface type main processing There is no difference from the conventional processing procedure.Here, the register interface type I10 board is the normal I10 board shown in the first piece.
The command interface type I10 board, which is a type of board C1, is a type of I10 board that has a microprocessor and sends and receives commands, as shown in FIG.

Further, a common process routine is set in advance for processes common to the I10 request reception process (2) and the interrupt request reception process (2), and when the common process is executed, this common process routine is executed regardless of the type of interface of the I10 board. Furthermore, for the I10 board that requires processing different from standard processing, a special processing routine is prepared and set, uploaded from the I10 board measurement at startup, and used by linking with the standard driver. Addresses of such special processing routines, etc. are set in the processing definition table TBL at startup.

Next, a method for generating this processing definition table TBL will be explained using FIG. 7.

The processing definition table TBL is generated for each I10 board at the time of the first I10 request reception process of the CPU board 10, and is performed by reading the board ID and various information of the I10 board.

First, the number of channels (number of boats) and whether output is necessary are set as parameters based on various information about the I10 board.

If the type of the I10 board is a command interface type, the addresses of each command register are set in a table, and then the addresses of each buffer are set in a table. If special processing is required, set the special processing routine address in the table.

Furthermore, if the type of the I10 board is a register interface type, each register address is set in a table.

Finally, turn on the table creation flag and execute various request processes.

By performing the above operations for each I10 board installed in the system, the processing definition table TBL can be set in the standard I10 driver SD.

Next, an example of the access processing of the Muku Jun I10 driver SD having such a processing definition table TBL will be described with reference to the flowchart of FIG.

When the access process, that is, the data transfer preparation process starts, C
The standard I10 driver SD of the PU board 10 is the I1
Referring to the processing definition table TBL of the I10 board, the parameters, ie, the number of channels (number of boats) and the presence or absence of output of the I10 board, are checked to identify the type of interface.

If it is a command interface type, refer to the processing definition table TBL and set the output buffer address to ge.
t, performs data conversion, and sets the data to be output in this output buffer. Then, refer to the processing definition table TBL again and set the command register address to ge.
tj,, set the output command. In this state I10
Waits for an interrupt from the board and returns when the interrupt is received.
Output status.

If the relevant I10 board is a register interface type, refer to the processing definition table TBL and input the output data.
Get the register address and check whether it is a data I10 interface. If it is a data I10 interface, convert 1-bit data to 1-word data, set mask data, and write the data to the output data register. If it is not a data I10 interface, write the data to the output data register. Write. The process of writing data to this output data register is a common process.

Since such a standard I10 driver SD is provided, even if many types of I10 boards are installed in the system, a processing definition table is generated for each I10 board and the I10 board can be accessed according to this processing definition table. , it is not necessary to provide a driver for each I10 board, and only one loss factor I10 driver can handle access processing with all I10 boards without degrading performance. In addition, since many types of I10 boards can be used with one loss factor I10 driver, subsequent I10
The man-hours required for driver development are reduced to zero, and the memory capacity required to store the I10 driver is also reduced.Furthermore, by standardizing the I10 board interface as register type or command type, users can design their own I10 board and integrate it into the system. It can also be incorporated.

Next, such a CPU board 10 and I10 bus bb
A hardware data transfer method with the I10 board connected via the board will be explained using FIGS. 9 and 10.

In the configuration diagram shown in FIG. 1, the I10 interface 107 for the I10 bus bb of the CPU board IO
and interface C1 of each 110 board CI, C2
1 and 12 are provided with strobe signal generating means for generating a strobe signal 5TB- on the control line in the I10 bus bb when a data transfer request occurs. Specifically, the I10 interface 107 configured with a gate array
, I/FC11゜12 sends a strobe signal 5TB- to the I10 bus b for each transfer frame in connection with data transfer requests.
Add a logical configuration to send to b.

FIG. 9 is a time chart when the I10 board transfers data to the CPU board 10 in response to a data transfer request from the CPU board 10.

When a data transfer request occurs from the CPU board 10, the C
PU board lo sends control frame FO and strobe signal STB*“L” to I10 bus bb.

Control frame FO has read/write distinction,
Data size (2 or 4 bytes), data type (
A transfer mode bit that specifies data or control signals, a byte enable bit that enables access in units of bytes, etc. are set. This control frame FO is made valid at the rising edge SO of the strobe signal 5TB)L''.

Subsequently, the CPU board 10 receives address frames Fl,
Send F2. These address frames Fl, F
2 consists of a 2-byte frame and guarantees an address space of 256KB. These address frames Fl
, F2 are the rising edges of the strobe signal 5TB-“L” S1. It becomes effective in S2.

During the period T1 up to this point, the CPU board 101N! ! This is the operation.

The I10 board that has received the above frames FO, Fl, and F2 executes processing to determine whether or not it has been selected in period T2, and if it has been selected, it executes data transmission preparation processing and the like. The selected I10 board is I1 in period T3
Data frame F3.0 to be sent on bus bb. F4
Send out.

In this case, the data is 2 bytes, and at the same time this I1
The 0 board only sends out the Trope signal 5TB-“L”.

Rising edge S3 of strobe signal sra*. S
4 to data frame F3. F4 is considered valid.

Finally, this I10 board sends out the status frame F5 as a reply signal along with the strobe signal STB*"L". This 1-byte status frame F5
are internal status signals of the I10 board, such as signals for setting various statuses such as normal data transfer, error status, and board failure status.

The frame signal FRH- is a signal whose falling edge indicates the first frame and whose rising edge indicates the last frame during a data transfer cycle, and is used for framing error detection. Furthermore, when the data direction designation signal DDIR* is "H" during the data transfer cycle, it indicates frame transfer from the CPU board to the I10 side, and when it is "L", it indicates frame transfer from the Ilo side to the CPU board side. 0 signal FR1h used to prevent data collision between the CPU board and I10 board, etc.
DDIR* is sent on the control line of I10 bus bb.

FIG. 10 is a time chart when data is transferred from the CPU board 10 to the I10 board.

In this case, during period T4, control frame FO, address frame F1. F2
, data frame F3. F4 is strobe signal STB
*Outputted together with "L", and after the I10 board performs necessary processing in period T5, it returns status frame F5 and strobe signal 5TB-"L" in period T6.

In this way, according to the data transfer method explained using FIGS. 9 and 10, each time a frame is transferred, the CPU board or I10 board sends out the strobe signal STB "L" to validate the frame. Therefore, frame transfer is synchronous transfer, and from the perspective of the entire data transfer cycle, in the case of FIG. 9, the processing of period TI and the period T3 are
The processing in period T4 and the processing in period T6 are asynchronous transfer in the case of FIG.
It is possible to realize a method that combines synchronous transfer and asynchronous transfer.

Fig. 11 shows a function to record the failure history of this programmable controller. Inside the programmable controller, there is a power-off detection circuit 21 that detects when the power is turned off, and a bulk temperature abnormality detection circuit that detects internal temperature abnormalities. Times F! @
22. An abnormality detection circuit such as a software abnormality detection circuit 23 is provided to detect runaway of internally executed software.

When an abnormality detection signal is generated from one of the abnormality detection circuits, this detection signal is input to the interrupt generation circuit 24 to generate an interrupt to the CPU 1 (11).

Upon receiving the interrupt signal, the CPU 101 starts the abnormality occurrence interrupt process 26 from the normal process 25 .

On the other hand, the CPU 101 has a clock function TT,
When the abnormality occurrence interrupt processing 26 is activated, an auxiliary memory that associates the type of abnormality occurrence with the time when this abnormality occurred, arranges the abnormality occurrences in chronological order, and stores them in a file format in the auxiliary storage device 27. The device 27 is the data memory 106
is used.

Later, if specified by the host computer, the CPU
101 starts the history succession processing 28, reads out the contents of the auxiliary storage device 1If27, and sends it to the upper side, thereby displaying the abnormality occurrence situation in the upper side CRT display device, printer, etc. in a table format as shown in Fig. 12. can be output externally, making it easy to analyze the details and time of abnormality occurrence, error analysis, and take countermeasures.

Next, identification of a ladder circuit in which an error occurs during execution of a ladder program or a desired ladder circuit in the programmable controller of the present invention will be described.

The programmable controller is, for example, R3232C
, R3422, etc., and generally a ladder program is set in the form of a ladder circuit with various comments added, as shown in FIG. That is, in the ladder program, the program name "TBST" is set in the first stage, the title "Test run circuit", the step number of the ladder circuit, the circuit comment "Emergency stop circuit" for multiple ladder circuits, and the ladder circuit 1.
Sub-comments corresponding to each line “operating conditions, operating status,
...” etc. are set.

The programmable controller stores such ladder programs internally and executes control operations, but if an error occurs during sequence control processing, all program steps can be deleted using a programming creation tool, etc. It is read out and displayed on the CRT display screen to identify the location of the failure. On the other hand, ladder circuits have thousands of steps, and it is difficult to find a specific ladder circuit on a CRT display screen that can only display a few dozen lines. We bring this to the site and match the actual circuit with the circuit on the program.

However, such a ladder circuit identification method has extremely poor workability.

In the programmable controller of the present invention, the ladder circuit is specified by the method described below.

FIG. 14 is a configuration diagram in which a programming tool is connected to the CPU board 10 of the programmable controller. The CPtJ board 10 uses a CPU for ease of explanation.
101, R3232C boat 111, RAM10
6. Only the internal bus b1 is shown, and the programming tool is connected to the R3232C board 111 of the CPU board 10, including a display section PTCRT, a keyboard operation section PTKB, and a main memory PTHI.

It has an auxiliary memory PTM2.

As mentioned above, on the programming tool, you can edit the ladder circuit corresponding to sequence control, and
Temporarily save it to the program image file IMF,
The created ladder program is R3232C boat 1
11 to RAM 106. At this time,
Along with the ladder program, a circuit/comment correspondence table OCT in which ladder circuits are associated with various comments is also transmitted at the same time.

This circuit/comment correspondence table CCT associates the position of a comment (step number) on a circuit with the position of a comment on a comment file CF, which will be described later.

Also, with this circuit/comment correspondence table CCT,
Even if the program is changed, the positioning of the ladder circuit and its comments can be memorized.

Accordingly, CPU 101 sets the transmitted sequence program SQP and circuit/comment correspondence table OCT.

Furthermore, on the programming tool side, auxiliary memory PTH2
A comment file CF is set in which the step number of the ladder circuit and the content of the comment added to the ladder circuit are stored in correspondence with each other.

Figure 15 shows the contents of comment file CF.
Figure 6 shows the contents of the circuit/comment correspondence table OCT.This comment file CF may be set in the RAM 106 of the CPU board 10, rather than in the programming tool. You may additionally set a comment file that corresponds to comments.

Now, the operation when searching for a specific location in the ladder circuit on the programming tool will be explained using FIG. 17.

The programming tool reads the contents of comment file CF and circuit/comment correspondence table CCT, and writes C
The RT display device is set in advance to display the following display screens 31, 32, 33, and 34.

The initial screen of the CRT display device of the programming tool is a circuit monitor menu screen S1, and when a circuit comment display screen S2 is selected from this screen, a circuit comment list is displayed in a list format on the CRT. When the sub-comment display screen S3 is further selected from this circuit comment display screen S2, all sub-comments included in the circuit comment are displayed. Then, when the circuit display screen S4 is selected in response to a sub-comment, a ladder circuit corresponding to this sub-comment is displayed.

That is, to identify a certain ladder circuit from a ladder program as shown in FIG. By specifying a circuit, a specific ladder circuit can be displayed on the CRT display screen.

Note that the circuit display screen S4 may be directly selected from the circuit monitor menu screen S1 or the circuit comment list S2, and page update scrolling and page update monitoring can be performed on each display screen.

In this way, in the programmable controller of the present invention, a comment file and a circuit/comment correspondence table are set and read, and various comments added to a ladder circuit are made to correspond to the ladder circuit, so that the CRT can be written hierarchically.
The desired ladder circuit can be immediately detected.

The above described method makes it easy to search the ladder circuit when adjusting the circuit or when an error occurs.Next, we will discuss how to improve the operation when creating and debugging a ladder program.

In general, sequence control processing that uses a ladder program includes common processing such as self-diagnosis, input/output refresh processing of input registers and output registers on the I10 board side, execution of a set ladder program, and control of host devices, etc. It is executed by a processing routine consisting of service processing and the like.

In the programmable controller of the present invention, when creating a sequence control program, the input/output refresh process following the common process is omitted so that programming and debugging can be performed without installing the I10 board, as shown in FIG. This allows debug operations to be performed without the need for an I10 board in response to instructions from a debugger such as a programming tool.

FIG. 19 is a conceptual diagram of the programming function of the ladder program in the programmable controller of the present invention. Each of these domestic blocks is a software functional block of the programmable controller of the present invention.

The operation of each functional block in this figure is as follows.

The circuit editing function 201 is a function for editing each circuit element of a ladder circuit. Using this function, a programmer writes the address of each circuit element using a signal name similar to a device name or the like when designing a ladder circuit. The signal definition function 202 is a table-type setting unit that presets the correspondence between the signal name and address of each circuit element. The compile function 203 refers to the signal name in the ladder circuit generated by the circuit editing function 201 and the corresponding address from the signal definition function 202, and further automatically generates addresses rti, l! Referring to the signal from the i-function 204, the executable program is sent to the sequence processing section 205. The automatic address generation function 204 is an a function block that automatically assigns a detailed address to the signal name from the signal definition function 202.

The steps for creating a ladder program using these functions will be explained below.

A ladder circuit as shown in FIG. 20 is generated using the programming tool and circuit editing function 201.

At this time, each circuit element such as a relay and an output section is SWl, C0
Set the circuit elements by signal names such as ILI, however, the signal names SWI, SW2 . C0ILI.

C0IL2. IRLI, TIMI, CNTl, REGI
As shown in FIG. 21, addresses X, X, Y, Y, 1 . T.C.

It is made to correspond in advance to D, where X is an input, Y is an output, ■ is an internal relay, T is a timer, C is a counter, and D is an address representing a data register.

If a detailed address is not set for each ladder circuit element by the compile function 203, the automatic address generation function 204 automatically assigns a detailed address. That is, if only address X is set in circuit element SWI and detailed address XXX is not set, detailed address X001 is assigned. At this time, detailed addresses are set in order from the smallest number added to the signal name of the ladder circuit element. The result is shown in FIG. That is, address X001 is set for signal name SW1, address X002 is set for signal name SW2, and so on.

Next, the executable program obtained by the compile function in this way is processed by the Sequence control processing section, but even if the I10 board is not installed at the debugging stage, the processing routine shown in FIG. As shown in the figure,
Since input/output refresh processing is bypassed, debugging operations can be performed using only the CPU board 10 without installing the I10 board. Then, depending on the debug result, the detailed address is assigned or changed as necessary.

Therefore, it is possible to automatically associate signal names and detailed addresses without being aware of the addresses of each ladder circuit element, making it easy to design a sequence control program, and debug operations can be performed without installing an I10 board.
It is possible to check the operation of the rudder and 10 grams before completing the design of the relay board that supports Siegens processing.

Further, in the programmable controller of the present invention, a ladder program having thousands of steps is divided into blocks for each process and programmed as follows. The programming method is shown in FIGS. 23(a), (b), and (c).

FIG. 23(a) is a part of the ladder program for step 1, (b) is for step 2, and FIG. 23(C) is for step 5.

The final step of process 1 includes the start command "ACT PROGl, 2" and the end command "I" newly defined in the present invention.
Set NACT PROGl, 1″. This will result in
When the control operation of process 1 reaches the final step, the block ladder program PROG1.1 of process 1 is stopped and the block ladder program PROG of process 2 is started.
Start 1.2. This starts the control operation of step 2.

The final step of the block ladder program PROG1.2 includes a stop command “INA” for the ladder program.
CT PROGl, 2" and parallel activation instructions of steps 3 and 4.5 "ACT PROGl, 3", "ACT PR
OG2.1""ACT PROG3.1" is set,
These steps 3.4.5 are activated simultaneously.

Process 5 monitors the completion of processes 3 and 4, and
4.5 When the stop is detected, the stop command “I N A C
T PROG3.1'' and “ACT PROGl,1”
Then, the process returns to step 1, which is the starting step of this sequence control process.

In this way, the ladder program activation command “ACT”
and stop command "INACT" are defined, it is possible to divide a series of sequence control programs numbering into thousands into several blocks and perform programming in parallel. Furthermore, since the ladder programs notify each other of their startup and termination, it is also possible to set each block-divided ladder program on a plurality of CPU boards and operate them under sequence control.

Figure 24 shows C with basic program processing set.
This is an example in which a control target M on an actual control line L is controlled by combining the PU board 11 and CPU boards 12, 13, and 14 set only for ladder program processing.

In addition, the CPU board 12 includes a ladder program LDI,
Set up LD2, install I10 board group cio, and install CP
The U board 13 has a ladder program LD3. LD4.
Set up LD5, install I10 board group C20, and
The ladder program LD6 is set on the U board 14, and the I10 board group C30 is installed.

An example of a basic program set on the CPU board 11 is shown in FIG.

Also, each ladder program LDI, LD2°LD3.
LD4. LD5. LD6 is a series of sequence control programs for each controlled object M, and is a ladder program having a block structure as described above, and can be programmed independently.

The basic program of the CPU board 11 gives a start command to each ladder program and receives its termination command.

When the operation starts, the CPU board 11
2 ladder program LD1 and then ladder program LD2 are started. When these programs are completed, the ladder program LD3. Or execute LD4. When you finish program LD3 or LD4,
Continue to run the basic program on CPU board 1.
3 and the ladder program LD5 in the CPU board 14 are started in parallel.

In this way, according to the system shown in this figure, a sequence control program in which a series of sequence control operations is divided into blocks can be operated and processed by multiple programmable controllers, and efficient sequence control processing is possible. be.

As described above, according to the programmable controller of the present invention, it is possible to improve the processing speed of Sequence control, to easily redesign the system when changing the system, and to realize a programmable controller with high processing efficiency.

<Effects of the Invention> As described above, the programmable controller of the present invention provides the following effects.

(1) 1-bit processing Since the processor directly reads program instructions from program memory and executes them, there is no need for the processor to read program instructions and determine control execution rights each time, which increases processing speed and reduces processing time. can reduce the burden of

(2) Efficient processing can be realized because sequence control processing and general basic processing are executed alternately.

(3) Since the type of language to be executed can be sent from the host computer, it is easy to change the processing language;
It is also easy to change the configuration of the entire system.

(4) The I10 board driver is a standard driver,
Since there is no need to configure settings for each I10 board installed, driver setting operations can be significantly reduced and system changes can be made easily.

(5) In data transfer between the processor and the I10 board, the data transfer source sends a strobe signal in units of frames, and the data transfer destination sends a status frame at the end, so the frame transfer is a synchronous transfer, and the processor and Since the entire data transfer with the I10 board is asynchronous transfer, mutual responses can be confirmed every cycle, increasing system reliability.In addition, the I10 board, which improves response speed due to asynchronous transfer, can be installed. can do.

(6) When checking a ladder circuit, comments added to the ladder circuit on the programming tool can be displayed hierarchically on the CR7 screen to specify the ladder circuit to be adjusted, making it easy to extract the ladder circuit.

(7) When creating a ladder circuit, addresses can be automatically assigned just by naming signals, making debugging easier without the need to install an I10 board.

(8) Abnormal conditions that occur internally can be recorded, so the abnormal situation can be easily confirmed and analyzed later.

(9) Since a ladder program with thousands of steps can be generated in block units for each process, programming for one sequence control can be divided and created, improving programming efficiency.

(10) Some basic ladder programs
Since the program is executed on several processor boards, the entire processing flow does not have to consist of only a long ladder program, and the host computer can grasp the execution status of each processor board and can communicate with each other at the optimal timing. data communication.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of the processor board and I10 board of the programmable controller of the invention, FIG. 2 is a diagram showing a ladder program for explaining the operation of the programmable controller of the invention, and FIG. is B in the programmable controller of the present invention.
A diagram for explaining the operation of the P U 102 and the CPU 101, FIG. 4 is a diagram showing the correlation between sequence control processing and basic processing of the programmable controller of the present invention, and FIG. 5 is a diagram for explaining the operation of the programmable controller of the present invention. FIG. 6 is a conceptual diagram showing the operation of the standard I10 driver of the programmable controller of the present invention, and FIG. 7 is a flowchart for setting the processing language from the host computer. FIG. 8 is a diagram showing the method of creating a process definition table in the driver.
I10 card by Shino Jun I10 driver of controller
Flowcharts representing the access procedure, Figures 9 and 1
Figure 0 shows the CPU of the programmable controller of the present invention.
FIG. 11 is a time chart showing the data transfer between the board and the I10 board; FIG.
Figure 2 is a diagram showing the case where the information of the abnormality recording device shown in Figure 11 is displayed on the CRT of the host computer;
14 is a block diagram showing the programming tool of the present invention and a function for displaying comments corresponding to the step numbers of the ladder circuit.
Figure 15 is a diagram showing the comment file in the function shown in Figure 14, Figure 16 is a diagram showing the circuit/comment correspondence table in the function shown in Figure 14, and Figure 17 is a diagram showing the comment file in the function shown in Figure 14.
Figure 4 is a transition state diagram of the CRT screen display of the programming tool according to the functions, Figure 18 is a diagram showing the processing routine of the programmable controller of the present invention, and Figure 19 is a diagram showing the ladder circuit of the programmable controller of the present invention during programming. Figure 20 is a diagram showing the functional blocks, Figure 20 is a diagram when the ladder circuit is generated, Figure 21 is a diagram showing the correspondence table between signal names and addresses of the ladder circuit, and Figure 22 is the diagram when the ladder circuit is generated.
Figure 1 shows when detailed addresses are assigned to the signal names of the ladder circuit. Figures 23 (a), (b), and (C) are diagrams showing the ladder program created for each block. Figure 24 shows the numbers. Figure 25 is an example of a basic program that controls the system in Figure 24, and Figure 26 is a general example of a program using a programmable controller. Diagram showing the system configuration, Part 2
Figure 7 shows an example of the Siegen control program.
FIG. 28 is a diagram showing a part of the program, FIG. 28 is a diagram showing program instructions corresponding to the ladder program of FIG. 27, and FIG. 29 is a circuit block diagram of a processor board in a conventional programmable controller. 10.11.12.13...CPU board, 101.
... Processor, 102 ... CPU gate array,
103... 1-bit processing processor, 104... program memory, 105... ROM, 106...
Data memory, 107... I10 interface, 108... Real-time clock generator, 109... Communication buffer, 110... Communication interface, 111... R3232C boat, bl... Internal bus, bb ...I10 bus, B...upper bus, 81...
- Execution right switching processing unit, 82... timer, cl, c2.
c3...I10 board, clo, c20. c30
...I10 board group, c 11. c12. c2
1...Interface, c22...8-bit processor, c23...Memory, c24...Interface. Figure 2 Figure 3 Figure 5 Figure 7 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 RE G I DU Ll 1 Figure 24 Figure 25 Figure 23 (a) (c) Figure 27Figure 28

Claims (10)

[Claims] (1) Consists of a group of I/O boards that exchange various information with a controlled object, and a processor board that executes a sequence control program and provides control signals to the controlled object via the I/O board group. In the programmable controller, the processor board controls the entire system, issues part of the instructions in the sequence control program, and instructions for starting and terminating the sequence control program, and performs general-purpose arithmetic processing, information processing, or control operations. a processor that executes a basic program that performs the following; and a processor that is directly connected to a program memory in which the sequence control program is stored, reads and executes instructions sequentially from the program memory, and executes the read instructions by the processor. In the case of an exponent sequence application instruction, a 1-bit processing processor that provides this instruction to the processor, a data memory that temporarily stores data, a fixed memory that stores a self-diagnosis program, and a communication operation with a host computer. a related communication interface; an I/O interface for coupling to an I/O bus connecting an I/O board that exchanges various information with the controlled object; the processor, the 1-bit processing processor, and the data memory; and an internal bus interconnecting the fixed memory, the communication interface, and the I/O interface. (2) A claim characterized in that the processor is provided with an execution right switching control means that repeats an operation of stopping the sequence control program after executing the sequence control program for a certain period of time and executing the basic program for a certain period of time. The programmable controller according to item (1). (3) Receive an execution command from the host computer to execute either a basic language execution command, a ladder language execution command, or a basic language and ladder language execution command, and generate an execution environment corresponding to the specified language execution command. The programmable controller according to claim (1). (4) At startup, the I/O driver set on the processor board inputs the board ID, board interface type, number of channels, command register address, buffer address, or data address for each I/O board. A processing definition table is set in which a register address and an address specifying the special processing are read out and stored in a table format when special processing is required, and the processing definition table is referred to when performing data output processing. The programmable controller according to claim (1). (5) A strobe signal generation means is provided in the processor board and the I/O board group, and when a data transfer cycle starts, the data transfer request source board sends a strobe signal every time a frame is transmitted to validate the frame. 2. The programmable controller according to claim 1, wherein the data transfer request destination board transmits a strobe signal every time a data frame and a status frame or a status frame is transmitted to complete the data transfer cycle. (6) Provide abnormality detection circuits corresponding to the number of types of abnormalities,
Claim (1) characterized in that the processor receives the abnormality detection signal as an interrupt signal and stores the time indicated by an internal timer function and the contents of the abnormality detection in a table format.
Programmable controller as described. (7) A comment file that stores comments to be added to the ladder circuit in the ladder program generated in the ladder language in correspondence with the step number of the ladder circuit, and a step number of the ladder circuit and the comment file. The programmable computer according to claim (1), characterized in that a circuit/comment table is set in which the comment number of the circuit/comment table is associated with the comment number, and the circuit comment, the step number, and the ladder circuit can be read out from the programming tool. controller. (8) Omit input/output refresh processing in the sequence control processing routine, assign signal names to each circuit element when creating a ladder circuit, and match signal names and addresses using a preset signal name/address correspondence table. 2. The programmable controller according to claim 1, wherein for those to which detailed addresses are not assigned at the time of compilation, detailed addresses corresponding to the signal names are set in descending order of addresses. (9) When programming a ladder program, a series of sequence control operations is divided into blocks corresponding to several steps, and the ladder circuit of the final step of each block contains an instruction specifying the next block to be executed and the corresponding 2. The programmable controller according to claim 1, further comprising: setting an instruction for specifying a block processing stop, and setting and executing a ladder program on a block-by-block basis. (10) A processor board that processes a basic language, at least one processor board that is dedicated to sequence language processing and stores one or more block-structured sequence control programs, and this sequence language processing board. It consists of a group of I/O boards that are installed on the lower side of a processor board dedicated to processing and exchange control information with control objects, and the processor board that processes the basic language is connected to the processor board dedicated to sequence language processing. - A programmable controller characterized in that a start instruction and an end instruction are notified to each of the block-configured sequence control programs in the board.