JPH03234049A - Surface treatment for external terminal of semiconductor package - Google Patents
Surface treatment for external terminal of semiconductor packageInfo
- Publication number
- JPH03234049A JPH03234049A JP3011590A JP3011590A JPH03234049A JP H03234049 A JPH03234049 A JP H03234049A JP 3011590 A JP3011590 A JP 3011590A JP 3011590 A JP3011590 A JP 3011590A JP H03234049 A JPH03234049 A JP H03234049A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- tin
- semiconductor package
- external terminal
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004381 surface treatment Methods 0.000 title claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910000679 solder Inorganic materials 0.000 claims abstract description 46
- 230000008018 melting Effects 0.000 claims abstract description 18
- 238000002844 melting Methods 0.000 claims abstract description 18
- 238000007747 plating Methods 0.000 claims description 22
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 230000035939 shock Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 229910000831 Steel Inorganic materials 0.000 description 4
- 239000010959 steel Substances 0.000 description 4
- 230000004907 flux Effects 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- 208000032544 Cicatrix Diseases 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 239000012442 inert solvent Substances 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 231100000241 scar Toxicity 0.000 description 1
- 230000037387 scars Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【発明の詳細な説明】
〔概要〕
編めつきされた外部端子に生じるボイスカー（ｌの針状
結晶）の発生を防止する半導体パッケージ外部端子の表
面処理方法に関し、
半導体パッケージに急激な熱衝撃等を与えないで錫ホイ
スカーの発生を完全に防止することを目的とし、
編めつき上の一部にはんだを付着させた半導体パッケー
ジの外部端子に、該はんだの融点以上で該錫めっきの融
点以下の温度で熱処理を行い、該外部端子の該編めつき
表出部に該はんだを加熱拡散させるように構成する。[Detailed Description of the Invention] [Summary] This invention relates to a method for surface treatment of external terminals of semiconductor packages that prevents the formation of voice cars (acicular crystals of l) that occur in braided external terminals. For the purpose of completely preventing the generation of tin whiskers by not exposing the external terminals of a semiconductor package to which solder is attached to a part of the braid, the temperature is higher than the melting point of the solder and lower than the melting point of the tin plating. The solder is heat-treated to diffuse the solder into the braided exposed portion of the external terminal.
本発明は、編めっきされた外部端子に生じるホイスカー
（ｗｈｓｋｅｒ）の発生を防止する半導体パッケージ外
部端子の表面処理方法に関する。The present invention relates to a method for surface treatment of external terminals of semiconductor packages, which prevents whiskers from occurring on braided external terminals.
近年、半導体パッケージの外部端子に生じる錫ホイスカ
ーにより電子、電気回路が短絡する危険性があることか
ら、−ボイスカーの発生を防止することが要求される。In recent years, there is a risk that electronic and electrical circuits may be short-circuited due to tin whiskers occurring at external terminals of semiconductor packages, so it is required to prevent the occurrence of -voice scars.
そのため、パッケージ等に影響を与えないで錫ボイスカ
ーの発生を防止する必要がある。Therefore, it is necessary to prevent the generation of tin voice ker without affecting the package or the like.
従来、半導体用パッケージの錫めっきされた外部端子に
生じる錫ホイスカーは、早いものでは数日、遅いもので
は数年後より錫めっき面から錫が針状結晶として成長し
、長いものでは数層にも成長する。この錫ボイスカーが
発生すると電子、電気回路の短絡を生じる場合があり、
高信頼性を要するコンピュータ、通信機圏ではその防止
策が不可欠な条件となっている。Conventionally, tin whiskers that occur on the tin-plated external terminals of semiconductor packages occur as needle-shaped crystals of tin that grow from the tin-plated surface as early as a few days or as slowly as several years later, and in the case of long ones, they grow into several layers. also grows. When this tin voice car occurs, it may cause a short circuit in electronic or electrical circuits.
Preventive measures are indispensable in computer and communication equipment areas that require high reliability.
そこで、従来より錫ホイスカーの発生を防止する方法が
考えられている。錫ホイスカーは、賜めつき液の添加剤
の影響、錫めっきの厚さ、素材との組合せ等により、そ
の成長に差があることが判明している。例えば、錫めっ
き液の添加剤をケトン系とし、めっき厚を厚くし、外部
端子の素材には真ちゅうを用いないようにすることで、
錫ボイスカーの発生をある程度防いでいる。この場合、
錫ホイスカーは発生し難くなるものの完全には防止する
ことができない。Therefore, methods for preventing the generation of tin whiskers have been considered. It has been found that the growth of tin whiskers varies depending on the influence of additives in the tinting solution, the thickness of tin plating, the combination with materials, etc. For example, by using a ketone-based additive in the tin plating solution, increasing the thickness of the plating, and not using brass as the material for the external terminals,
This prevents the occurrence of tin voice cars to some extent. in this case,
Although tin whiskers are less likely to occur, they cannot be completely prevented.
また、錫めっき被膜を錫の融点以上の高温で溶融処理を
行うことにより錫ホイスカーの発生を抑制する方法も考
えられている。Furthermore, a method of suppressing the generation of tin whiskers by melting the tin plating film at a high temperature higher than the melting point of tin has been considered.
さらには、半導体パッケージの外部端子全体を高温のは
んだ槽に浸漬してハンダで覆い、錫ボイスカーの発生を
防止するいわゆるはんだデイツプ処理を行う方法も考え
られている。Furthermore, a method has been considered in which the entire external terminals of a semiconductor package are immersed in a high-temperature solder bath and covered with solder to perform a so-called solder dip treatment to prevent the formation of tin voice cars.
しかし、上記錫めっき被膜を溶融処理することは、半導
体用パッケージも高温となりデバイス全体の信頼性が低
下するおそれがある。また、はんだデイツプ処理では、
外部端子全体を錫めっき面が残らないように完全にはん
だで覆う必要性のために高温のはんだ槽に浸漬すること
から、該パッケージへの熱衝撃が大きく、信頼性を損う
危険性があるという問題がある。However, when the tin plating film is melt-treated, the semiconductor package also becomes high temperature, which may reduce the reliability of the entire device. In addition, in solder dip processing,
Because the entire external terminal needs to be completely covered with solder so that no tin-plated surface remains, the package is immersed in a high-temperature solder bath, resulting in a large thermal shock to the package, which risks impairing reliability. There is a problem.
そこで、本発明は上記課題に鑑みなされたもので、半導
体パッケージに急激な熱衝撃等を与えないで錫ホイスカ
ーの発生を完全に防止する半導体パッケージ外部端子の
表面処理方法を提供することを目的とする。Therefore, the present invention was made in view of the above-mentioned problems, and an object thereof is to provide a method for surface treatment of external terminals of a semiconductor package that completely prevents the generation of tin whiskers without applying sudden thermal shock to the semiconductor package. do.
本発明は上記課題を解決するために、錫めっき上の一部
にはんだを付着させた半導体パッケージの外部端子に、
該はんだの融点以上で咳錫めっきの融点以下の温度で熱
処理を行い、該外部端子の該編めつき表出部に該はんだ
を加熱拡散させるものである。In order to solve the above problems, the present invention provides an external terminal of a semiconductor package in which solder is attached to a part of the tin plating.
Heat treatment is performed at a temperature above the melting point of the solder and below the melting point of the tin plating to heat and diffuse the solder into the braided exposed portion of the external terminal.
上述のように、半導体パッケージの外部端子に付着され
たはんだを錫めっき面全体に加熱拡散させて、該外部端
子上の純粋な錫めっき部分をはんだに覆われるようにし
ている。As described above, the solder attached to the external terminals of the semiconductor package is heated and diffused over the entire tin-plated surface so that the pure tin-plated portions on the external terminals are covered with solder.
すなわち、はんだの加熱拡散は、加熱温度がはんだの融
点以上で錫めっきの融点以下であることから、半導体パ
ッケージに急激な熱衝撃を与えることなく錫ボイスカー
の発生を完全に防止することが可能となる。In other words, since the heating temperature for solder diffusion is above the melting point of the solder and below the melting point of the tin plating, it is possible to completely prevent the generation of tin voice cars without applying sudden thermal shock to the semiconductor package. Become.
第１図に本発明の第１の実施例の説明図を示し、第２図
に第１の実施例の概念図を示す。図において、半導体パ
ッケージ１の外部端子２に錫めつき３を行う（第１図工
程１．第２図（Ａ））。これをプリント基板４に、はん
だ５により実装される（第１図工程２．第２図（Ｂ））
。そして、はんだ５の融点以上で錫めつき３の融点以下
の温度で加熱処理を行う（第１図工程３）。この場合、
はんだ５は加熱拡散され、外部端子２の錫めっき残部３
ａ全面が拡散したはんだ５ａにより覆われて外部端子２
上で純粋な錫めっきの表出部分の存在をなくしている（
第２図（Ｃ））。例えば、はんだ５はインジウム・錫（
Ｉｎ −８ｎ ’Ｊ共晶合金の低温はんだ（融点１１１
℃）を用いた場合、錫めつき３の融点が約２３０℃であ
ることから、１５０℃にて１時間加熱拡散処理が行われ
る。FIG. 1 shows an explanatory diagram of a first embodiment of the present invention, and FIG. 2 shows a conceptual diagram of the first embodiment. In the figure, tin plating 3 is performed on the external terminals 2 of the semiconductor package 1 (Step 1 in FIG. 1 and FIG. 2 (A)). This is mounted on the printed circuit board 4 with solder 5 (Step 2 in Figure 1, Figure 2 (B))
. Then, heat treatment is performed at a temperature above the melting point of the solder 5 and below the melting point of the tin plating 3 (Step 3 in FIG. 1). in this case,
The solder 5 is heated and diffused to remove the remaining tin plating 3 of the external terminal 2.
a The entire surface is covered with the diffused solder 5a and the external terminal 2
Eliminates the presence of pure tin plating on the top (
Figure 2 (C)). For example, solder 5 is indium tin (
In-8n'J eutectic alloy low temperature solder (melting point 111
℃), the melting point of tin plating 3 is about 230°C, so the heating diffusion treatment is performed at 150°C for 1 hour.
ここで、第１の実施例の加熱拡散処理をした場合としな
い場合の比較を第１表に示す。なお、プリント基板４は
ガラスエポキシ系多層構造もので、半導体パッケージは
第２図に示すような外部端子鋼めっきサーデイツプタイ
プＩＣを用いた。また、はんだ５は上述の１ｎ−８ｎ共
晶合金はんだを用い、フラックス（ミル規格Ｍ Ｉ Ｌ
−Ｆ−１４２５６ＴＹＰＥ ＲＭＡ相当〉を使用した
。そして、ＩＣを実装後加熱処理を行なった基板、及び
ＩＣを実装後加熱処理をしていない基板をそれぞれ５０
℃の恒温で５００時間、 １０００時間放置し、錫ボイ
スカーの発生、成長を観察したものである。Here, Table 1 shows a comparison between the case where the heat diffusion treatment of the first example was performed and the case where it was not performed. The printed circuit board 4 had a glass epoxy multilayer structure, and the semiconductor package used was a steel dip type IC with external terminals plated with steel as shown in FIG. In addition, the solder 5 uses the above-mentioned 1n-8n eutectic alloy solder, and flux (mil standard M I L
-F-14256TYPE RMA equivalent) was used. Then, 50 substrates each were heat-treated after mounting the IC, and 50 substrates were heat-treated after mounting the IC.
The specimens were left at a constant temperature of 500°C for 500 to 1000 hours, and the generation and growth of tin voice ker was observed.
第１表
第１表に示すように、加熱処理を行っていない基板では
試料Ｂ＋が１０００時間放置後で発生率１００％、最大
長さ１，４履の錫ホイスカーの発生、成長が確認された
。この錫ボイスカーは端子間を短絡させるのに十分な長
さである。これに対し、加熱処理を行った基板では試料
Ａｚ 、Ｂｚ共錫ホイスカーの発生は全くみられなかっ
た。Table 1 As shown in Table 1, on the substrate that was not heat-treated, the occurrence rate was 100% for sample B+ after being left for 1000 hours, and the generation and growth of tin whiskers with a maximum length of 1.4 shoes was confirmed. . This tin voice car is long enough to create a short between the terminals. On the other hand, in the heat-treated substrates, no tin whiskers were observed in both samples Az and Bz.
また、加熱処理をしていない基板の試料Ｂ１を１０００
時間放置後、本発明の加熱拡散処理を行った場合、長い
錫ホイスカーははんだの拡散により端子部に取込まれ、
その後さらに１０００時間放置しても錫ボイスカーの発
生はみられなかった。すなわち、実装後時間を経過して
いるものでも錫ホイスカーを除去し、その後の発生が防
止される。In addition, sample B1, which is a substrate that has not been heat-treated, was heated to 1000
When the heat diffusion treatment of the present invention is performed after standing for a period of time, the long tin whiskers are incorporated into the terminal part due to solder diffusion.
After that, no tin voice car was observed even after being left for another 1000 hours. In other words, tin whiskers are removed even if some time has passed since they were mounted, and their subsequent occurrence is prevented.
このように、基板実装後に発生する錫ホイスカーを完全
に抑えることができるとともとに、既に錫ホイスカーの
発生している基板に対して加熱拡散処理を行うことによ
り錫ホイスカーを除去することができる。In this way, tin whiskers that occur after board mounting can be completely suppressed, and tin whiskers can be removed by performing heat diffusion treatment on a board that already has tin whiskers. .
次に、第３図に本発明の第２の実施例の説明図を示し、
第４図に第２の実施例の概念図を示す。Next, FIG. 3 shows an explanatory diagram of the second embodiment of the present invention,
FIG. 4 shows a conceptual diagram of the second embodiment.
図において、まず、半導体パッケージ１の外部端子２へ
錫めっき３を行う（第３図工程１．第４図（Ａ））。ま
た、外部端子２上の錫めっき面３の一部分（例えば、シ
ーテイングプレーン６付近まで）に、錫めっきの一部分
３ａを残す用にして、ハンダ５を付着する（第３ｖＡ工
程２．第４図（Ｂ））。この場合の錫めつき３（融点約
２３０℃）及びはんだ５（融点１１７℃）は第１の実施
例と同様である。そして、第１の実施例と同様に、１５
０℃で１時間加熱処理を行う（第３図工程３）。この加
熱処理により、はんだ５が加熱拡散され、はんだ５ａが
錫めっき残部３ａの全面を覆い、純粋な錫めっき部分の
表出をなくしている（第４図（Ｃ））。In the figure, first, tin plating 3 is performed on the external terminals 2 of the semiconductor package 1 (Step 1 in FIG. 3 and FIG. 4(A)). Further, solder 5 is attached to a portion of the tin-plated surface 3 on the external terminal 2 (for example, up to the vicinity of the seating plane 6), leaving a portion 3a of the tin-plating (3rd vA step 2. (B)). In this case, the tin plating 3 (melting point: about 230° C.) and the solder 5 (melting point: 117° C.) are the same as in the first embodiment. Then, as in the first embodiment, 15
Heat treatment is performed at 0° C. for 1 hour (Step 3 in Figure 3). By this heat treatment, the solder 5 is heated and diffused, and the solder 5a covers the entire surface of the tin-plated remaining portion 3a, so that the pure tin-plated portion is not exposed (FIG. 4(C)).
ここで、第２の実施例の加熱拡散処理をした場合としな
い場合の比較を第２表に示す。Here, Table 2 shows a comparison between the case where the heat diffusion treatment of the second example was performed and the case where it was not performed.
第２表
なお、半導体パッケージは、第４図に示すように外部端
子鋼めっきサーデイツプタイプＩＣを用い、試料１は従
来通り何も処理していないＩＣであり、試料２は本発明
の第２の実施例の処理を行なったＩＣであり、試料３は
、本発明の第２の実施例の別の方法であり、はんだ付着
債の加熱処理をベーパフェーズソルダリング装置（ＶＰ
Ｓ）により行ない、はんだ５を加熱拡散させたものであ
る。このＶＰＳは、不活性溶剤の高温蒸気（ベーパー）
（約２１５℃）によりはんだ付けを行なう方法である
。Table 2 Note that the semiconductor package uses a steel dip type IC with external terminal steel plating as shown in FIG. Sample 3 is an IC subjected to the treatment of the second embodiment of the present invention, and sample 3 is an IC processed by another method of the second embodiment of the present invention, in which the heat treatment of the solder bond is performed using a vapor phase soldering device (VP).
S), and the solder 5 is heated and diffused. This VPS uses high-temperature steam (vapor) of inert solvent.
(approximately 215°C).
そして、試料１〜３の半導体パッケージをｌＴｌ−８１
共品合金はんだでプリント基板に実装（プリント基板、
使用フラックスは第１の実施例のものと同一）シ、それ
ぞれ５０℃の恒温にて５００時間、 １００時間放置
し、錫ボイスカーの発生、成長を観察したものである。Then, the semiconductor packages of samples 1 to 3 were
Mounted on a printed circuit board using common alloy solder (printed circuit board,
The flux used was the same as that in the first example), and the samples were left at a constant temperature of 50° C. for 500 hours and 100 hours, respectively, and the generation and growth of tin voice ker was observed.
第２表に示すように、従来方式の試料１の半導体パッケ
ージは１０００時間放置後に、発生率１００％。As shown in Table 2, the conventional semiconductor package of Sample 1 had a 100% occurrence rate after being left for 1000 hours.
最大長さ１．４ａｍの錫ボイスカーの発生、成長が確認
された。これは、端子間を短絡させるのに十分な長さで
ある。これに対し、本発明の処理を行なった試料２．３
では錫ホイスカーの発生が全くなかった。The generation and growth of a tin voice car with a maximum length of 1.4 am was confirmed. This is long enough to create a short between the terminals. In contrast, sample 2.3 treated according to the present invention
There was no occurrence of tin whiskers.
このように、半導体パッケージのボディ部がはんだ槽に
触れずにはんだデイツプ処理を行うことができ、該半導
体パッケージに熱衝機を与えることなく錫ボイスカーの
発生を防止することができる。第１の実施例はプリント
基板実装後に加熱処理を行うのに対し、第２の実施例は
実装前（例えば組立工程、購入段階）に加熱処理を行っ
て錫ホイスカーの発生を防止するものである。In this way, the solder dip process can be performed without the body of the semiconductor package touching the solder bath, and the generation of tin voice ker can be prevented without applying a thermal shock to the semiconductor package. In the first embodiment, heat treatment is performed after mounting the printed circuit board, whereas in the second embodiment, heat treatment is performed before mounting (for example, in the assembly process or purchasing stage) to prevent the generation of tin whiskers. .
なお、加熱拡散処理の方法として前述のｖＰＳを用いて
もよく、また、はんだの拡散を容易にするために外部端
？１．：前述のようなフラックスを塗布した後に加熱拡
散処理を行ってもよい。Note that the above-mentioned vPS may be used as a heating diffusion treatment method, and the outer end may be used to facilitate solder diffusion. 1. : Heat diffusion treatment may be performed after applying the flux as described above.
以上のように本発明によれば、半導体パッケージの外部
端子に付着されたはんだを錫めっき面全体に加熱拡散さ
せることにより、半導体パッケージに熱衝撃を与えるこ
となく錫ボイスカーの発生を完全に防止することができ
、これにより、錫めっき端子を有する半導体パッケージ
の信頼性及びこれを使用したシステムの信頼性を向上さ
せることができる。As described above, according to the present invention, by heating and diffusing the solder attached to the external terminals of the semiconductor package over the entire tin-plated surface, the generation of tin voice cars can be completely prevented without applying thermal shock to the semiconductor package. As a result, the reliability of a semiconductor package having tin-plated terminals and the reliability of a system using the same can be improved.
第１図は本発明の第１の実施例の説明図、第２図は第１
の実施例の概念図、
第３図は本発明の第２の実施例の説明図、第４図は第２
の実施例の概念図である。
図において、
１は半導体パッケージ、
２は外部端子、
３は錫めっき、
４はプリント基板、
５ははんだ
を示す。FIG. 1 is an explanatory diagram of the first embodiment of the present invention, and FIG. 2 is an explanatory diagram of the first embodiment of the present invention.
3 is an explanatory diagram of the second embodiment of the present invention, and FIG. 4 is a conceptual diagram of the second embodiment of the present invention.
It is a conceptual diagram of an example of. In the figure, 1 is a semiconductor package, 2 is an external terminal, 3 is a tin plating, 4 is a printed circuit board, and 5 is a solder.
Claims (1)
導体パッケージ（１）の外部端子（２）に、 該はんだ（５）の融点以上で該錫めっき（３）の融点以
下の温度で熱処理を行い、該外部端子（２）の該錫めっ
き（３）表出部に該はんだ（５）を加熱拡散させること
を特徴とする半導体パッケージ外部端子の表面処理方法
。[Claims] The tin plating (3) is applied to the external terminal (2) of the semiconductor package (1) with the solder (5) adhered to a portion of the tin plating (3) at a temperature higher than the melting point of the solder (5). 3) A surface treatment for an external terminal of a semiconductor package, characterized in that heat treatment is performed at a temperature below the melting point of the external terminal (2) to heat and diffuse the solder (5) onto the exposed portion of the tin plating (3) of the external terminal (2). Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3011590A JPH03234049A (en) | 1990-02-09 | 1990-02-09 | Surface treatment for external terminal of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3011590A JPH03234049A (en) | 1990-02-09 | 1990-02-09 | Surface treatment for external terminal of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03234049A true JPH03234049A (en) | 1991-10-18 |
Family
ID=12294785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3011590A Pending JPH03234049A (en) | 1990-02-09 | 1990-02-09 | Surface treatment for external terminal of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03234049A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006074017A (en) * | 2004-09-04 | 2006-03-16 | Samsung Techwin Co Ltd | Lead frame and its manufacturing method |
| JP2007081235A (en) * | 2005-09-15 | 2007-03-29 | Renesas Technology Corp | Method of manufacturing semiconductor device |
-
1990
- 1990-02-09 JP JP3011590A patent/JPH03234049A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006074017A (en) * | 2004-09-04 | 2006-03-16 | Samsung Techwin Co Ltd | Lead frame and its manufacturing method |
| JP2007081235A (en) * | 2005-09-15 | 2007-03-29 | Renesas Technology Corp | Method of manufacturing semiconductor device |
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