JPH07273263A - External terminal of electronic component - Google Patents

External terminal of electronic component

Info

Publication number
JPH07273263A
JPH07273263A JP6170694A JP6170694A JPH07273263A JP H07273263 A JPH07273263 A JP H07273263A JP 6170694 A JP6170694 A JP 6170694A JP 6170694 A JP6170694 A JP 6170694A JP H07273263 A JPH07273263 A JP H07273263A
Authority
JP
Japan
Prior art keywords
tin
lead
melting point
alloy
external terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6170694A
Other languages
Japanese (ja)
Inventor
Kazuto Akagi
和人 赤城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6170694A priority Critical patent/JPH07273263A/en
Publication of JPH07273263A publication Critical patent/JPH07273263A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a external terminal of electronic components such as an IC which does not cause ICs or other electronic components or a printed wiring board itself to be damaged, makes it difficult to oxidize the external terminal of ICs. and achieves a high-quality solderability. CONSTITUTION:Tin - lead alloy with 61.9%, or higher tin within a melting point of 183-231.9 deg.C or an alloy whose melting point is reduced by adding other metals (for example, bismuth) to tin and lead is coated on the surface of a lead 4 of an IC 1 as an intermediate layer 5 and further tin- lead alloy with 60%, or higher lead within a melting point of 231.9-327.4 deg.C melting at a higher temperature than the melting point of tin or an alloy whose melting point is increased by adding other metals (for example, silver) to tin and lead is coated on the coated surface as an outermost layer 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、樹脂封止型半導体装
置、スライドスイッチ、コネクターなどの外部端子のは
んだメッキに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to solder plating of external terminals such as resin-sealed semiconductor devices, slide switches and connectors.

【0002】[0002]

【従来の技術】先ず、図3及び図4を用いて従来技術の
電子部品の外部端子を説明する。なお、以下の説明にお
いては、電子部品として樹脂封止型半導体装置(「I
C」と略記する)を代表に取り挙げて説明するが、この
発明はICに限定されるものではないことを付言してお
く。図3は従来技術のICの一例を示した一部断面側面
図であり、図4は従来技術のICの他の例を示した一部
断面側面図である。
2. Description of the Related Art First, an external terminal of a conventional electronic component will be described with reference to FIGS. In the following description, a resin-sealed semiconductor device (“I
(Abbreviated as “C”) will be described as a representative, but it should be added that the present invention is not limited to the IC. 3 is a partial cross-sectional side view showing an example of a conventional art IC, and FIG. 4 is a partial cross-sectional side view showing another example of a conventional art IC.

【0003】図3に示したように、従来のこの種のIC
11は、半導体集積回路を形成した後、その半導体集積
回路を保護するために、複数の外部端子13を外部に導
出させるようにして封止樹脂12で封止されている。そ
れらの外部端子13はプリント基板等に実装する場合の
はんだ付け性を良くするために、リード14の表面には
んだ層として錫を多く含む融点183°C以上231.
9°C未満の範囲に入る錫61.9%以上の錫─鉛合金
及び錫─鉛に他の金属(例えば、ビスマスなど)を加
え、融点を更に下げた合金層と錫の金属層の内、いづれ
か一方のはんだ層15が被覆されていた。
As shown in FIG. 3, a conventional IC of this type is used.
After forming the semiconductor integrated circuit, 11 is sealed with a sealing resin 12 so that the plurality of external terminals 13 are led out to protect the semiconductor integrated circuit. These external terminals 13 have a melting point of 183 ° C. or more containing a large amount of tin as a solder layer on the surface of the lead 14 in order to improve solderability when mounted on a printed circuit board or the like.
Of the tin-lead alloy and tin-lead alloy containing 61.9% or more of tin falling within the range of less than 9 ° C and another metal (for example, bismuth) added to the alloy layer and the metal layer of tin to further lower the melting point. Either one of the solder layers 15 was covered.

【0004】この外部端子13の表層のはんだ層15
は、前記のように、融点183°Cから融点231.9
°Cの低融点のため、このはんだ層15の融点以上の温
度で作業が行われるとはんだ層15が溶けて、本来、一
様の厚さで被覆されているはんだ層15が不均一にな
り、外部端子13の太さが太くなるなどして、作業工程
上、またICの品質上好ましくない現象が生じた。
The solder layer 15 on the surface of the external terminal 13
As described above, the melting point is 183 ° C. to the melting point 231.9.
Because of the low melting point of ° C, when the work is performed at a temperature higher than the melting point of the solder layer 15, the solder layer 15 melts, and the solder layer 15 originally covered with a uniform thickness becomes non-uniform. As a result, the thickness of the external terminal 13 is increased, which causes an undesirable phenomenon in the work process and the quality of the IC.

【0005】そのため、リード14にはんだ層15を被
覆する作業工程は、融点以上の高温に曝される作業の後
に持ってくるという制限が課せられ、製造工程の手順を
自由に変更することが不可能であり、作業の効率化を図
ることができないという欠点がある。また、融点の高い
鉛または錫のみの金属層を形成するという考え方もある
が、外部端子のプリント基板への実装時には高品質のは
んだ付け性が得られないという欠点もあった。
Therefore, the work process of coating the solder layer 15 on the leads 14 is restricted to be brought after the work exposed to a high temperature higher than the melting point, and it is not possible to freely change the procedure of the manufacturing process. It is possible, and there is a drawback that the work efficiency cannot be improved. Further, there is an idea of forming a metal layer of only lead or tin having a high melting point, but there is a drawback that high quality solderability cannot be obtained when the external terminal is mounted on the printed board.

【0006】これらの欠点を解消する目的のICが、例
えば、特開平1─110754号「樹脂封止型半導体集
積回路装置」の公開特許公報に開示されている。このI
Cを図4に示した。このIC11Aの外部端子13A
は、プリント基板等に実装する場合のはんだ付け性を良
くするために、リード14の表面にはんだ層として錫の
金属層か錫を多く含む錫─鉛合金属のいづれか一方の中
間層16と鉛の金属層の最外層17の二重層で被覆して
いる。
An IC for the purpose of eliminating these drawbacks is disclosed in, for example, Japanese Unexamined Patent Publication No. 1-1110754, "Resin-sealed semiconductor integrated circuit device". This I
C is shown in FIG. External terminal 13A of this IC 11A
In order to improve the solderability when mounting on a printed circuit board or the like, the lead 14 has a metal layer of tin as a solder layer or a tin-lead alloy containing a large amount of tin on the intermediate layer 16 and a lead layer. The outermost metal layer 17 is covered with a double layer.

【0007】[0007]

【発明が解決しようとする課題】しかし、この外部端子
13Aの構造では、最外層17が鉛の金属層であること
から、はんだ付け工程中にICや他の電子部品、或いは
印刷配線基板を高温(327.4°C以上)に曝さなけ
ればならず、それらの品質に好ましくない悪影響を与
え、また、高温下において作業を行わなければならず、
作業の安全上においても好ましくない。
However, in the structure of the external terminal 13A, since the outermost layer 17 is a lead metal layer, the IC, other electronic components, or the printed wiring board is heated to a high temperature during the soldering process. Have to be exposed to (327.4 ° C or higher), have an unfavorable adverse effect on their quality, and have to work at high temperatures,
It is not preferable in terms of work safety.

【0008】また、前記中間層16と前記最外層17の
それぞれの厚さを制御する必要がある。仮に最外層17
の鉛の厚みが全体の90%であった場合、溶融後の皮膜
は、錫の比率が最大でも10%にしかならず、高融点に
なり、実装時に高品質のはんだ付け性が得られないばか
りでなく、鉛の酸化膜が生成し、この酸化膜の生成はは
んだの生成よりも早く、かつ厚いために一層高品質のは
んだ付け性が得られない。従って、実装時に所望の比率
の錫─鉛合金層の外部端子を得ることが困難であり、外
部端子13Aのプリント基板への実装時に高品質のはん
だ付け性が得られないという欠点もあった。
Further, it is necessary to control the thickness of each of the intermediate layer 16 and the outermost layer 17. The outermost layer 17
If the lead has a thickness of 90% of the total, the film after melting has a tin content of only 10% at the maximum, has a high melting point, and does not only provide high-quality solderability during mounting. However, a lead oxide film is formed, and the formation of this oxide film is faster than that of solder and is thicker, so that higher quality solderability cannot be obtained. Therefore, it is difficult to obtain a desired ratio of the external terminal of the tin-lead alloy layer at the time of mounting, and there is also a drawback that high quality solderability cannot be obtained at the time of mounting the external terminal 13A on the printed board.

【0009】[0009]

【課題を解決するための手段】そのため、この発明のI
Cは、その複数の外部端子を、融点183°C以上融点
231.9°C未満の範囲に入る錫61.9%以上の錫
を多く含む錫ー鉛合金か、錫、鉛に他の金属(例えば、
ビスマスなど)を加え、融点を更に下げた合金か、錫の
内のいづれか一つで形成された中間層と、錫の融点23
1.9°Cよりも高温で、且つ鉛の融点327.4°C
より低温の範囲に入る鉛60%以上の錫ー鉛合金か、
錫、鉛に他の金属(例えば、銀など)を加え、融点を更
に上げた合金のいづれか一方で形成された最外層とで被
覆して構成した。
Therefore, I of the present invention
C is a tin-lead alloy containing a large amount of tin with a melting point of 183 ° C. or more and a melting point of less than 231.9 ° C. and containing 61.9% or more of tin. (For example,
Bismuth or the like) to lower the melting point of the alloy or an intermediate layer formed of either one of tin and the melting point of tin 23
Higher than 1.9 ° C and melting point of lead 327.4 ° C
A tin-lead alloy with 60% or more lead in the lower temperature range,
Other metals (for example, silver) are added to tin and lead, and the alloy is coated with the outermost layer formed by one of alloys having a higher melting point.

【0010】[0010]

【作用】従って、このICを印刷配線基板に実装する場
合に、外部端子を被覆している中間層と最外層とが溶融
した後に、その被覆層の融点が231.9°C以下にす
ることができ、実装時に高品質のはんだ付け性が得られ
る。更に、印刷配線基板に実装する場合に、鉛の融点3
27.4°Cよりも低温で作業を行うことができる。
Therefore, when this IC is mounted on a printed wiring board, the melting point of the coating layer should be 231.9 ° C. or less after the intermediate layer and the outermost layer coating the external terminals are melted. And high quality solderability can be obtained during mounting. Furthermore, when mounted on a printed wiring board, the melting point of lead is 3
It is possible to work at temperatures below 27.4 ° C.

【0011】[0011]

【実施例】以下、図1及び図2を用いて、この発明の実
施例を説明する。図1はこの発明のICの第1の実施例
の一部断面側面図であり、図2はこの発明のICの第2
の実施例の一部断面側面図である。なお、従来技術のI
Cの構成と同一の構成部分には同一の符号を付して説明
する。
Embodiments of the present invention will be described below with reference to FIGS. 1 is a partial sectional side view of a first embodiment of an IC of the present invention, and FIG. 2 is a second side view of an IC of the present invention.
It is a partial cross-sectional side view of the Example of FIG. In addition, I of the conventional technique
The same components as those of the configuration C will be described with the same reference numerals.

【0012】この第1の実施例のIC1では、封止樹脂
2から導出した外部端子3を、リード4の表面に、例え
ば、錫70%、鉛30%の錫─鉛合金を約9μmの厚さ
で中間層5として被覆し、更にこの表面に、例えば、錫
10%、鉛90%の錫─鉛合金を約1μmの厚さで最外
層6として被覆した。これら中間層5及び最外層6の錫
─鉛合金層が溶融した後の合金比率は錫64%、鉛36
%の合金皮膜になり、その融点は183°Cから23
1.9°Cの範囲に入って、はんだ付け性に優れた皮膜
が得られる。
In the IC 1 of the first embodiment, the external terminal 3 led out from the sealing resin 2 is formed on the surface of the lead 4 with a tin-lead alloy of 70% tin and 30% lead having a thickness of about 9 μm. Then, as the intermediate layer 5, a tin-lead alloy of 10% tin and 90% lead was coated on the surface as the outermost layer 6 in a thickness of about 1 μm. The alloy ratio after melting of the tin-lead alloy layers of the intermediate layer 5 and the outermost layer 6 is 64% tin and 36% lead.
% Alloy film with a melting point of 183 ° C to 23
When the temperature falls within the range of 1.9 ° C, a film having excellent solderability can be obtained.

【0013】前記中間層5の融点183°C以上23
1.9°C未満の範囲に入る61.9%以上の錫を多く
含む錫─鉛合金皮膜の代わりに、錫、鉛に他の金属(例
えば、ビスマスなど)を加え、融点を下げた合金の皮膜
を中間層5とし、最外層6として前記の成分比の錫─鉛
合金皮膜を形成してもよい。これら中間層5と最外層6
とは電気メッキにより形成することができる。
The melting point of the intermediate layer 5 is 183 ° C. or higher 23
Instead of a tin-lead alloy coating containing a large amount of tin of 61.9% or more falling within the range of less than 1.9 ° C, tin, an alloy in which another metal (for example, bismuth) is added to lead to lower the melting point Alternatively, the tin-lead alloy film having the above component ratio may be formed as the intermediate layer 5 and the outermost layer 6 as the film. These middle layer 5 and outermost layer 6
And can be formed by electroplating.

【0014】第2の実施例のIC1Aでは、図2に示し
たように、封止樹脂2から導出した外部端子3Aを、リ
ード4の表面に、例えば、厚さ6μmの錫の金属皮膜を
中間層7として被覆し、更にその上に最外層8として、
錫の融点231.9°Cよりも高温で、鉛の融点32
7.4°Cよりも低温の範囲に入る錫10%、鉛90%
の錫─鉛合金を厚さ約4μmの皮膜を被覆した。これら
中間層7及び最外層8の錫─鉛合金層が溶融した後の合
金比率は錫64%、鉛36%の合金皮膜になり、その融
点は183°Cから231.9°Cの範囲に入って、は
んだ付け性に優れた良好な皮膜が得られる。前記最外層
8の前記融点231.9°Cから327.4°Cの範囲
に入る錫─鉛合金の代わりに、錫、鉛に他の金属(例え
ば、銀など)を加え、融点を下げた合金を用いてもよ
い。
In the IC 1A of the second embodiment, as shown in FIG. 2, the external terminal 3A derived from the sealing resin 2 is provided on the surface of the lead 4 with, for example, a tin metal film having a thickness of 6 μm as an intermediate layer. As a layer 7, a further outermost layer 8 is formed thereon,
At a temperature higher than the melting point of tin 231.9 ° C, the melting point of lead 32
10% tin and 90% lead, which are in the temperature range below 7.4 ° C
Of tin-lead alloy was coated to a thickness of about 4 μm. The alloy ratio after melting of the tin-lead alloy layers of the intermediate layer 7 and the outermost layer 8 becomes an alloy film of 64% tin and 36% lead, and the melting point thereof is in the range of 183 ° C to 231.9 ° C. Upon entering, a good film with excellent solderability can be obtained. The melting point of the outermost layer 8 was lowered by adding another metal (for example, silver) to tin or lead instead of the tin-lead alloy falling within the range of 231.9 ° C to 327.4 ° C. Alloys may be used.

【0015】[0015]

【発明の効果】以上、説明したように、この発明のIC
の外部端子では、被覆されている層が、中間層及び最外
層を含めて考えた場合に、錫を多く含む融点183°C
から231.9°Cの範囲に入る錫61.9%以上の錫
─鉛合金か、錫、鉛に他の金属を加え、融点を更に下げ
た合金層となることから、この発明のICを印刷配線基
板に実装した時に、そのICや他の電子部品、或いは印
刷配線基板が加熱されるなどの悪影響を受けることがな
く、高品質のはんだ付け性が得られる。
As described above, the IC of the present invention
In the external terminal of, the coating layer, including the intermediate layer and the outermost layer, contains a large amount of tin and has a melting point of 183 ° C.
From 231.9 ° C to 231.9 ° C, a tin-lead alloy with a tin content of 61.9% or more, or an alloy layer in which another metal is added to tin or lead to further lower the melting point. When mounted on a printed wiring board, high quality solderability can be obtained without adverse effects such as heating of the IC, other electronic components, or the printed wiring board.

【0016】また、最外層が鉛でないため、酸化膜の生
成が遅く、膜厚が薄いために、このICを印刷配線基板
に実装する時に高品質のはんだ付け性が得られる。な
お、従来技術のICと同様に、作業中、最外層が溶けて
表面が不均一になることがなく、作業工程の手順も自由
に変更できるので作業の効率化が図れるなど、同様の効
果が得られることは言うまでもない。
Further, since the outermost layer is not lead, the oxide film is produced slowly and the film thickness is thin. Therefore, when this IC is mounted on a printed wiring board, high quality solderability can be obtained. Similar to the IC of the prior art, the outermost layer does not melt and the surface does not become non-uniform during the work, and the procedure of the work process can be freely changed, so that the work efficiency can be improved. It goes without saying that you can get it.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明のICの第1の実施例の一部断面側
面図である。
FIG. 1 is a partial sectional side view of a first embodiment of an IC of the present invention.

【図2】 この発明のICの第2の実施例の一部断面側
面図である。
FIG. 2 is a side view, partly in section, of a second embodiment of the IC of the present invention.

【図3】 従来技術のICの一例を示した一部断面側面
図である。
FIG. 3 is a partial cross-sectional side view showing an example of a conventional IC.

【図4】 従来技術のICの他の一例を示した一部断面
側面図である。
FIG. 4 is a partial cross-sectional side view showing another example of a conventional IC.

【符号の説明】[Explanation of symbols]

1 第1の実施例の樹脂封止型半導体装置(IC) 1A 第2の実施例の樹脂封止型半導体装置(IC) 3 外部端子 3A 外部端子 4 リード 5 中間層 6 最外層 7 中間層 8 最外層 1 Resin-Encapsulated Semiconductor Device (IC) 1A of First Example 1A Resin-Encapsulated Semiconductor Device (IC) of Second Example 3 External Terminal 3A External Terminal 4 Lead 5 Intermediate Layer 6 Outermost Layer 7 Intermediate Layer 8 Outermost layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電子部品の外部端子が、融点183°C
以上231.9°C未満の範囲に入る61.9%以上の
錫を多く含む錫ー鉛合金か、錫、鉛に他の金属(例え
ば、ビスマスなど)を加え、融点を下げた合金か、錫の
内のいづれか一つで形成された中間層と、錫の融点23
1.9°Cよりも高温で、且つ鉛の融点327.4°C
より低温の範囲に入る鉛60%以上の錫ー鉛合金か、
錫、鉛に他の金属(例えば、銀など)を加え、融点を上
げた合金のいづれか一方で形成された最外層とで被覆さ
れていることを特徴とする電子部品の外部端子。
1. The external terminal of an electronic component has a melting point of 183 ° C.
Is a tin-lead alloy containing a large amount of tin of 61.9% or more falling within the range of less than 231.9 ° C, or an alloy having a melting point lowered by adding another metal (such as bismuth) to tin or lead, or An intermediate layer formed of one of tin and a melting point of tin 23
Higher than 1.9 ° C and melting point of lead 327.4 ° C
A tin-lead alloy with 60% or more lead in the lower temperature range,
An external terminal for an electronic component, characterized in that it is covered with an outermost layer formed by adding tin or lead to another metal (for example, silver) and either one of alloys having a higher melting point.
JP6170694A 1994-03-30 1994-03-30 External terminal of electronic component Pending JPH07273263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6170694A JPH07273263A (en) 1994-03-30 1994-03-30 External terminal of electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6170694A JPH07273263A (en) 1994-03-30 1994-03-30 External terminal of electronic component

Publications (1)

Publication Number Publication Date
JPH07273263A true JPH07273263A (en) 1995-10-20

Family

ID=13178953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6170694A Pending JPH07273263A (en) 1994-03-30 1994-03-30 External terminal of electronic component

Country Status (1)

Country Link
JP (1) JPH07273263A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009070997A (en) * 2007-09-12 2009-04-02 Toyota Motor Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009070997A (en) * 2007-09-12 2009-04-02 Toyota Motor Corp Semiconductor device

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