JP2002289652A - Semiconductor device tape carrier and its manufacturing method - Google Patents

Semiconductor device tape carrier and its manufacturing method

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Publication number
JP2002289652A
JP2002289652A JP2001086912A JP2001086912A JP2002289652A JP 2002289652 A JP2002289652 A JP 2002289652A JP 2001086912 A JP2001086912 A JP 2001086912A JP 2001086912 A JP2001086912 A JP 2001086912A JP 2002289652 A JP2002289652 A JP 2002289652A
Authority
JP
Japan
Prior art keywords
tin
thickness
layer
tin plating
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001086912A
Other languages
Japanese (ja)
Inventor
Hisanori Akino
久則 秋野
Masahiro Mizuno
雅裕 水野
Masaru Sugano
優 菅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2001086912A priority Critical patent/JP2002289652A/en
Publication of JP2002289652A publication Critical patent/JP2002289652A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Abstract

PROBLEM TO BE SOLVED: To prevent excess melting of copper of a lead wire in a lower part of a solder resist and suppress the whisker of tin plating in a semiconductor device tape carrier. SOLUTION: The solder resist 6 is applied in a position except its terminal portion on a copper foil wiring pattern 3 which is formed on a dielectric film 1 via an adhesive layer 2, thereafter, a thin tin-plated layer of 0.01 to 0.2 μm in thickness is formed on the terminal portion as first tin plating treatment, and a pure tin layer 4a and a tin-copper alloy layer 5a of 0.20 μm or less are formed by heat treatment. Then, a pure tin plating layer of 0.15 to 0.80 μm in thickness is formed on the terminal portion as a second tin plating treatment, and a pure tin layer 4b of 0.15 to 0.80 μm in thickness and a tin-copper alloy layer 5b of 0.20 μm or more in thickness are formed by heat treatment.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、精密電子部品であ
るTABテープキャリアのような半導体装置用テープキ
ャリア、特にその銅箔の配線パターンにスズめっきを行
うに際し、ソルダーレジスト際の銅の喰われを防止した
構造のテープキャリア及びスズめっき手法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape carrier for semiconductor devices such as a TAB tape carrier, which is a precision electronic component, and more particularly, to tin plating on a wiring pattern of a copper foil when copper is solder resisted. And a tin plating method.

【0002】[0002]

【従来の技術】従来のTABテープキャリアの構造は、
図2に示すように、ポリイミド樹脂製絶縁フィルム1に
接着剤層2を介して貼り合わせた銅箔に所定の配線パタ
ーン3を形成し(図2(a))、その配線パターン3上
には、その銅リード3a等の端子部分を除く所定の位置
に、絶縁層としてソルダーレジスト6を印刷塗布し(図
2(b))、その後、当該配線パターン3の端子部分で
ある銅リード3aに安定した接合性を与えるために、無
電解スズめっきにより純スズめっき層4を形成し(図2
(c))、加熱処理によりスズ−銅合金層5を形成した
構造(図2(d))である。
2. Description of the Related Art The structure of a conventional TAB tape carrier is as follows.
As shown in FIG. 2, a predetermined wiring pattern 3 is formed on a copper foil bonded to an insulating film 1 made of a polyimide resin via an adhesive layer 2 (FIG. 2A). Then, a solder resist 6 is printed and applied as an insulating layer at a predetermined position except for the terminal portions such as the copper leads 3a (FIG. 2B). The pure tin plating layer 4 is formed by electroless tin plating in order to provide the improved bonding property.
FIG. 2C shows a structure in which a tin-copper alloy layer 5 is formed by a heat treatment (FIG. 2D).

【0003】このTABテープキャリアの半導体素子へ
の実装作業は、例えば図3に示すように半導体素子(I
Cチップ)7をデバイスホールに位置するように配置
し、デバイスホールに突出したインナーリードと半導体
素子7の電極を位置合わせした後、ボンディングツール
により圧着する。半導体素子7の電極には金バンプ8が
形成されており、加熱された状態で銅リード3aに圧着
されると、スズめっきが溶融し金−スズ合金が形成し、
電極とインナーリードが接合される。
[0003] The work of mounting the TAB tape carrier on a semiconductor device is performed, for example, as shown in FIG.
The C chip 7 is arranged so as to be located in the device hole, and the inner lead projecting into the device hole and the electrode of the semiconductor element 7 are aligned, and then pressure-bonded by a bonding tool. Gold bumps 8 are formed on the electrodes of the semiconductor element 7, and when pressed against the copper leads 3a in a heated state, the tin plating melts to form a gold-tin alloy,
The electrode and the inner lead are joined.

【0004】[0004]

【発明が解決しようとする課題】一般にスズめっきは、
耐食性、はんだ付け性に優れていることから電子部品に
広く使用されている。
In general, tin plating is
It is widely used in electronic components because of its excellent corrosion resistance and solderability.

【0005】しかしながら、上記した従来のTABテー
プキャリアにおいては、無電解スズめっきする際に、図
4に示すように、ソルダーレジスト6の下方の際部(端
部)にて銅が過剰溶解し、銅リード3aに溝状に浸食さ
れた部分(過剰溶解部9)を形成し、リード強度を低下
させるという問題がある。
However, in the above-described conventional TAB tape carrier, when electroless tin plating is performed, as shown in FIG. 4, copper excessively dissolves at the edge (end) below the solder resist 6, There is a problem that a groove-eroded portion (excess melting portion 9) is formed in the copper lead 3a, and the lead strength is reduced.

【0006】一般に無電解スズめっきは銅との置換で析
出するが、この場合、無電解スズめっきの前処理液がソ
ルダーレジスト下方は浸透しにくく、銅表面に有機物の
残さ、汚染物等が残り、無電解スズめっき時に反応速度
が著しく早くなり、銅が過剰に溶解する。
In general, electroless tin plating is precipitated by substitution with copper. In this case, the pretreatment liquid for electroless tin plating hardly penetrates below the solder resist, and organic substances and contaminants remain on the copper surface. At the time of electroless tin plating, the reaction speed is remarkably increased, and copper is excessively dissolved.

【0007】さらに最近では微細配線パターン化の要求
が強くなっており、めっき面積がより小さくなっている
ことから、めっき面積の大きいところと微細な部分で、
無電解スズめっき時に反応速度に差が生じる。特に、微
細部では無電解スズめっきの反応速度が早くなり、銅が
過剰溶解しリード強度が低下する。
[0007] More recently, the demand for fine wiring patterning has become stronger, and the plating area has become smaller.
A difference occurs in the reaction rate during electroless tin plating. In particular, the reaction rate of the electroless tin plating is increased in the fine part, and the copper is excessively dissolved to lower the lead strength.

【0008】他の問題点として、スズめっき皮膜はスズ
めっき直後、放置するとホイスカ(ひげ状の結晶)が発
生することが良く知られており、特に微細ピッチのパタ
ーンではホイスカの発生がショートの原因となるため、
種々の検討が行われてきた。このスズホイスカの抑制手
段としては、(1) 下地めっきとして、ニッケル、銅、
鉛、はんだ、スズ−ニッケル合金、スズ−銅合金層を形
成する。(2) めっき後にリフロー処理を施す。(3) めっ
き後に加熱してアニール処理を施す。(4) スズめっきを
他のスズ−合金めっきまたは他の金属めっきに変更す
る。(5) スズめっきに数%以上鉛を含む半田めっきに変
更する。等が知られている。
As another problem, it is well known that whiskers (whisker-like crystals) are generated when the tin plating film is left immediately after tin plating, and the generation of whiskers is a cause of short-circuit especially in a fine pitch pattern. Because
Various studies have been made. As means for suppressing tin whiskers, (1) nickel, copper,
Form a lead, solder, tin-nickel alloy, tin-copper alloy layer. (2) Perform reflow treatment after plating. (3) Anneal by heating after plating. (4) Change the tin plating to another tin-alloy plating or another metal plating. (5) Change to tin plating that contains several percent or more lead. Etc. are known.

【0009】しかしながら、上記(1) の下地めっきを施
す手法は、下地めっき工程が付与されるのでコストが高
くなる。上記(2) のめっき後にリフロー処理を施す方法
は、最初に厚く均一なめっきを施したとしても、リフロ
ー後はめっき厚にバラツキが生じてしまい、さらにスズ
めっき表面が酸化するという問題が生じる。上記(3)の
めっき後にアニール処理を施す方法は、短期間ではホイ
スカ抑制効果があるが、6ケ月程度の長期間になると完
全にホイスカの成長を防止することができないため、完
全なホイスカ対策とはならないという問題がある。上記
(4) 、(5) の手法は金めっき、半田めっきを行うことが
あるが、金めっきはコスト高、半田めっきはめっき皮膜
組成、膜厚のコントロールが難しい等の問題がある。
However, the method of (1) for applying the undercoating increases the cost because the undercoating step is provided. In the method (2) of performing reflow treatment after plating, even if thick and uniform plating is performed first, the plating thickness varies after reflow, and furthermore, there arises a problem that the tin plating surface is oxidized. The method of performing the annealing treatment after the plating of the above (3) has an effect of suppressing whiskers in a short period of time, but cannot completely prevent whisker growth in a long period of about 6 months. There is a problem that should not be. the above
In the methods (4) and (5), gold plating and solder plating are sometimes performed. However, gold plating has a high cost, and solder plating has problems such as difficulty in controlling the plating film composition and film thickness.

【0010】そこで、本発明の目的は、上記課題を解決
し、ソルダーレジスト下方のリード配線の銅の過剰溶
解、つまりソルダーレジスト際の銅の喰われを防止する
と共に、下地めっきや合金めっきを施さずに、安価に、
且つスズめっきの特性を損なわずに、スズめっきのホイ
スカを抑制することのできる、高い信頼性を有するスズ
めっき構造の半導体装置用テープキャリアおよびその製
造方法を提供することにある。
Accordingly, an object of the present invention is to solve the above-mentioned problems, to prevent excessive dissolution of copper in a lead wiring below a solder resist, that is, to prevent copper from being eroded at the time of a solder resist, and to perform base plating or alloy plating. Without any cost,
It is another object of the present invention to provide a highly reliable tin-plated semiconductor device tape carrier having a tin-plated structure and capable of suppressing tin-plated whiskers without impairing the tin-plated characteristics, and a method of manufacturing the same.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、次のように構成したものである。
Means for Solving the Problems In order to achieve the above object, the present invention is configured as follows.

【0012】(1)請求項1の発明に係る半導体装置用
テープキャリアは、絶縁フィルム上に接着剤層を介して
施された銅箔の配線パターン上に、その端子部分を除く
所定の位置にソルダーレジストを塗布し、前記端子部分
に、厚さ0.01〜0.2μmの薄いスズめっき層を形
成し加熱処理することにより、純スズ層と厚さ0.20
μm以下のスズ−銅合金層を形成し、更にその上に厚さ
0.15〜0.80μmの純スズめっき層を形成したこ
とを特徴とする。
(1) The tape carrier for a semiconductor device according to the first aspect of the present invention is provided on a copper foil wiring pattern formed on an insulating film via an adhesive layer, at a predetermined position excluding a terminal portion thereof. A solder resist is applied, and a thin tin plating layer having a thickness of 0.01 to 0.2 μm is formed on the terminal portion, and a heat treatment is performed.
A tin-copper alloy layer having a thickness of 0.1 μm or less is formed, and a pure tin plating layer having a thickness of 0.15 to 0.80 μm is further formed thereon.

【0013】(2)請求項2の発明は、請求項1記載の
半導体装置用テープキャリアにおいて、前記純スズめっ
き層を加熱処理することにより、厚さ0.15〜0.8
0μmの純スズ層と厚さ0.20μm以上のスズ−銅合
金層を形成したことを特徴とする。
(2) The tape carrier for a semiconductor device according to the first aspect of the present invention, wherein the pure tin plating layer is heat-treated to have a thickness of 0.15 to 0.8.
It is characterized in that a pure tin layer having a thickness of 0 μm and a tin-copper alloy layer having a thickness of 0.20 μm or more are formed.

【0014】(3)請求項3の発明に係る半導体装置用
テープキャリアの製造方法は、絶縁フィルム上に接着剤
層を介して施された銅箔の配線パターン上に、その端子
部分を除く所定の位置にソルダーレジストを塗布した
後、前記端子部分に、1回目のスズめっき処理として、
厚さ0.01〜0.2μmの薄いスズめっき層を施し、
加熱処理することにより、純スズ層と厚さ0.20μm
以下のスズ−銅合金層を形成し、次いで、前記端子部分
に、2回目のスズめっき処理として、純スズめっき層を
0.15〜0.80μmの厚さで形成し、加熱処理する
ことにより、厚さ0.15〜0.80μmの純スズ層と
厚さ0.20μm以上のスズ−銅合金層を形成すること
を特徴とする。
(3) The method for manufacturing a tape carrier for a semiconductor device according to the third aspect of the present invention is a method for manufacturing a tape carrier for a semiconductor device, the method comprising the steps of: After applying a solder resist to the position of the above, as a first tin plating process on the terminal portion,
Apply a thin tin plating layer with a thickness of 0.01 to 0.2 μm,
By heating, pure tin layer and thickness 0.20μm
The following tin-copper alloy layer is formed, and then, as a second tin plating process, a pure tin plating layer having a thickness of 0.15 to 0.80 μm is formed on the terminal portion, followed by heat treatment. A pure tin layer having a thickness of 0.15 to 0.80 μm and a tin-copper alloy layer having a thickness of 0.20 μm or more.

【0015】(4)請求項4の発明は、請求項3記載の
製造方法において、前記2回目のスズめっき処理とし
て、純スズめっき層を0.3〜0.6μmの厚さで形成
し、加熱処理することにより、厚さ0.25〜0.30
μmの純スズ層と厚さ0.20〜0.25μmのスズ−
銅合金層を形成することを特徴とする。
(4) The invention according to claim 4 is the manufacturing method according to claim 3, wherein a pure tin plating layer having a thickness of 0.3 to 0.6 μm is formed as the second tin plating treatment. By heat treatment, a thickness of 0.25 to 0.30
μm pure tin layer and 0.20 to 0.25 μm thick tin
It is characterized by forming a copper alloy layer.

【0016】(5)請求項5の発明は、請求項3又は4
記載の製造方法において、前記1回目のスズめっき処理
及び2回目のスズめっき処理を無電解めっきにより行う
ことを特徴とする。
(5) The invention of claim 5 is the invention of claim 3 or 4
In the manufacturing method described above, the first tin plating process and the second tin plating process are performed by electroless plating.

【0017】[0017]

【発明の実施の形態】以下、本発明を図示の実施形態に
基づいて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the illustrated embodiment.

【0018】図1に本発明による半導体装置用テープキ
ャリアの例としてのTABテープキャリアの製造方法を
示す。まず、ポリイミド樹脂製絶縁フィルム1上に接着
剤層2を介して銅箔を形成したテープキャリアに、所定
のフォトレジストを塗布して乾燥させた後に、所定の配
線リードパターンを有するフォトマスクを通して露光、
現像させた後、エッチングを行うことにより、図1
(a)に示すように所定の微細配線パターン3を作製す
る。
FIG. 1 shows a method of manufacturing a TAB tape carrier as an example of a tape carrier for a semiconductor device according to the present invention. First, a predetermined photoresist is applied to a tape carrier on which a copper foil is formed on a polyimide resin insulating film 1 via an adhesive layer 2 and dried, and then exposed through a photomask having a predetermined wiring lead pattern. ,
After the development, etching is performed to obtain FIG.
A predetermined fine wiring pattern 3 is formed as shown in FIG.

【0019】次いで、図1(b)に示すように、このポ
リイミドポリイミド樹脂製絶縁フィルム1上に銅の微細
配線パターン3が形成されたテープキャリアの銅パター
ン上の一部分に、つまり銅パターン上の銅リード3a等
の端子部分を除いた所定の位置に、ソルダーレジスト6
を印刷法により塗布する。
Next, as shown in FIG. 1 (b), a part of the copper pattern of the tape carrier in which the copper fine wiring pattern 3 is formed on the polyimide-polyimide insulating film 1, that is, on the copper pattern, Solder resist 6 is placed at a predetermined position excluding terminal portions such as copper leads 3a.
Is applied by a printing method.

【0020】次に、図1(c)に示すように、上記銅リ
ード3a等の端子部分に、1回目のスズめっき処理とし
て、厚さ0.01〜0.2μmの薄いスズめっき層を形
成し、その後130℃で10分間の加熱処理をすること
により当該スズめっき層に銅を拡散して、実質的に銅を
含有しないスズめっき層すなわち純スズ層4aと、厚さ
0.20μm以下の銅拡散スズめっき層すなわちスズ−
銅合金層5aを形成する。
Next, as shown in FIG. 1C, a thin tin plating layer having a thickness of 0.01 to 0.2 μm is formed on the terminal portion such as the copper lead 3a as a first tin plating process. Then, by performing a heat treatment at 130 ° C. for 10 minutes, copper is diffused into the tin plating layer, and a tin plating layer containing substantially no copper, that is, a pure tin layer 4a and a thickness of 0.20 μm or less are formed. Copper diffusion tin plating layer, ie tin-
The copper alloy layer 5a is formed.

【0021】この後、図1(d)に示すように、このテ
ープキャリアの上記端子部分(銅リード3a等)に、つ
まり1回目のスズめっき層上に、2回目のスズめっき処
理として、純スズめっき層を0.15〜0.80μmの
厚さで形成し、100〜150℃、5分〜90分の加熱
処理をすることにより当該スズめっき層に銅を拡散し
て、厚さ0.15〜0.80μmの実質的に銅を含有し
ないスズめっき層すなわち純スズ層4bと、厚さ0.2
0μm以上の銅拡散スズめっき層すなわちスズ−銅合金
層5bを形成する。
Thereafter, as shown in FIG. 1 (d), a pure tin is formed on the terminal portion (copper lead 3a, etc.) of the tape carrier, that is, on the first tin plating layer as a second tin plating process. A tin plating layer is formed with a thickness of 0.15 to 0.80 μm, and heat treatment is performed at 100 to 150 ° C. for 5 to 90 minutes to diffuse copper into the tin plating layer, and a thickness of 0. A substantially copper-free tin plating layer having a thickness of 15 to 0.80 μm, that is, a pure tin layer 4b;
A copper diffusion tin plating layer of 0 μm or more, that is, a tin-copper alloy layer 5b is formed.

【0022】図1(e)に、最終的に銅リード3a表面
が純スズめっき層4とスズ−銅合金層5の層構造になっ
た状態を示す。
FIG. 1E shows a state in which the surface of the copper lead 3a finally has a layer structure of the pure tin plating layer 4 and the tin-copper alloy layer 5.

【0023】このようにして形成されるTABテープキ
ャリアは、1回目のスズめっき処理の際には薄くスズめ
っきされるので、ソルダーレジスト6が存在していて
も、局部的に銅の過剰溶解部9が形成される度合いが実
際上無視しうる程度に小さい。そして2回目のスズめっ
き処理の際には、ソルダーレジスト6の下面にめっき液
が侵入したとしても、銅の表面はスズ−銅合金層5aが
形成され、銅箔がめっき液と接触することはないので、
局部的な電食が起こらず、従って、図4に示した銅の過
剰溶解部9が銅リード3aに形成されることがない。よ
って、銅リード3aに銅の過剰溶解部9が存在して銅リ
ード3aの強度が弱わまるという不都合を無くすことが
できる。
The TAB tape carrier formed in this manner is thinly tin-plated during the first tin plating process. Therefore, even if the solder resist 6 is present, the excessively dissolved copper locally exists. The degree to which 9 is formed is practically negligible. Then, at the time of the second tin plating, even if the plating solution enters the lower surface of the solder resist 6, the tin-copper alloy layer 5a is formed on the copper surface, and the copper foil may not come into contact with the plating solution. Since there is no,
Local electrolytic corrosion does not occur, and therefore, the excessive copper dissolution portion 9 shown in FIG. 4 is not formed on the copper lead 3a. Therefore, it is possible to eliminate the inconvenience that the copper lead 3a has the excessively melted copper 9 and the strength of the copper lead 3a is weakened.

【0024】上記のTABテープキャリアの製造方法に
おいて、1回目のスズめっき処理後の加熱処理は実施せ
ず、純スズ層4aを形成させただけでも良い。
In the above-described TAB tape carrier manufacturing method, the heat treatment after the first tin plating may not be performed, and only the pure tin layer 4a may be formed.

【0025】1回目の薄いスズめっき層の厚さは0.0
1〜0.2μmが好ましい。この1回目の薄いスズめっ
き層の厚さが0.2μmを越えると、ホイスカ抑制効果
が低くなり、また図4で説明した銅の過剰溶解(過剰溶
解部9)が発生する可能性が高くなるからである。
The thickness of the first thin tin plating layer is 0.0
1 to 0.2 μm is preferred. When the thickness of the first thin tin plating layer exceeds 0.2 μm, the effect of suppressing whiskers is reduced, and the possibility of excessive dissolution of copper (excess dissolution portion 9) described with reference to FIG. 4 is increased. Because.

【0026】一方、2回目のスズめっき処理による純ス
ズ層4の厚さを0.15〜0.80μmとした理由は、
0.15μm未満の場合はインナリードのボンディング
性が困難となり、0.8μmを越えるとめっきだれを生
じ、短絡の原因となるからである。また、2回目のスズ
めっき処理によるスズ−銅合金層5の厚さを0.20μ
m以上とした理由は、0.20μm未満の場合はホイス
カ抑制効果が不十分となるからである。
On the other hand, the reason for setting the thickness of the pure tin layer 4 in the second tin plating process to 0.15 to 0.80 μm is as follows.
If the thickness is less than 0.15 μm, the bonding property of the inner lead becomes difficult, and if the thickness exceeds 0.8 μm, the plating will be dripped and cause a short circuit. Further, the thickness of the tin-copper alloy layer 5 by the second tin plating treatment is set to 0.20 μm.
The reason for setting m or more is that if it is less than 0.20 μm, the whisker suppression effect becomes insufficient.

【0027】上記TABテープキャリアの半導体素子へ
の実装作業は、例えば図3に示すように半導体素子(I
Cチップ)7をデバイスホールに位置するように配置
し、デバイスホールに突出したインナーリードと半導体
素子7の電極を位置合わせした後、ボンディングツール
により圧着する。半導体素子7の電極には金バンプ8が
形成されており、加熱された状態で銅リード3aに圧着
されると、スズめっきが溶融し金−スズ合金が形成し、
電極とインナーリードが強固に接合される。
The mounting operation of the TAB tape carrier on a semiconductor device is performed, for example, as shown in FIG.
The C chip 7 is arranged so as to be located in the device hole, and the inner lead projecting into the device hole and the electrode of the semiconductor element 7 are aligned, and then pressure-bonded by a bonding tool. Gold bumps 8 are formed on the electrodes of the semiconductor element 7, and when pressed against the copper leads 3a in a heated state, the tin plating melts to form a gold-tin alloy,
The electrode and the inner lead are firmly joined.

【0028】[0028]

【実施例】ポリイミド樹脂製絶縁フィルム1上に接着剤
層2を介して形成された銅箔25μmのテープキャリア
に、所定のレジストを塗布して乾燥させた後に、所定の
配線リードパターンを有するフォトマスクを通して露
光、現像させた後、エッチングを行うことによりリード
パターンを作製した。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A predetermined resist is applied to a tape carrier of 25 μm copper foil formed on a polyimide resin insulating film 1 via an adhesive layer 2 and dried, and then a photo having a predetermined wiring lead pattern is formed. After exposure and development through a mask, etching was performed to produce a lead pattern.

【0029】そして、まず、ポリイミド樹脂製絶縁フィ
ルム1上に銅の微細パターン3が形成された半導体装置
用テープキャリアの銅配線パターン上の一部分にソルダ
ーレジスト6を印刷後、1回目のスズめっき処理とし
て、0.01〜0.2μmのスズめっき層を形成し、1
00℃〜150℃で5分〜90分加熱処理により、純ス
ズ層4aとスズ−銅合金層5aを形成した。
First, a solder resist 6 is printed on a part of a copper wiring pattern of a tape carrier for a semiconductor device in which a fine copper pattern 3 is formed on a polyimide resin insulating film 1, and then a first tin plating process is performed. To form a tin plating layer of 0.01 to 0.2 μm,
The heat treatment was performed at 00 ° C to 150 ° C for 5 minutes to 90 minutes to form a pure tin layer 4a and a tin-copper alloy layer 5a.

【0030】次に、2回目のスズめっき処理として、純
スズめっき層を0.3〜0.6μm形成し、100〜1
50℃、5分〜90分の加熱処理により、純スズ層4b
を0.2〜0.3μm、スズ−銅合金層5bを0.15
〜0.25μm形成させたものを作製した。
Next, as a second tin plating treatment, a pure tin plating layer is formed in a thickness of 0.3 to 0.6 μm,
Pure tin layer 4b by heat treatment at 50 ° C. for 5 to 90 minutes
Is 0.2 to 0.3 μm, and the tin-copper alloy layer 5b is 0.15
One having a thickness of 0.25 μm was prepared.

【0031】ここでスズめっきは電解及び無電解めっき
のいずれかの方法で形成しても良いが、めっき厚のバラ
ツキの少ない点で無電解めっきとした。
Here, the tin plating may be formed by either electrolytic or electroless plating, but the electroless plating is used because the plating thickness has less variation.

【0032】無電解スズめっき液は石原薬品製580M
を用い、70℃、5〜500sで処理した。1回目のス
ズめっき後、100〜150℃、5〜90分加熱処理
し、2回目のスズめっき後の加熱処理を100〜150
℃、5〜90分加熱した。このように作製したサンプル
について、銅の過剰溶解性の評価を断面観察にて行っ
た。この結果を、表1にスズめっき条件と銅過剰溶解性
評価結果として示す。
The electroless tin plating solution is 580M manufactured by Ishihara Chemical Co., Ltd.
And treated at 70 ° C. for 5 to 500 s. After the first tin plating, heat treatment is performed at 100 to 150 ° C. for 5 to 90 minutes, and the heat treatment after the second tin plating is performed at 100 to 150 ° C.
Heated for 5 to 90 minutes. With respect to the sample thus manufactured, the excess solubility of copper was evaluated by cross-sectional observation. The results are shown in Table 1 as tin plating conditions and copper excess solubility evaluation results.

【0033】[0033]

【表1】 [Table 1]

【0034】表1から判るように、1回目のスズめっき
厚が0.01〜0.2μmの範囲では、銅の過剰溶解は
観察されなかった。一方、サンプル1のようにソルダー
レジスト印刷後に2回目のスズめっき処理に相当する無
電解スズめっきをしただけの場合(1回目のスズめっき
処理なしの場合)、およびサンプル6のように1回目の
スズめっき厚が0.2μm以上の場合には、銅の過剰溶
解が観察された。
As can be seen from Table 1, when the first tin plating thickness was in the range of 0.01 to 0.2 μm, no excessive dissolution of copper was observed. On the other hand, the case where only the electroless tin plating corresponding to the second tin plating treatment was performed after the solder resist printing like the sample 1 (the case without the first tin plating treatment), and the case where the first When the tin plating thickness was 0.2 μm or more, excessive dissolution of copper was observed.

【0035】次に、コクール計により純スズめっき厚、
蛍光X線膜厚計により全スズ厚を測定し、(全スズ厚)
から(純スズ厚)を差し引きしてスズ−銅合金層の層厚
を求め、1〜6月(30日、60日、90日、180
日)放置した後のインナリード150本について、それ
ぞれ200倍の光学顕微鏡によりホイスカの観察を行
い、そのホイスカの発生数を数えた。このスズめっき条
件とスズめっき厚、ホイスカ性評価結果を表2に示す。
表2から判るように、スズ−銅合金層が0.20μm未
満(サンプル2、5、8、11、14)の場合、経過日
数が増加するにつれてホイスカ発生数が増加することが
観察された。これによりスズ−銅の拡散層が厚いほどス
ズのホイスカを抑制する効果があることが判る。
Next, the thickness of pure tin plating is
Measure the total tin thickness with a fluorescent X-ray film thickness meter, (total tin thickness)
(Pure tin thickness) is subtracted from the above to determine the thickness of the tin-copper alloy layer, and from January to June (30 days, 60 days, 90 days, 180 days)
Day) The whiskers were observed for each of the 150 inner leads after standing by using an optical microscope of 200 times, and the number of whiskers generated was counted. Table 2 shows the tin plating conditions, tin plating thickness and whisker evaluation results.
As can be seen from Table 2, when the tin-copper alloy layer was less than 0.20 μm (samples 2, 5, 8, 11, and 14), it was observed that the number of whiskers generated increased as the number of elapsed days increased. This shows that the thicker the tin-copper diffusion layer is, the more effective it is to suppress tin whiskers.

【0036】[0036]

【表2】 [Table 2]

【0037】上記実施例では銅箔25μmのテープキャ
リアを用いたが、これに代えて銅箔10μmのテープキ
ャリアで上記と同様な評価を行ったところ、1回目のス
ズめき厚さが0.2μm以下では銅の過剰溶解現象は発
生しなかったが、0.2μmを越えたケースでは過剰溶
解が促進していることが観察された。
In the above embodiment, a tape carrier having a copper foil of 25 μm was used. However, a tape carrier having a copper foil of 10 μm was used for the same evaluation as above. In the following, the phenomenon of excessive dissolution of copper did not occur, but it was observed that excessive dissolution was promoted in cases exceeding 0.2 μm.

【0038】[0038]

【発明の効果】以上説明したように本発明によれば、次
のような優れた効果が得られる。
As described above, according to the present invention, the following excellent effects can be obtained.

【0039】本発明の半導体装置用テープキャリア及び
その製造方法によれば、ポリイミド樹脂等の絶縁フィル
ム上に接着剤層を介して施された銅箔の導体微細パター
ン上の一部分にソルダーレジストを印刷塗布した後、1
回目のスズめっき処理として、厚さ0.01〜0.20
μmの薄いスズめっき層を形成し、加熱処理により純ス
ズ層とスズ−銅合金層を形成する。この1回目のスズめ
っき処理の際には、厚さ0.01〜0.20μmという
薄いスズめっきが施されるので、ソルダーレジストが存
在していても、銅の過剰溶解部の形成される度合いは実
際上無視しうる程度に小さい。
According to the tape carrier for a semiconductor device of the present invention and the method of manufacturing the same, a solder resist is printed on a part of a conductor fine pattern of a copper foil applied on an insulating film such as a polyimide resin via an adhesive layer. After applying, 1
As the second tin plating treatment, a thickness of 0.01 to 0.20
A thin tin plating layer having a thickness of μm is formed, and a pure tin layer and a tin-copper alloy layer are formed by heat treatment. At the time of this first tin plating treatment, a thin tin plating having a thickness of 0.01 to 0.20 μm is applied. Is practically negligible.

【0040】その後、2回目のスズめっき処理として、
純スズめっき層を0.15〜0.80μm以上形成し、
加熱処理によりスズ−銅合金層を0.20μm以上、純
スズ層を0.15〜0.80μmとする。この2回目の
スズめっき処理の際には、既に銅の表面にスズ−銅合金
層が形成されているので、ソルダーレジストの下面にめ
っき液が侵入したとしても、銅箔がめっき液と接触する
ことにはならないので、局部的な電食が起こらない。こ
れにより、ソルダーレジスト下方のリード部の銅の過剰
溶解を抑制することが可能である。またスズめっき以外
の金属めっきを行わなくても、比較的安価でスズのホイ
スカを抑制することができ、高い信頼性を有したスズめ
っき皮膜が得られる。
Then, as a second tin plating treatment,
Forming a pure tin plating layer of 0.15 to 0.80 μm or more,
The heat treatment makes the tin-copper alloy layer 0.20 μm or more and the pure tin layer 0.15 to 0.80 μm. At the time of the second tin plating treatment, since the tin-copper alloy layer has already been formed on the surface of copper, even if the plating solution enters the lower surface of the solder resist, the copper foil contacts the plating solution. This does not mean that there is no local electrolytic corrosion. This makes it possible to suppress excessive dissolution of copper in the lead portion below the solder resist. Further, even if metal plating other than tin plating is not performed, tin whiskers can be suppressed at relatively low cost, and a highly reliable tin plating film can be obtained.

【0041】更に、2回目のスズめっき処理において
は、純スズ層を0.15〜0.80μmとしているの
で、インナリードのボンディング性が良好であり、且つ
めっきだれを生じない。また2回目のスズ−銅合金層を
0.20μm以上としているので、十分なホイスカ抑制
効果を得ることができる。
Further, in the second tin plating treatment, the pure tin layer has a thickness of 0.15 to 0.80 μm, so that the bonding property of the inner lead is good and no plating dripping occurs. Further, since the second tin-copper alloy layer has a thickness of 0.20 μm or more, a sufficient whisker suppression effect can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のテープキャリアの構造を工程毎に示し
た断面図である。
FIG. 1 is a sectional view showing the structure of a tape carrier of the present invention for each process.

【図2】従来のテープキャリアの構造を工程毎に示した
断面図である。
FIG. 2 is a sectional view showing the structure of a conventional tape carrier for each process.

【図3】本発明のテープキャリアにICチップを搭載し
て半導体装置を構成した組立図である。
FIG. 3 is an assembly diagram in which a semiconductor device is configured by mounting an IC chip on the tape carrier of the present invention.

【図4】銅の過剰溶解現象を示した断面図である。FIG. 4 is a cross-sectional view showing the phenomenon of excessive dissolution of copper.

【符号の説明】[Explanation of symbols]

1 ポリイミド樹脂製絶縁フィルム 2 接着剤層 3 配線パターン 3a 銅リード 4 純スズめっき層 4a、4b 純スズ層 5 スズー銅合金層 5a、5b スズー銅合金層 6 ソルダーレジスト 9 銅の過剰溶解部 Reference Signs List 1 insulating film made of polyimide resin 2 adhesive layer 3 wiring pattern 3a copper lead 4 pure tin plating layer 4a, 4b pure tin layer 5 tin-copper alloy layer 5a, 5b tin-copper alloy layer 6 solder resist 9 excessive melting part of copper

フロントページの続き (72)発明者 菅野 優 茨城県日立市助川町3丁目1番1号 日立 電線株式会社電線工場内 Fターム(参考) 4K022 AA02 AA42 BA21 BA35 CA08 CA09 DA01 EA01 4K028 CA01 CB02 CB03 CC04 CD01 5E343 AA02 AA18 AA33 BB09 BB12 BB14 BB17 BB24 BB34 BB52 DD32 ER11 ER12 GG01 GG03 GG06 GG18 5F044 MM03 MM23 MM25 MM26 Continued on the front page (72) Inventor Yu Sugano 3-1-1, Sukekawa-cho, Hitachi-shi, Ibaraki F-term in the cable plant of Hitachi Cable, Ltd. (Reference) 4K022 AA02 AA42 BA21 BA35 CA08 CA09 DA01 EA01 4K028 CA01 CB02 CB03 CC04 CD01 5E343 AA02 AA18 AA33 BB09 BB12 BB14 BB17 BB24 BB34 BB52 DD32 ER11 ER12 GG01 GG03 GG06 GG18 5F044 MM03 MM23 MM25 MM26

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】絶縁フィルム上に接着剤層を介して施され
た銅箔の配線パターン上に、その端子部分を除く所定の
位置にソルダーレジストを塗布し、 前記端子部分に、厚さ0.01〜0.2μmの薄いスズ
めっき層を形成し加熱処理することにより、純スズ層と
厚さ0.20μm以下のスズ−銅合金層を形成し、 更にその上に厚さ0.15〜0.80μmの純スズめっ
き層を形成したことを特徴とする半導体装置用テープキ
ャリア。
1. A solder resist is applied to a predetermined position excluding a terminal portion on a copper foil wiring pattern provided on an insulating film via an adhesive layer, and a thickness of 0.1 mm is applied to the terminal portion. By forming a thin tin plating layer having a thickness of 0.1 to 0.2 μm and performing a heat treatment, a pure tin layer and a tin-copper alloy layer having a thickness of 0.20 μm or less are formed. A tape carrier for a semiconductor device, comprising a pure tin plating layer having a thickness of 80 μm.
【請求項2】請求項1記載の半導体装置用テープキャリ
アにおいて、前記純スズめっき層を加熱処理することに
より、厚さ0.15〜0.80μmの純スズ層と厚さ
0.20μm以上のスズ−銅合金層を形成したことを特
徴とする請求項1記載の半導体装置用テープキャリア。
2. The tape carrier for a semiconductor device according to claim 1, wherein the pure tin plating layer is heat-treated to form a pure tin layer having a thickness of 0.15 to 0.80 μm and a thickness of 0.20 μm or more. The tape carrier for a semiconductor device according to claim 1, wherein a tin-copper alloy layer is formed.
【請求項3】絶縁フィルム上に接着剤層を介して施され
た銅箔の配線パターン上に、その端子部分を除く所定の
位置にソルダーレジストを塗布した後、 前記端子部分に、1回目のスズめっき処理として、厚さ
0.01〜0.2μmの薄いスズめっき層を施し、加熱
処理することにより、純スズ層と厚さ0.20μm以下
のスズ−銅合金層を形成し、 次いで、前記端子部分に、2回目のスズめっき処理とし
て、純スズめっき層を0.15〜0.80μmの厚さで
形成し、加熱処理することにより、厚さ0.15〜0.
80μmの純スズ層と厚さ0.20μm以上のスズ−銅
合金層を形成することを特徴とする半導体装置用テープ
キャリアの製造方法。
3. A solder resist is applied to a predetermined position excluding a terminal portion on a copper foil wiring pattern provided on an insulating film via an adhesive layer, and then a first time is applied to the terminal portion. As a tin plating process, a thin tin plating layer having a thickness of 0.01 to 0.2 μm is applied, and a heat treatment is performed to form a pure tin layer and a tin-copper alloy layer having a thickness of 0.20 μm or less, As a second tin plating process, a pure tin plating layer having a thickness of 0.15 to 0.80 μm is formed on the terminal portion, and a heat treatment is performed to form a pure tin plating layer having a thickness of 0.15 to 0.5 μm.
A method for producing a tape carrier for a semiconductor device, comprising forming a pure tin layer having a thickness of 80 μm and a tin-copper alloy layer having a thickness of 0.20 μm or more.
【請求項4】請求項3記載の製造方法において、前記2
回目のスズめっき処理として、純スズめっき層を0.3
〜0.6μmの厚さで形成し、加熱処理することによ
り、厚さ0.25〜0.30μmの純スズ層と厚さ0.
20〜0.25μmのスズ−銅合金層を形成することを
特徴とする半導体装置用テープキャリアの製造方法。
4. The method according to claim 3, wherein
As the second tin plating treatment, the pure tin plating layer
A pure tin layer having a thickness of 0.25 to 0.30 μm and a thickness of 0.1 to 0.6 μm are formed and heat-treated.
A method for manufacturing a tape carrier for a semiconductor device, comprising forming a tin-copper alloy layer having a thickness of 20 to 0.25 μm.
【請求項5】請求項3又は4記載の製造方法において、
前記1回目のスズめっき処理及び2回目のスズめっき処
理を無電解めっきにより行うことを特徴とする半導体装
置用テープキャリアの製造方法。
5. The method according to claim 3, wherein
A method for manufacturing a tape carrier for a semiconductor device, wherein the first tin plating and the second tin plating are performed by electroless plating.
JP2001086912A 2001-03-26 2001-03-26 Semiconductor device tape carrier and its manufacturing method Withdrawn JP2002289652A (en)

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