JPH03230391A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain rapid writing/reading of image data by means of a control circuit with simple constitution by including an address control part for image processing in the semiconductor storage device. CONSTITUTION:An initial address setting instruction outputted from a CPU is set up in an instruction/data control circuit 26 through an address bus 27 and an address I/O circuit 25 at first. Then, initial addresses are respectively set up in row/column address generating counters 23, 24. When an access mode is set up in the circuit 26 from the CPU, the circuit 26 controls the counters 23, 24 so that the counters 23, 24 count up external control clocks outputted from the CPU at the counting interval and in the counting direction corresponding to the specified access mode. Consequently, the rapid writing/reading of image data can be attained only by applying a control instruction for specifying the access mode from the outside.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device capable of high-speed processing.

[Prior Art] In recent years, the need for high-speed processing in semiconductor storage devices that store digitized image data has increased significantly.

However, semiconductor storage devices commonly used for storing image data are general-purpose DRAM (dynamic random access memory) or video RAM (dual baud RAM), and for high-speed image processing, DRAM control requires a large-scale control circuit.

FIG. 5 schematically shows an image data storage device and its control circuit in a conventional image processing system.

The digitized image data is applied to and stored in an image data storage device 10 such as a general-purpose DRAM or video RAM. Writing/reading of data necessary for image processing is controlled by a control circuit 11. That is, by applying an address designation signal via the bar mower 2 and a control signal via the bar mower 3 from the control circuit 1.1, write data and read data are transferred to the external data bus 14.
The image data is input to and output from the image data storage device 10 via the image data storage device 10.

[Problems to be Solved by the Invention] However, according to the conventional image processing system, since the control circuit II of the image data storage device is composed of a large number of semiconductor element parts, signal delays in parts other than the storage device are ignored. This has become an impediment to speeding up the entire image processing system.

Furthermore, it is difficult to reduce the size of the system by increasing the mounting density of components.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that can read and write data at high speed with a control circuit having a simple configuration.

[Means for Solving the Problems] The features of the present invention that achieve the above-mentioned object include a memory array having a plurality of memory cells arranged in a matrix, and a memory cell for accessing one of the plurality of memory cells. row and column selection means; address generation counter means capable of counting up or down at desired intervals;
It includes means for setting an initial address given from the outside into the address generation counter means, and control means for controlling the count interval and counting direction of the address generation counter means in an access mode according to an instruction given from the outside. That's true.

The address generation counter means outputs a carry signal and the address to the outside when the generated address exceeds a predetermined range, and when the carry signal is applied from the outside, the address is initialized to the address given from the outside. may be configured.

[Operation] When an addressing mode is externally applied and a control clock signal is applied, the counter means counts at the count interval and in the counting direction of the applied access mode. This generates an address to access one of the plurality of memory cells, and image data is written or read in the desired order.

When expanding the capacity of the storage device, if the address generated by the address generation counter means exceeds a predetermined range, a carry signal and the address are output to the outside, and
When a carry signal is applied from the outside, it is configured to initialize to the address given from the outside, so each storage device is connected to the address bus and the carry signal input/output section of each storage device is connected to each other. It can be easily expanded by simply

[Example] Embodiments of the present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram schematically showing the configuration of an embodiment of a semiconductor memory device of the present invention.

In the figure, 20 is a memory array in which memory cells are arranged in a matrix, and a row decoder 21 and a column decoder 22 are connected to this memory array 20. Row decoder 21 and column decoder 22 correspond to row and column selection means of the present invention.

A row address generation counter 23 is connected to the row decoder 21, and a column address generation counter 24 is connected to the column decoder 22. These row address generation counter 23 and column address generation counter 24 correspond to the address generation counter means of the present invention, and are constituted by general up/down counters. A row carry signal Cx is input to and output from the row address generation counter 23 via a line 23a, and a column carry signal cy is input to and output from the column address generation counter 24 via a line 24a.

Note that the input and output of the carry signal may be configured using different lines.

An address input/output circuit 25 and an instruction and data control circuit 26 are connected to the row address generation counter 23 and the column address generation counter 24. The address input/output circuit 25 is connected to an external address bus 27 and reads and reads addresses. The command and data control circuit 26 is connected to an external control signal bus 28 and an external data bus 29, and is capable of reading control commands,
Control of the internal circuits of the storage device, such as decoding of control commands and transfer of data, and transfer of data to and from the outside are performed.

The address input/output circuit 25 corresponds to means for setting the initial address of the present invention. Further, the command and data control circuit 26 corresponds to the control means of the present invention.

As shown in FIG. 1, the above-mentioned memory array 20, row decoder 21, column decoder 22, row address generation counter 23, column address generation counter 24, address input/output circuit 25, and instruction and data control circuit 26 are main components. This constitutes a semiconductor memory device 30 of the embodiment.

Next, the operation of this embodiment will be explained.

FIG. 2 is a flowchart schematically showing a part of a program for controlling the operation of the semiconductor memory device shown in FIG.

First, in step Sl, an external CPU (not shown)
An initial address setting command is set in the command and data control circuit 26 from the CPU (central processing unit).

Next, in step S2, initial addresses are set in the row address generation counter 23 and column address generation counter 24, respectively. This set allows the address to be sent from the CPU.
<This is done via the address input/output circuit 27 and the address input/output circuit 25.

In the next step S3, the access code is set in the command and data control circuit 26 by the CPU.

This setting is performed by loading address bus 27 with information for selecting the storage device, and loading data bus 29 with information specifying the access mode to be implemented.

Next, in step S4, the instruction and data control circuit 26 causes the row address generation counter 23 and column address generation counter 24 to count the external control clock from the CPU at a count interval and in a count direction corresponding to the specified access mode. Control.

There are various access modes specific to image processing, and FIG. 3 shows examples of their access sequences on the memory array. Of course, various combinations in addition to these access modes are possible.

In the figure, 0 indicates the initial address, 1.2
．． 3... are addresses accessed in the forward direction, 1, -
2, -3, . . . respectively indicate addresses accessed in the opposite direction.

(A) is sequential step mode (forward/reverse direction)
, (B) is the sequential column direction step mode (forward direction/'reverse direction), and (C) is the sequential column direction step mode (forward direction/'reverse direction).
(backward direction), (D), (E), and (F) show the interlaced matrix direction step mode (forward direction/'backward direction), (G) shows the sequential rotation mode, and (H) shows the interlaced rotation mode, respectively. .

Table 1 shows the control modes of the row address generation counter 23 and column address generation counter 24 for implementing each of these access modes.

In the same table, INC/DEC indicates count up or count down operation. Also, INC/D, E
C(1) means that one count-up or count-down operation is performed for one external control clock, and INC/DEC (2) means that one count-up or count-down operation is performed for two external control clocks. means to do. Further, ROR means to perform a circular operation, and ROR (3/1) means to perform one time and three consecutive times for one external control clock.

For example, to execute the sequential row direction step mode (forward direction) which is mode (A), the row address generation output trancoder 3 is counted up once per external control clock, and the column address generation counter 24 is According to this embodiment, an address control unit specific to image processing is built into the semiconductor memory device, so that the control clock may be kept constant without responding to the control clock.

Therefore, writing and reading of image data can be executed using the control clock simply by externally supplying a control command specifying the access mode.

When the address overflows in the row address generation counter 23, the row carry signal Cx is outputted to the outside via the line 23a, and at the same time, the row address at that time is read out onto the address bus 27 by the address input/output circuit 25. and output to the outside. In addition, if the address overflows in the column address generation counter 24, a column carry signal cy is sent via the line 242.
is outputted to the outside, and at the same time, the column address at that time is read onto the address bus 27 by the address input/output circuit 25 and outputted to the outside.

Conversely, if a row carry signal Cx is externally applied via line 23a, or if a column carry signal Cy is externally applied via line 212, the storage device is enabled and address bus 27 is applied. The above address information is set in the row address generation counter 23 or the column address generation counter 24 via the address input/output circuit 25.

With this configuration, a plurality of semiconductor memory devices can be combined with a simple configuration without a complicated peripheral control circuit.

FIG. 4 shows the semiconductor memory device 3 shown in FIG.
A plurality of semiconductor memory devices M-〇 having the same configuration as 0,
O), 'v1 (0,1), M (1
, 0) and M(1, 1) are connected in a matrix.

Each semiconductor memory device M(0,0), M(0,1), M
The connections between (1,0), M(i,1) and the external address bus 27, external control signal bus 28, and external data pathcoder 9 are exactly the same as in the embodiment shown in FIG. be. The connection between each semiconductor memory device is a row xery signal Cx.
Moon line 4. and 41 and the line 2 for the column carry signal Cy.
and "3" in a matrix, and the continuity of data (continuity of data space) can be guaranteed with an extremely simple system configuration in which a special control circuit is additionally provided.

2. Effects of the Invention: As described in detail above, according to the present invention, there is provided an address generation counter means capable of counting up or counting down at desired intervals, and an initial address given from the outside set in the address generation counter means. and control means for controlling the count interval and count direction of the address generation counter means in an access mode according to an instruction given from the outside, so that it is possible to receive a control command specifying the access mode from the outside. Writing and reading of image data can be executed by simply supplying the control clock. As a result, the control circuit can have a very simple configuration, making it possible to read and write data at high speed.

Further, according to the present invention, the address generation counter means outputs a carry signal and the address to the outside when the generated address exceeds a predetermined range, and when a carry signal is applied from the outside, the address generation counter means outputs the carry signal and the address to the outside. Since the address is configured to be initialized, the capacity of the storage device for image processing can be expanded simply by connecting the carry signal line between the recording/inspection devices. That is, the capacity can be easily expanded with a control circuit having a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the semiconductor memory device of the present invention, FIG. 2 is a flowchart schematically showing a part of a program for controlling operations in the embodiment of FIG. 1, and FIG. FIG. 4 is a block diagram showing a schematic configuration of another embodiment of the present invention, and FIG. 5 is a diagram showing examples of various access sequence modes specific to image processing on a memory array. FIG. 2 is a block diagram showing the configuration. 20...Memory array, 21...Row decoder, 22...Column decoder, 23...
・Row address generation counter, 23a, 24a,
40.41.42.43... line, 24...
...Column address generation counter, 25...Address input/output circuit, 26...Command and data control circuit,', 7...Address bus, 28...
・Control signal bus, 29... Data bus, 30.
...Semiconductor storage device. x Figure (A) (B) (D) (E) Figure 3 (C) (F)

Claims (1)

[Claims] A memory array having a plurality of memory cells arranged in a matrix, row and column selection means for accessing one of the plurality of memory cells, and an address generator capable of counting up or down at desired intervals. means for setting an initial address given from the outside into the address generation counter means; and means for setting the count interval and counting direction of the address generation counter means in an access mode according to an instruction given from the outside. 1. A semiconductor memory device comprising: a control means for controlling the semiconductor memory device.