JPH03230387A - Dynamic ram control device - Google Patents

Abstract

PURPOSE:To improve the reading efficiency of a memory by switching a bust mode(BM) and a normal mode(NM), and in the BM, immediately outputting a signal to be used for a burst reading cycle when a BRDY signal is turned to the 'L' level. CONSTITUTION:A signal generator 19 generates a switching signal for switching the NM and the BM in the memory reading cycle based upon HADS, HW/R, HHLDA, and BLAST signals outputted from a central processing unit(CPU), a DRAMCS signal outputted from a DRAM decoder and a BRDY signal from a CPU cycle state machine. When the BM is selected by the mode switching signal from the generator 19, a multiplexer 20 outputs address signals MA0, MA1 to be used for the burst reading cycle of the DRAM immediately after turning the BRADY signal to the 'L' level. Consequently, time required for the reading cycle of the memory can be shortened and the reading efficiency of the memory can be improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a dynamic RAM that controls access to the dynamic RAM based on instructions from a central processing unit.
Regarding a control device.

[Prior Art] For example, a 100ns dynamic RA self-control device for 8048B-25PC/AT has an address decoder 1, a back
Page bit φ detector 2
, CPU (Central Processing Unit) Cycle State
Machine 3, DMA (Direct Memory Access)
φ cycle-state fight machine 4, refresh cycle state fist machine 5, DRAM control
A signal generator 6, a row/column address multiplexer 7, etc. are provided to
st) ・Figures 8, 9 and 10 in mode
Signal processing was performed at the timing shown in the figure.

Figure 8 shows the bank miss (bank miss) slow cycle and bank hit page miss (bank miss).
Figure 9 shows the write cycle timing of Bank hit page 5iss).
Bank hit page hit
), and Figure 10 shows the timing of the read cycle, write cycle, and back φ miss (Bank wlss) write cycle. It shows.

[Question 8 to be solved by the invention] By the way, address signals from the CPU (HA2 to HA31)
), the BRDY- signal is always o - (Low) and is delayed by about 22 ns from the rising edge of the clock (CLK), so in the conventional memory skew burst read cycle, an extra cycle occurs and the read cycle time becomes longer. There was a problem. In other words, the read cycle for bank miss is 1.
4 clocks are required, and the bank Q hint contest page.
A read cycle for a hit or miss requires 12 clocks, and a read cycle for a bank hit epage◆miss requires 16 clocks.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a dynamic RAM control device that can shorten the time required for a memory burst read cycle and improve memory read efficiency.

[Means for Solving the Problems] The present invention provides a dynamic RAM that controls access to the dynamic RAM based on instructions from a central processing unit.
In the control device, from the central processing unit (7) HAD
S-,)IW/R-, HHLDA, BLAST-
DRAM from each signal and dynamic RAM decoder
C8 - BR from signal and CPU cycle state machine
Burst in memory read cycle by DY signal
Turn off mode and normal mode! A mode switching signal generating means for generating a mode switching signal to be input, and an address signal used for a burst read cycle of the dynamic RAM when the burst mode is selected by the mode switching signal from this signal generating means. - An address output means is provided which outputs the signal immediately when the signal becomes low level.

[Function] In the present invention having such a configuration, the mode switching signal generating means switches between the burst mode and the normal mode, and in the burst mode, the address signal used for the burst read cycle is set to BRDY. - It is possible to output the signal as soon as it goes low, thereby eliminating extra cycles.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is an address decoder, 12 is a bank hit page hit detector, 13 is a CPU cycle state machine, and 14 is a D M
A cycle state machine, 15 is refresh cycle state machine, 16 is DRAM control signal generator, 17 is Row/C
olumn address multiplexer. The configuration of each part described above is the same as the conventional one.

18 is a burst mode address O generator which is a feature of the present invention;
It is composed of a mode address and control signal generator 19 and a burst/φ normal mode/φ address multiplexer 20.

The burst mode address contestant control signal generator 19 receives HADS-, HW/R-, HHLDA from the central processing unit.

Mode switching signal generation that generates a mode switching signal to switch between burst mode and normal mode in a memory read cycle using each BLAST- signal, the DRAMC9- signal from the dynamic RA Fv1 decoder, and the BRDY signal from the CPU cycle state machine. have the means.

The burst Φ and normal mode address
The multiplexer 20 performs burst read/write operations on the dynamic RAM when the norst mode is selected by the mode switching signal from the mode switching signal generating means.
The address signals MAO and MA1 used in the cycle are
It is provided with address output means that outputs an output immediately when the RDY- signal becomes low level.

In this embodiment with such a configuration, the burst mode address and control signal generator 19 receives HADS11W/R-, lI+IIDA from the central processing unit as shown in FIGS. 2 and 3.
, R1, AST, c7) and the DRAMC8- signal from the dynamic RAM decoder and the BRD Y signal from the CPU cycle state machine, the normal mode and burst mode are selected in the memory read cycle.
A mode switching signal is generated to switch the mode.

Note that FIG. 2 shows the case of bank miss, and FIG. 3 shows the case of bank hit page hit.

The first burst and normal mode address multiplexer 20 receives signals from the burst mode address and control signal generator 19 as shown in FIGS. 4, 5 and 6. Address signals MAO and MAl used for a burst read cycle of the dynamic RAM are outputted immediately when the BRDY- signal becomes low level while the burst mode is selected by the mode switching signal.

In addition, Figure 4 shows the lead competition cycle of Bank Miss and the bank fist hit/page turn hit (
Bank hit page hit), Bank hit page miss (Bank hit page hit)
1ss), and the fifth
The diagram shows Bank hit page hits.
t page hit) read cycle, write cycle
Figure 6 shows the timing of write cycles and bank misses.
Bank hit page
The read cycle of ``Miss'' is shown.

4 corresponds to FIG. 8, FIG. 5 corresponds to FIG. 9, and FIG. 6 corresponds to FIG. 10. As shown in FIG. 4, the read cycle for a bank miss ends in 11 clocks, and as shown in FIG. , and as shown in FIG. 6, the hang-hit-page-miss read cycle ends in 13 clocks.

Note that the write cycle is the same as before.

As shown in Figure 2, the read cycle for a bank miss is conventionally 1.
It only takes 11 clocks instead of 4 clocks, and the read cycle for bank hit page hit only needs 9 clocks instead of 12 clocks in the past. - The read cycle for a miss only takes 13 clocks, compared to 16 clocks in the conventional system, making it possible to shorten the time required for a read cycle and improve memory read efficiency.

2. Effects of the Invention: As detailed above, according to the present invention, it is possible to provide a dynamic RAM control device that can shorten the time required for a memory read cycle and improve memory read efficiency. It is.

[Brief explanation of drawings]

1 to 6 show embodiments of the present invention.
The figure is a block diagram, and Figures 2 and 3 are memory read/
Timing diagrams of normal mode and burst mode in write contention cycle; Figures 40, 5 and 6 are timing diagrams showing read/write control in burst mode; Figures 7 to 10 are conventional examples 7 is a block diagram, and FIGS. 8, 9, and 10 are timing diagrams showing read/write control in burst mode. 18... Burst mode address generator, 19... Burst mode address and control signal generator, 20... Burst and normal contention mode address contention multiplexer.

Claims (1)

[Claims] Dynamic R based on commands from the central processing unit
In a dynamic RAM control device that controls access to AM, HADS_-, HW/
R_-, HHLDA, BLAST_- signals and DRAMCS_- signal from the dynamic RAM decoder and C
Mode switching signal generating means generates a mode switching signal for switching between burst mode and normal mode in a memory read cycle in accordance with the BRDY signal from the PU cycle state machine, and the burst mode is selected by the mode switching signal from this signal generating means. 1. A dynamic RAM control device comprising address output means for immediately outputting an address signal used for a burst read cycle of a dynamic RAM when a BRDY_- signal becomes low level.