JPH02178858A - Memory access controller - Google Patents

Abstract

PURPOSE:To access a memory at a high speed with a simple constitution by starting the access with a false address strobe signal generated by a cycle start signal. CONSTITUTION:An access control part 6 is provided, and a cycle start signal ECS and an address strobe signal AS are inputted from an MPU 1 to the control part 6, and the control part 6 generates a pseudo address strobe signal F-AS and a cycle effective signal VLD-CYC and gives them to a DRAM controller 2. The access control part 6 consists of a sequencer or the like. The access is started with the pseudo address strobe signal F-AS. Thus, the memory is accessed at a high speed with the simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Fields> The present invention relates to a memory access control device for rapidly accessing a memory array constituting main memory in a microprocessor system to which a cache memory is added. It is related to.

<Conventional technology> Memory and memory in conventional microprocessor systems
Access is as follows.

In order to achieve high-speed access to the microprocessor,
A cache memory for storing a part of the main memory (DRAM array) is added, and access operations are performed to this cache memory. And the cache
When accessing information stored in memory (Hira)
~) can achieve high-speed operation, and when accessing information that is not in the cache memory (miss), the main memory DRAM is used.
Initiate access to the array.

<Problem to be solved by the invention> By the way, in recent years, the development of microprocessors has been remarkable.
Its operating speed has become much faster.

Due to this, conventional memory devices installed in microprocessors are no longer able to fully utilize the capabilities of microprocessors. Using SRAM, which has a high operating speed, is one way to increase speed, but it is expensive and cannot be used in large quantities. It is also possible to use SRAM as a cache memory, but its peripheral circuits,
The external circuit becomes large and complicated, making it unsuitable for small to medium-sized systems.

It also determines cache memory misses and
Additional time was also required when migrating access to the memory array (memory array).

The technical object of the present invention is to maintain the above-described conventional configuration as much as possible and to perform memory access at high speed with a simple configuration.

Another object of the present invention is to realize a memory access control device that is inexpensive, simple in configuration, and high speed.

<Means for Solving the Problems> The present invention provides a machine/processor that outputs from a microprocessor.
Create a pseudo address signal F-AS using a cycle start signal 1 which indicates the start of a cycle,
This starts accessing the memory array, and determines whether or not this cycle is valid or invalid based on the error (presence or absence of address/sl/lobe borrow AS output) of the memory. , its structure is as follows.

That is, in a memory access control device comprising a microprocessor, a memory array, and a memory control section that receives address signals output from the microprocessor and outputs various access signals to the memory array, A cycle start signal outputted from the processor and an address strobe signal AS are input to send pseudo address signals 1 to 1" to the memory control section.
- an access control unit is provided that sends the A S and makes this cycle valid in the case of a cache memory miss of the microprocessor, and invalidates this cycle in the case of a cache memory miss); The memory control unit uses the pseudo address SL-.

- This is a memory access control device characterized in that access is started by a block signal F-AS.

<Operation> The memory access control device of the present invention operates as follows.

When the access control unit is given a cycle start signal from the microprocessor, the access control unit generates pseudo address signals F-1 to F- regardless of hits or misses in the cache memory.
Send AS to the memory control unit. The memory control section starts accessing the DRAM array in response to this pseudo address strobe signal F-AS. On the other hand, the access control section
In the case of a cache memory miss (address strobe signal λS "7'"), this cycle is valid; in the case of a cache memory hit (address strobe signal AS "H"), this cycle is invalidated. .

<Embodiment> FIG. 1 shows a block diagram of a memory access control device embodying the present invention.

In this figure, 1 is a microprocessor M I)U,
2 are access signals to the DRAM array 3 (row address strobe signal RAS, column address strobe signal CAS, row 1-enable signal WE,
Memory control units such as DRAM controllers 1 to 3 which send addresses RA9 to RA0) are a DRAM array, and the configuration up to this point is the same as that of a conventional memory access control device.

Here, it is assumed that MC68020 is used as MPU1. Furthermore, as peripheral circuits, a decoder 4 selects the DRAM array 3 from the addresses A31-AO sent from the MPU 1, and a decoder 4 that selects the DRAM array 3 from the addresses A31-AO sent from the MPU 1;
A parity generator/checker 5 is installed to monitor errors from 1 to 0.

The present invention provides such a memory access control device with MP
Input cycle start signal EC8 and address strobe signal AS from UI, generate pseudo address signal 1~lobe signal 1''-AS, cycle valid signal VLD-CYC, and send to ``CD RAM core 1-0-ra2''. The feature is that an access control section 6 is provided to provide access control. This access control section 6 is constituted by a sequencer or the like.

Now, the operation of the memory access control device of the present invention having the above configuration will be explained using the time charts shown in FIGS. 2(a) and 2(b).

FIG. 2(a) is a time chart l~ in the case of a cache memory miss in M P tJ l.

When the cycle start signal EC8"'L'° indicating the start of a machine cycle is sent from MPtJl, the access control roller 6 immediately sends the pseudo address strobe signal F"-AS"'■-°". It is generated and output to the DRAM controller 2.

The DRAM controller 2 uses this pseudo address strobe signal F-AS'"L" to open the access,
A row/7' address/slow signal RAS ``L,'' is output to the DRAM array 3.

On the other hand, M P LJ 1 loses the address signal AS ``'I7'' due to a memory error.
" is outputted and given to the access controller 1-roller 6. The access controller 6 outputs a cycle valid signal VLD-CYC" from this address strobe signal AS.
Generate 'L', DR, AM controller l-roller 2
ノ＼Send.

DRAM controller 1 and roller 2 are cycle valid signals ■LD-
With CYC "L'", this access cycle is determined to be valid, and a column address strobe signal CAS "L" is sent out at a specified timing to start access.

In the case of this cache memory miss, in the conventional device, 3'"L" is sent from address strobe 1 to row 1, and then row address strobe signal RAS "
L'', column address strobe signal CAS'';
''' is output and the access starts. However, according to the device of the present invention, since the access is started by the pseudo address strobe signal F-AS "L", the access is preceded by 1/2 clock compared to the conventional device. .

FIG. 2(b) is a time chart in the case of a cache memory hit in the MPUI.

In this time chart, the cycle start signal EC8 "L," is sent from the MPU 1, and the pseudo address slave signal "2W1" is sent from the access controller 6.
°゛L′″ is sent out, and the DRAM controller 2
AM array 3 low address 1 low signal RA
The operation up to outputting S"L" is the same as in the case of cache memory miss in FIG. 2 (a>).

On the other hand, the MPU 1 does not need to access the DRAM array 3 because the cache memory is filled 1~, and does not send out the address strobe signal AS"L'" (valid).

The access controller 6 receives a cycle start signal EC3.
If the address strobe signal AS does not become valid ('L') even after one clock (CLK) has passed after detecting 'L,', the cycle valid signal is invalidated.

As a result, the DRAM controller 1-roller 2 does not output the column address slave signal CAS' even at the predetermined timing t, and invalidates the access that has proceeded halfway.

In the case of cache memory filler 1, access to DRAM array 3 is completed as a simple RAS only refresh.

As described above, the memory access control device of the present invention starts access using the pseudo address strobe signal FAS, and determines the presence or absence of the address strobe signal AS corresponding to the cache memory miss/filler 1-. This determines whether this cycle is valid or invalid.

In the embodiment shown in FIG. 1, the DRAM array 3 is used as the object to be accessed, but the present invention is not limited to this and can be applied to SRAM as well. When applying the present invention to SRAM,
The SRAM has a row address strobe signal RAS,
Since there is no concept of column address slave signal m, cache memory filler 1 ends as a read cycle rather than as a RAS-only refresh cycle.

<Effects of the Invention> According to the memory access control device of the present invention, the following effects can be obtained.

■ Compared to the original access initiated by the address slave signal AS, the present invention uses a pseudo address strotope signal F- generated by the cycle start signal.
Since access is started with AS "L", the operation is preceded by 1/2 clock.

■ Since high-speed access is possible using a conventional DRAM array as is, an inexpensive system can be realized.

(2) Since only two types of signals, the pseudo address strobe signal F-AS and the cycle valid signal VLD-CYC, are generated, the circuit scale is small and can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory access control device embodying the present invention, and FIGS. 2(a) and 2(b) are flowcharts 1 showing the operation of the device of the present invention. 1...Microprocessor M P tJ, 2...D
RAM controller 1-roller, 3...DRAM array,
4...Decoder, 5...Parity generator/
Checker, 6...Access control section.

Claims (1)

[Claims] (1) A memory access control device comprising a microprocessor, a memory array, and a memory control section that receives address signals output from the microprocessor and outputs various access signals to the memory array, A cycle start signal and an address strobe signal @AS@ outputted from the processor are inputted, and a pseudo address strobe signal @F- is sent to the memory control section.
an access control unit that sends an AS@ and also enables a cycle valid signal in the case of a cache memory miss of the microprocessor and invalidates the cycle valid signal in the case of a cache memory hit; A memory access control device characterized in that the control section starts access by the pseudo address strobe signal @F-AS@.