JPH0322618A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPH0322618A JPH0322618A JP1157669A JP15766989A JPH0322618A JP H0322618 A JPH0322618 A JP H0322618A JP 1157669 A JP1157669 A JP 1157669A JP 15766989 A JP15766989 A JP 15766989A JP H0322618 A JPH0322618 A JP H0322618A
- Authority
- JP
- Japan
- Prior art keywords
- output
- gate
- transistor
- circuit
- gate voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は出力回路に関し、特に半導体メモリやマイクロ
コンピュータに内蔵されるＣＭＯＳ型の出力回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to a CMOS type output circuit built into a semiconductor memory or a microcomputer.
従来、この種の出力回路は、第３図に示すような回路構
成を取るものが一般的である。Conventionally, this type of output circuit generally has a circuit configuration as shown in FIG.
ここで工，〜Ｉ３はインバータ、Ｇｌは２人力のＮＯＲ
回路、Ｇ，は２人力のＮＡＮＤ回路であｂ１これらで出
力制御回路１を形成し、Ｍ，はＰ型のトランジスタ、Ｍ
，はＮ形のトランジスタであシ、これらで出力部２を形
威している。Here, ~I3 is an inverter, and Gl is a two-man NOR
The circuit, G, is a two-man NAND circuit b1 These form the output control circuit 1, M, is a P-type transistor, M
, are N-type transistors, and form the output section 2.
またＤＡＴＡは入カデータｓ Ｄｏｔｒｒは出力データ
である。さらにＯＥは出力制御信号であう，高レベルの
時に出力端子は高インピーダンス状態となうＳＧレベル
のとき出力信号Ｉ）ｏｔｒｒは入カデータＤＡＴＡの反
転レベルとなる。Further, DATA is input data s, and Dotrr is output data. Further, OE is an output control signal, and when it is at a high level, the output terminal is in a high impedance state.When it is at an SG level, the output signal I)otrr is at an inverted level of the input data DATA.
上述した従来の出力回路は、出力部１０トランジスタＭ
！がスイッチングすると、負荷容量の電荷を放電する電
流変化と接地配線のインダクタンスにより，接地電位が
揺れ、その結果、ＩＣ内部に誤動作を生ずるという欠点
を有する。１た、この接地電位の揺れは、電源電位が高
ければ高い程大きくなる。The conventional output circuit described above has an output section 10 transistor M
! When the IC switches, the ground potential fluctuates due to the current change that discharges the charge in the load capacitance and the inductance of the ground wiring, resulting in a malfunction inside the IC. Furthermore, the higher the power supply potential is, the larger the ground potential fluctuation becomes.
本発明の目的は、負荷容量の電荷の放電時に、接地電位
の揺れを低減し、ＩＣ内部の誤動作を防止することがで
きる出力回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit that can reduce fluctuations in ground potential and prevent malfunctions inside an IC when the charge of a load capacitor is discharged.
本発明の出力回路は、入力データ及び出力制御信号を入
力して第１及び第２のゲート信号を出力する出力制御回
路と、前記出力制御信号に従って所定のレベルのゲート
電圧制御信号を出力するゲート電圧制御回路と、前記ゲ
ート電圧制御信号によシ制御されて前記第２のゲート信
号を出力端へ伝達する制御トランジスタと、電源端子と
出力端子との間に接続されゲートに前記第１のゲート信
号を入力する一導電型のトランジスタ及び前記出力端子
と接地端子との間に接続されゲートに前記制御ト−）ｙ
ジスタの出力端からの信号を入力する逆導電型のトラン
ジスタを備えたＣＭＯＳ型の出力部とを有している。The output circuit of the present invention includes an output control circuit that inputs input data and an output control signal and outputs first and second gate signals, and a gate that outputs a gate voltage control signal of a predetermined level according to the output control signal. a voltage control circuit; a control transistor that is controlled by the gate voltage control signal and transmits the second gate signal to the output terminal; A transistor of one conductivity type into which a signal is input, and a transistor connected between the output terminal and the ground terminal, and the control transistor connected to the gate.
It has a CMOS type output section including a reverse conductivity type transistor that inputs a signal from the output end of the transistor.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
この実施例は、インバータＩ１〜Ｉ，，ＮＯＲ回路Ｇ．
，ＮＡＮＤ回路Ｇ，を備え、入カデータＤＡＴＡ及び出
力制御信号ＯＥを入力して第１及び第２のグート信号Ｃ
，Ｄを出力する出力制御回路１と、Ｐ形のトランジスタ
Ｍ，，Ｎ形のトランジスタＱ Ｉ＝ Ｑ ｉを備え、出
力制御信号ＤＥに従って所定のレベルのゲート電圧制御
信号Ｌを出力するゲート電圧制御回路３と、ゲート電圧
制御信号Ｌによシ制御されて第２のゲート信号Ｄを出力
端へ伝達するトランスファ用ノンドープＮ形の制御ト２
冫ジスタ４と、電源端子と出力端子Ｔｏとの間に接続さ
れゲートに第１のゲート信号Ｃを入力するＰ形のトラン
ジスタＭ，及び出力端子Ｔｏと接地端子との間に接続さ
れゲートに制御トランジスタ４の出力端からの信号を入
力するＮ形のトランジスタＭ，を備えたＣＭＯＳ型の出
力部２とを有する構成と々っている。In this embodiment, inverters I1 to I, , NOR circuit G.
, NAND circuit G, and inputs input data DATA and output control signal OE to output first and second GUT signals C.
, D, and a P-type transistor M, , N-type transistor Q I = Q i, and outputs a gate voltage control signal L at a predetermined level in accordance with an output control signal DE. circuit 3, and a non-doped N-type transfer control circuit 2 which is controlled by the gate voltage control signal L and transmits the second gate signal D to the output terminal.
a P-type transistor M connected between the power supply terminal and the output terminal To and inputting the first gate signal C to the gate; and a P-type transistor M connected between the output terminal To and the ground terminal and controlled by the gate. The configuration includes a CMOS type output section 2 including an N-type transistor M, which inputs a signal from the output terminal of the transistor 4.
次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
今、トランジスタＱ，〜Ｑｉのしきい電圧をＶ？Ｎとす
ると、ゲート電圧制御回路３の出力信号、すなわちゲー
ト電圧制御信号Ｌは次のようになる。Now, set the threshold voltage of transistors Q, ~Qi to V? When N, the output signal of the gate voltage control circuit 3, that is, the gate voltage control signal L is as follows.
電源電圧をＶＣＣとして、
Ｖｃｃ ＞ＶＴＮ Ｘ ｉ （ＤときＬ＝Ｖ７ＨＸｉ．
ＶＣＣ≦■ＮｘｉのときＬ＝Ｖｃｃとなる。Assuming that the power supply voltage is VCC, Vcc > VTN X i (when D, L=V7HXi.
When VCC≦■Nxi, L=Vcc.
このように、このゲート電圧制御信号Ｌ，すなわち制御
トランジスタ４のゲート電圧は、電源電圧ｖｃｃが上昇
しても■テＨＸｉ以上の電位にはならない。In this way, this gate voltage control signal L, that is, the gate voltage of the control transistor 4, does not reach a potential higher than 1HXi even if the power supply voltage vcc increases.
したがって、出力部２０Ｎ形のトランジスタＭ，のゲー
ト電位ＥもＶｔ＊Ｘｉ−（制御トランジスタ４のしきい
電圧）以上には上昇しない。Therefore, the gate potential E of the transistor M of the output section 20N type does not rise above Vt*Xi- (threshold voltage of the control transistor 4).
以上のようにして、出力部２のＮ形のトランジスタＭ，
のゲート電位Ｅが必要以上に上昇することを抑制して負
荷の放電電流の変化を抑制し、接地ラインの揺れを抑制
することができる。１た、トランジスタＱ，〜Ｑｉの個
数ｉを調整することによｂ１最適の電圧を得ることがで
きる。As described above, the N-type transistor M of the output section 2,
It is possible to suppress the gate potential E from increasing more than necessary, suppress changes in the discharge current of the load, and suppress fluctuations in the ground line. Furthermore, by adjusting the number i of transistors Q, .about.Qi, the optimum voltage of b1 can be obtained.
第２図は，本発明の第２の実施例のゲート電圧制御回路
の回路図である。FIG. 2 is a circuit diagram of a gate voltage control circuit according to a second embodiment of the present invention.
この実施例においては、第１の実施例のゲート電圧制御
回路３のトランジスタＱ１〜Ｑｉの一部をＥＰＲＯＭ型
のメモリトランジスタＴＭ．〜ＴＭｊＫ置き換え、かつ
トラ／ジスタ全体の個数を減らしたものである。In this embodiment, some of the transistors Q1 to Qi of the gate voltage control circuit 3 of the first embodiment are replaced with EPROM type memory transistors TM. ~TMjK is replaced and the total number of transistors/registers is reduced.
メモリトランジスタＴＭ，−ＴＭｊのしきい電圧ＶＴＮ
はＮ形のトランジスタＱ，〜Ｑｔのしきい電圧ＶＴＮに
比べ高く、それだけ直列に接続するト２冫ジスタの数を
へらすことができる。すなわち、ｉ ） ｊ 十ｋ
となる。Threshold voltage VTN of memory transistors TM, -TMj
is higher than the threshold voltage VTN of the N-type transistors Q, -Qt, and the number of transistors connected in series can be reduced accordingly. That is, i ) j 10k.
今、メモリトランジスタＴＭｉ〜ＴＭｊ及びトランジス
タＱ，〜Ｑｋのしきい電圧のばらつきをｊＶｔとすれば
、第１の実施例でのゲート電圧制御信号Ｌの電位のばら
つきぱｉＸｊＶ７第２の実施例でのばらつきはｋ Ｘ
ｊＶＴとなる。Now, if the variations in the threshold voltages of the memory transistors TMi to TMj and the transistors Q, to Qk are jVt, the variations in the potential of the gate voltage control signal L in the first embodiment are equal to iXjV7 in the second embodiment. The variation is k
It becomes jVT.
このように、第２の実施例では第１の実施例に比べゲー
ト電圧制御信号Ｌの電位のぱらつきを抑制することがで
きる。In this way, in the second embodiment, fluctuations in the potential of the gate voltage control signal L can be suppressed compared to the first embodiment.
以上説明したように、本発明は、出力回路部のトランジ
スタのゲート電圧を制御ト−）／ジスタ及びゲー｝！圧
制御回路によシ制御する構或をすることによｂ１出力部
のトランジスタのゲート電位をある一定の電圧以上に上
昇するのを抑制することができるので負荷容量の電荷の
放１！電流の変化を抑制することができ、接地電位の揺
れを低減しＩＣ内部の誤動作を防止することができる効
果がある。As explained above, the present invention controls the gate voltage of the transistor in the output circuit section. By using a voltage control circuit to control the voltage, it is possible to prevent the gate potential of the transistor in the b1 output section from rising above a certain voltage, thereby reducing the discharge of charge in the load capacitance. Changes in current can be suppressed, fluctuations in ground potential can be reduced, and malfunctions inside the IC can be prevented.
図は本発明の第２の実施例のゲート電圧制御回路の回路
図、第３図は従来の出力回路の一例を示す回路図である
。This figure is a circuit diagram of a gate voltage control circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing an example of a conventional output circuit.
１・・・・・・出力制御回路、２・・・・・・出力部、
３．３１・・・・・ゲート電圧制御回路、４・・・・・
・制御トランジスタ、Ｇ，・・・・・・ＮＯＲ回路、Ｇ
，・・・・・・ＮＡＮＤ回路、ＩＩ〜工．・・・・・・
インパータ、Ｍ１〜Ｍｓ＝ Ｑｔ−Ｑｉ−Ｑｋ・・・・
・・トランジスタ、ＴＭ１〜ＴＭｊ・・・・・・メモリ
トランジスタ。1... Output control circuit, 2... Output section,
3.31...Gate voltage control circuit, 4...
・Control transistor, G, NOR circuit, G
,...NAND circuit, II~Eng.・・・・・・
Inperter, M1~Ms=Qt-Qi-Qk...
...Transistor, TM1 to TMj...Memory transistor.
Claims (1)
ゲート信号を出力する出力制御回路と、前記出力制御信
号に従って所定のレベルのゲート電圧制御信号を出力す
るゲート電圧制御回路と、前記ゲート電圧制御信号によ
り制御されて前記第２のゲート信号を出力端へ伝達する
制御トランジスタと、電源端子と出力端子との間に接続
されゲートに前記第１のゲート信号を入力する一導電型
のトランジスタ及び前記出力端子と接地端子との間に接
続されゲートに前記制御トランジスタの出力端からの信
号を入力する逆導電型のトランジスタを備えたＣＭＯＳ
型の出力部とを有することを特徴とする出力回路。an output control circuit that inputs input data and an output control signal and outputs first and second gate signals; a gate voltage control circuit that outputs a gate voltage control signal of a predetermined level according to the output control signal; and the gate a control transistor that is controlled by a voltage control signal and transmits the second gate signal to an output terminal; and a transistor of one conductivity type that is connected between a power supply terminal and an output terminal and inputs the first gate signal to its gate. and a CMOS comprising a reverse conductivity type transistor connected between the output terminal and the ground terminal and inputting a signal from the output terminal of the control transistor to its gate.
An output circuit characterized in that it has a type output section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157669A JP2808678B2 (en) | 1989-06-19 | 1989-06-19 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157669A JP2808678B2 (en) | 1989-06-19 | 1989-06-19 | Output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0322618A true JPH0322618A (en) | 1991-01-31 |
| JP2808678B2 JP2808678B2 (en) | 1998-10-08 |
Family
ID=15654794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1157669A Expired - Lifetime JP2808678B2 (en) | 1989-06-19 | 1989-06-19 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2808678B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0574168A2 (en) * | 1992-06-08 | 1993-12-15 | Advanced Micro Devices, Inc. | High speed CMOS bus driver circuits |
| EP0574184A2 (en) * | 1992-06-12 | 1993-12-15 | Advanced Micro Devices, Inc. | High speed CMOS output buffer circuits |
| JPH07183780A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Output buffeer circuit |
| WO1997029544A1 (en) * | 1996-02-12 | 1997-08-14 | Advanced Micro Devices, Inc. | Gate oxide voltage limiting devices for digital circuits |
| US5849457A (en) * | 1995-05-09 | 1998-12-15 | Sumitomo Chemical Company, Limited | Positive-working quinonediazide sulfonic acid ester resist composition utilizing solvent system including 2-heptanone, ethyl lactate, and γ- |
| DE4324138B4 (en) * | 1992-07-25 | 2008-07-10 | Magnachip Semiconductor, Ltd. | CMOS tri-state buffer circuit |
-
1989
- 1989-06-19 JP JP1157669A patent/JP2808678B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0574168A2 (en) * | 1992-06-08 | 1993-12-15 | Advanced Micro Devices, Inc. | High speed CMOS bus driver circuits |
| EP0574168A3 (en) * | 1992-06-08 | 1994-02-02 | Advanced Micro Devices, Inc. | High speed CMOS bus driver circuits |
| EP0574184A2 (en) * | 1992-06-12 | 1993-12-15 | Advanced Micro Devices, Inc. | High speed CMOS output buffer circuits |
| EP0574184A3 (en) * | 1992-06-12 | 1994-02-23 | Advanced Micro Devices Inc | |
| DE4324138B4 (en) * | 1992-07-25 | 2008-07-10 | Magnachip Semiconductor, Ltd. | CMOS tri-state buffer circuit |
| JPH07183780A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Output buffeer circuit |
| US5849457A (en) * | 1995-05-09 | 1998-12-15 | Sumitomo Chemical Company, Limited | Positive-working quinonediazide sulfonic acid ester resist composition utilizing solvent system including 2-heptanone, ethyl lactate, and γ- |
| WO1997029544A1 (en) * | 1996-02-12 | 1997-08-14 | Advanced Micro Devices, Inc. | Gate oxide voltage limiting devices for digital circuits |
| US5892371A (en) * | 1996-02-12 | 1999-04-06 | Advanced Micro Devices, Inc. | Gate oxide voltage limiting devices for digital circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2808678B2 (en) | 1998-10-08 |
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