KR100351978B1 - Checking and compensating circuit for low voltage detection level - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low voltage detection level diagnosis and compensation circuit. In the conventional circuit, the reference voltage Vref is applied when the voltage of the NMOS transistor NM2 and the power supply voltage Vdd generates a constant reference voltage Vref. The NMOS transistor in the inverter (INV1) that recognizes the value from 'low' to 'high' shows a severe change by the threshold voltage (Vt) value of the process parameter, affecting the test margin and the process control margin. There were many problems such as falling. Accordingly, the present invention includes a test voltage generation unit for outputting test voltages above and below a predetermined margin based on a low voltage LVD level to be detected; A compensation control signal generator for outputting a compensation control signal according to whether a low voltage LVD level is detected at an upper level of an upper margin voltage and a lower level of a lower margin voltage output from the test voltage generator; The low voltage detection level compensation unit adjusts the level of the reference voltage by the compensation control signal output from the compensation control signal generator to compensate for the low voltage within a predetermined margin, thereby increasing or decreasing the threshold voltage Vt. By diagnosing the detection voltage inside the device and compensating within a predetermined margin, not only can the yield be increased, but also a more stable operation can be performed.

Description

CHECKING AND COMPENSATING CIRCUIT FOR LOW VOLTAGE DETECTION LEVEL}

The present invention relates to a low voltage detection (LVD) level diagnosis and compensation circuit, and in particular, due to a threshold voltage (Vt) of a process parameter in which characteristics of the low voltage detection circuit are set differently according to environmental changes in a semiconductor manufacturing process. The present invention relates to a low voltage detection level diagnosis and compensation circuit for diagnosing and compensating a high or low detection voltage internally so that a low voltage can be detected within an accurate level margin.

1 is a conventional low voltage detection circuit diagram, as shown therein, which receives a power supply voltage Vdd and generates a reference voltage Vref by voltage distribution; The low voltage detector 2 detects the level of the power supply voltage Vdd through the reference voltage generator 1 and outputs a low voltage detection signal below a specific level.

At this time, the reference voltage generator 1 receives the power supply voltage Vdd on the source side through the resistor R1 and receives the stop signal Stop on the gate to control the on / off of the PMOS transistor PM1. Wow; An NMOS transistor NM1 having a drain connected to the drain of the PMOS transistor PM1 and controlled by receiving the stop signal Stop from a gate; A gate and a drain are commonly connected to the drain of the PMOS transistor PM1, and a source is formed of the NMOS transistor NM2 grounded through the resistor R2.

In addition, the low voltage detection unit 2 is composed of two inverters INV1 and INV2 connected in series with each other to buffer and output the output level of the reference voltage generator 1, and the operation and operation of the conventional low voltage detection circuit configured as described above. This is as follows.

First, the PMOS transistor PM1 serves as an on / off switch function and an upper resistance of voltage distribution when the low voltage detection LVD function is used, and the NMOS transistor NM2 is always saturated due to a shorted gate and drain. The reference voltage Vref outputted by operating the saturation region maintains a constant level with little influence on the change in the power supply voltage Vdd.

In addition, the inverter INV1 of the low voltage detection unit 2 recognizes the reference voltage level Vref, which was recognized as low in the normal state, and recognizes the reference voltage level as high when the level of the power supply voltage Vdd falls. The inverter INV2 inverts the output of the inverter INV1 to output the low voltage detection signal LVD out.

In other words, the reference voltage Vref is generated by the voltage distribution of (resistance component + resistance R1 of PMOS transistor PM1) and (resistance component + resistance R2 of NMOS transistor NM1). Normally, the 'low' level is maintained and the reference voltage level is almost unchanged when the voltage of the power supply voltage (Vdd) decreases, but the reference was the 'low' input due to the drop of the power supply voltage (Vdd) supplied to the inverter (INV1). The voltage Vref is recognized as 'high' to generate the low voltage detection signal LVD out through the inverter INV2.

As described above, in the conventional circuit, the reference voltage Vref is recognized from 'low' to 'high' during the voltage drop between the NMOS transistor NM2 and the power supply voltage Vdd generating a constant reference voltage Vref. The NMOS transistor in the inverter INV1, which has a function of showing a severe change due to the threshold voltage (Vt) value of the process parameter, has many problems such as a decrease in yield due to an impact on the test margin and the process control margin.

Accordingly, the present invention has been made to solve the above-mentioned problems, and the low voltage detection level that can diagnose the detection voltage higher or lowered by the threshold voltage (Vt) internally and compensate within a predetermined margin. The purpose is to provide a diagnostic and compensation circuit.

1 is a conventional low voltage detection circuit diagram.

2 is a block diagram of a low voltage detection level diagnosis and compensation circuit according to the present invention;

3 is a detailed circuit diagram of a test voltage generator in FIG. 2;

4 is a detailed circuit diagram of a compensation control signal generator in FIG. 2; FIG.

FIG. 5 is a detailed circuit diagram of a low voltage detection level compensation unit in FIG. 2; FIG.

*** Description of the symbols for the main parts of the drawings ***

10: test voltage generator 20: compensation control signal generator

30: low voltage detection level compensation unit 20a: test reference voltage generator

20b: test undervoltage detector 20c: buffer

20d: control signal output unit 30a: variable reference voltage generator

30b: low voltage detection unit PM1 to PM8: PMOS transistor

NM1 to NM11: NMOS transistors R1 to R10: resistors

INV1 to INV5: Inverter C1: Capacitor

NOR1, NOR2: Noah gate Latch1, Latch2: Latch

The present invention for achieving the above object, the test voltage generating unit for outputting the test voltage of the upper and lower predetermined margin on the basis of the low voltage (LVD) level to be detected; A compensation control signal generator for outputting a compensation control signal according to whether a low voltage LVD level is detected at an upper level of an upper margin voltage and a lower level of a lower margin voltage output from the test voltage generator; It is achieved by configuring a low voltage detection level compensator for compensating a low voltage within a predetermined margin by adjusting the level of the reference voltage by the compensation control signal output from the compensation control signal generator, an embodiment according to the present invention. When described in detail with reference to the accompanying drawings as follows.

FIG. 2 is a block diagram of a low voltage detection level diagnosis and compensation circuit according to the present invention. As shown in FIG. 2, a test voltage outputting a test voltage above and below a predetermined margin based on a low voltage LVD level to be detected. A generator 10; The compensation control signal generator 20 outputting a compensation control signal according to whether the low voltage LVD level is detected at an upper level of the upper margin voltage and a lower level of the lower margin voltage output from the test voltage generator 10. )Wow; The low voltage detection level compensator 30 adjusts the level of the reference voltage by the compensation control signal output from the compensation control signal generator 20 to compensate for the low voltage within a predetermined margin. The operation and operation of the present invention constituted will be described.

FIG. 3 is a detailed circuit diagram of the test voltage generator 10. The PMOS transistor PM1 receives a power supply voltage Vdd from a source using poly, which is hardly affected by changes in process parameters. An NMOS transistor NM2 connected in series, the source is grounded, and controlled by receiving a test-on signal TEST_on in common to its gate; A resistor (R3) connected in series via a resistor (R1) to a common connection point of the two transistors (PM1, NM2); The resistor R2 connected in series with each other and the NMOS transistor NM1 receiving the clock CK1 at the gate are connected in parallel with the resistor R3.

In the operation, first, in the 'low' section of the clock CK1, the NMOS transistor NM1 is turned off to distribute the high level voltage of the low voltage detection margin through the resistor R3 to compensate the control signal generator 20. ), The test power supply T_Power is supplied, and in the 'high' section of the next clock CK1, the NMOS transistor NM1 is turned on so that the voltage of the lower level of the low voltage detection margin corresponding to the parallel resistors R2 and R3 is supplied. The test power supply T_Power is supplied to the compensation control signal generator 20 by distributing.

For reference, if the low voltage detection level is 2.5 volts, the upper level is 3 volts and the lower level is 2 volts when the margin is set to 1 volt.

Next, FIG. 4 is a detailed circuit diagram of the compensation control signal generator 20. As shown in FIG. 4, a test reference voltage generator (not shown) receives a test power source T_Power and generates a reference voltage Vref by voltage division. 20a); A test low voltage detector 20b which senses a level of a test power T_Power through the reference voltage generator 20a and outputs a low voltage detection signal below a specific level; A buffer unit 20c for buffering and outputting the output of the test low voltage detector 20b with a power supply voltage Vdd; The control signal output unit 20d receives the low voltage detection signal output through the buffer unit 20c and outputs a compensation control signal in synchronization with the clock CK1.

Here, the test reference voltage generator 20a receives a test power supply T_Power on the source side through the resistor R4 and receives a test on signal TEST_on from the gate to control the on / off of the PMOS transistor. PM2); An NMOS transistor NM3 having a drain connected to the drain of the PMOS transistor PM2 and controlled by receiving the test-on signal TEST_on at a gate thereof; An NMOS transistor NM4 having a gate and a drain connected in common with the drain of the PMOS transistor PM2 and whose source is grounded through a resistor R5; The resistor R6 connected in series with each other and the NMOS transistor NM5 to which the test power source T_Power is applied to the gate are connected in parallel with the resistor R5.

In addition, the test low voltage detector 20b receives a test power source T_Power as an operating voltage and performs the test reference by an inverter configured by connecting PMOS transistors PM3 and PM4 and NMOS transistors NM6 and NM7 in series. It consists of two inverter units connected in series to buffer and output the output level of the voltage generator 20a.

Next, the buffer unit 20c is configured to buffer and output the output level of the test low voltage detector 20b by two inverters INV1 and INV2 connected in series using the power supply voltage Vdd as an operating voltage.

Next, the control signal output unit 20d includes a NOR gate NOR1 configured to receive a clock CK1 through an inverter INV3 at one end thereof and to perform a NOR operation by receiving a test-on signal TEST_on at the other end thereof; A NOR gate NOR2 configured to receive a clock CK1 at one end and a NOR operation by receiving a test-on signal TEST_on at the other end; The outputs of the NOA gates NOR1 and NOR2 are clocked, and the outputs of the buffer unit 20c are commonly received as data inputs and latched to output the compensation control signals option1 and option2 to latches Latch1 and Latch2. The operation by the circuit will be described below.

First, the low voltage detection test is performed at the level of the upper margin in the 'low' section of the clock CK1, and the low voltage detection test is performed at the low margin level in the 'high' section of the clock CK1. Three cases occur as shown in Table 1.

Test level CK1 = 'low' CK1 = 'high' Latch2 Latch1 When higher than upper margin level H H H H Upper margin to lower margin L H L H When lower than margin level L L L L

That is, when the clock level CK1 is 'low', when the test level is greater than the upper margin level, 'high' is output. When low voltage is detected, the signal output from the noar gate NOR2 of the control signal output unit 20d is output. A latch latch2 as a clock latches the 'high' data input to output a compensation control signal option2. Next, when the clock CK1 is in the 'high' section, the test level is smaller than the lower margin level. When the low is output and the low voltage is not detected, the latch Latch1 which clocks the signal output from the NOA gate NOR1 of the control signal output unit 20d as the clock latches the data input of the low to compensate for the control. The signal option1 is outputted.

Next, the low voltage detection level compensation unit 30 slightly decreases the reference voltage Vref level by the compensation control signals option1 and option2 output from the control signal output unit 20d to reduce the low voltage LVD detection level. The configuration is as shown in Fig. 5 to fall within a predetermined margin width.

That is, FIG. 5 is a detailed circuit diagram of the low voltage detection level compensation unit 30. As shown in FIG. 5, the power supply voltage Vdd is generated by the compensation control signals option1 and option2 output from the compensation control signal generation unit 20. As shown in FIG. A variable reference voltage generator 30a for generating a reference voltage Vref by adjusting a distribution voltage of the variable voltage; The low voltage detector 30b detects the level of the power supply voltage Vdd through the variable reference voltage generator 30a and outputs a low voltage detection signal compensated below a specific level.

At this time, the variable reference voltage generator 30a receives the power supply voltage Vdd on the source side through the resistor R7 and receives the stop signal Stop on the gate to control the on / off of the PMOS transistor PM5. )Wow; An NMOS transistor NM8 having a drain connected to the drain of the PMOS transistor PM5 and controlled by receiving the stop signal Stop at a gate thereof; A capacitor C1 connected in parallel with the NMOS transistor NM8; An NMOS transistor NM9 having a gate and a drain connected in common with the drain of the PMOS transistor PM5 and whose source is grounded through a resistor R8; An NMOS transistor NM10 receiving a compensation control signal option1 applied to a resistor R9 and a gate connected in series with each other in parallel with the resistor; A resistor R10 connected in series with the resistor R9 and the transistor NM10 and the NMOS transistor NM11 to which the compensation control signal option2 is applied to the gate.

In addition, the low voltage detector 30b includes two inverters INV4 and INV5 connected in series to each other, buffering and outputting the output level of the variable reference voltage generator 30a.

A detailed operation of the low voltage detection level compensation unit 30 configured as described above is as follows. That is, the low voltage detection level compensation unit 30 outputs the first compensation output from the compensation control signal generator 20. When the control signal option1 is input, the NMOS transistor NM10 is turned on, and the reference voltage Vref is lowered by the parallel resistors R8 and R9. When the second compensation control signal option2 is received, the NMOS transistor NM10 is turned on. NM11 is turned on so that the reference voltage Vref is further lowered by the parallel resistors R8, R9, and R10. In this way, the reference voltage Vref is slightly added or subtracted to determine the low voltage LVD detection level. It is to be made into the margin of the.

As described above, the low voltage detection level diagnosis and compensation circuit of the present invention uses a low voltage detection circuit to detect a low or high detection voltage due to a threshold voltage Vt of a process parameter that is set differently according to environmental changes in a semiconductor manufacturing process. By internally diagnosing and compensating within a predetermined margin, not only can the yield be increased, but also a more stable operation can be performed.

Claims (7)

An NMOS transistor NM2 connected in series with a PMOS transistor PM1 to which a power voltage is applied to the source, the source is grounded, and controlled by receiving a test-on signal TEST_on in common to its gate; A resistor (R3) connected in series via a resistor (R1) to a common connection point of the two transistors (PM1, NM2); The NMOS transistor NM1, which receives the clock CK1 connected in series with the resistor R2 connected in series with each other, is connected to the resistor R3 in parallel so as to be above and below a predetermined margin based on the low voltage LVD level to be detected. A test voltage generator for outputting a test voltage of the test unit; A compensation control signal generator for outputting a compensation control signal according to whether a low voltage LVD level is detected at an upper level of an upper margin voltage and a lower level of a lower margin voltage output from the test voltage generator; A variable reference voltage generator configured to variably generate a reference voltage Vref by adjusting a distribution voltage of the power supply voltage Vdd according to the compensation control signal output from the compensation control signal generator; Low voltage detection level compensation configured to detect the level of the power supply voltage (Vdd) through the variable reference voltage generator to output a low voltage detection signal compensated below a certain level to compensate for the low voltage within a predetermined margin A low voltage detection level diagnosis and compensation circuit, comprising: delete delete The PMOS transistor of claim 1, wherein the test reference voltage generator receives a test power (T_Power) on a source side through a resistor (R4) and receives a test-on signal (TEST_on) from a gate to control the on / off of the PMOS transistor. PM2); An NMOS transistor NM3 having a drain connected to the drain of the PMOS transistor PM2 and controlled by receiving the test-on signal TEST_on at a gate thereof; An NMOS transistor NM4 having a gate and a drain connected in common with the drain of the PMOS transistor PM2 and whose source is grounded through a resistor R5; A low voltage detection level diagnosis and compensation circuit, comprising: a resistor (R6) connected in series with each other and an NMOS transistor (NM5) receiving a test power (T_Power) applied to a gate thereof in parallel to the resistor (R5). 2. The test low voltage detector of claim 1, wherein the test low voltage detection unit receives a test power supply T_Power as an operating voltage, and performs the test by an inverter configured by connecting PMOS transistors PM3 and PM4 and NMOS transistors NM6 and NM7 in series. Low voltage detection level diagnosis and compensation circuit, characterized in that consisting of two inverter units connected in series to buffer and output the output level of the reference voltage generator (20a). The control signal output unit of claim 1, wherein the control signal output unit comprises: a noar gate NOR1 configured to receive a clock CK1 through an inverter INV3 at one end thereof and to perform a NOR operation by receiving a test-on signal TEST_on at the other end; A NOR gate NOR2 configured to receive a clock CK1 at one end and a NOR operation by receiving a test-on signal TEST_on at the other end; The outputs of the NOA gates NOR1 and NOR2 are clocked, and the outputs of the buffer unit are commonly received as data inputs and latched to output compensation control signals option1 and option2. Low voltage detection level diagnosis and compensation circuit. 2. The PMOS transistor of claim 1, wherein the variable reference voltage generator is configured to receive a power supply voltage Vdd from a source through a resistor R7 and receive a stop signal Stop at a gate thereof to control on / off of the PMOS transistor PM5. )Wow; An NMOS transistor NM8 having a drain connected to the drain of the PMOS transistor PM5 and controlled by receiving the stop signal Stop at a gate thereof; A capacitor C1 connected in parallel with the NMOS transistor NM8; An NMOS transistor NM9 having a gate and a drain connected in common with the drain of the PMOS transistor PM5 and whose source is grounded through a resistor R8; An NMOS transistor NM10 receiving a compensation control signal option1 applied to a resistor R9 and a gate connected in series with each other in parallel with the resistor; Low voltage detection level diagnosis and compensation, comprising a resistor R10 connected in series with the resistor R9 and the transistor NM10 and an NMOS transistor NM11 to which a compensation control signal option2 is applied to a gate. Circuit.