KR0125314B1 - Address input buffer - Google Patents

Abstract

Address buffer circuit is used to a memory device, makes an external address signal accurately maintain an original logic state even if a power-supply voltage is varied, and prevents an unnecessary power-consumption in a standby mode. The address buffer circuit includes: an input line for inputting address signal; a control line for inputting an enable signal to control a buffering operation; a buffer for buffering the address signal on the input line; a latch for latching the address signal from the buffer to an output line according to the enable signal; a first switch for switching a power-supply voltage to be provided to the buffer; a first switch controller which is connected between the control line and the first switch, and controls a switching operation of the first switch according to the enable signal; a second switch for switching a ground voltage to be provided to the buffer; and a second switch controller which is connected between the control line and the second switch, and controls a switching operation of the second switch according to the enable signal.

Description

Address input buffer

1 is a circuit diagram of a conventional column address input buffer.

2 is a signal flow diagram when a column address input buffer receives a column address signal in a conventional DRAM.

3 is a circuit diagram of a column address input buffer according to an embodiment of the present invention.

4 is a signal flow diagram when the column address input buffer shown in FIG. 3 receives a column address signal.

* Explanation of symbols for main parts of the drawings

10, 20, 22, 30, 32: Inverter 12, 16, 18, 24, 26: NAND gate

14, 28: latch circuit 34, 36: transmission control circuit

Q1 to Q8: MOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address input buffer of a semiconductor memory device, and more particularly, to an address input buffer that is resistant to noise signals generated in power lines and reduces power consumption.

The present invention can be used for all semiconductor memory devices using the address input buffer.

In general, DRAM receives a row address by a ras (/ RAS) and a casing (/ CAS) signal, gives a row address to a cell of a row axis, and after the row address is latched in a buffer, the column address is sequentially It is supposed to accept. 1 is a circuit diagram showing a conventional column address input buffer that accepts a column address, which is an input line 11 for receiving a column address signal An from the outside and a control line 13 for receiving a control signal phiENB. ), A NAND gate 12 for outputting a NAND logic operation by inputting an inverted signal of the column address signal An and the control signal phiENB, and the control signal phiENB may have a high state. The latch circuit 14 outputs the inverted signal of the signal output from the NAND gate 12 to the first output line 15, and the second output line outputs the inverted signal of the first output line 15. (17) is provided.

The conventional column address input buffer is controlled by the control signal 'phiENB' input to the control line 13, and the 'phiENB' signal is a / RAS signal as shown in the waveform diagram of FIG. 2. It is delayed from the / RAS to enable sufficient latching and is enabled. When the / CAS signal rises, it is disabled to latch the column address input to the column address buffer.

By the way, in the conventional column address input buffer having the above constitution, when switching the NAND gate 12 for inputting the address signal An, it inevitably consumes operating current, which increases as the number of address buffers increases. There was a problem. In addition, due to noise generated from the power supply voltage (Vcc) or ground voltage (Vss), the minimum voltage (V _1h ) that recognizes the 'high' input of the address as 'high' and the 'low' input of the address to 'low' There was also a problem that the maximum voltage (V _1l ) to be recognized is almost the same, so that the input address signal is not recognized correctly and malfunction occurs.

Accordingly, an object of the present invention is to provide an address input buffer capable of buffering an address signal from the outside to maintain its original logic state even when a power supply voltage is changed and preventing unnecessary power consumption in the standby mode. .

In order to achieve the above object, the address buffer circuit of the present invention provides an input line for inputting an address signal, a control line for inputting an enable signal for controlling a buffering operation, and buffering the address signal on the input line. Buffer means for latching, latch means for latching the buffered address signal from the buffer means toward an output line in accordance with the enable signal, first switching means for switching a power supply voltage to be supplied to the buffer means; A first switching control means connected between the control line and the first switching means for controlling a switching operation of the first switching means according to the enable signal, and for switching a ground voltage to be supplied to the buffer means. Second switching control for controlling a switching operation between the second switching means and the control line and the second switching means; It characterized in that it includes a stage.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a column address input buffer according to an embodiment of the present invention, in which an inverter 22 for inputting an address signal from an input line 21 and an address signal inverted by the inverter 22 are shown. The latch circuit 28 for inputting is shown. The inverter 22 is composed of first and second MOS transistors Q1 and Q2 having gates connected to the input line 21. The first MOS transistor Q1 is a PMOS transistor, and when the address signal has a low logic, the latch circuit 28 receives the first power voltage Vcc input via the third MOS transistor Q3. The low logic of the address signal is inverted to a high logic by supplying to. In contrast, the second MOS transistor Q2 is an NMOS transistor. When the address signal has a high logic, the second MOS transistor Q2 receives the second power supply voltage Vcc input through the fourth NMOS transistor Q4 from the latch circuit. 28 to invert the high logic of the address signal to low logic. The low logic of the inverted address signal has the same voltage level as the second input buffer Vss, and the high logic of the inverted address signal has the same power supply voltage as the first input buffer Vcc. The first and second MOS transistors Q1 and Q2 have the latch circuit when the first and second power supply voltages Vcc and Vss are blocked by the third and fourth MOS transistors Q3 and Q4. Make sure the input line of is in high impedance state.

The latch circuit 28 outputs the inverted address signal from the inverter 22 when the low logic enable signal as shown in FIG. 4D is applied from the control line 23. Latched towards the line. The latch circuit 25 is a conventional S-R latch composed of two NAND gates 24 and 26 and a detailed description thereof will be omitted. An inverter 30 connected between the first output line 26 and the second output line 27 inverts the inverted address signal from the latch circuit 28 again. The first and second output lines 25 and 27 are connected to an address decoder (not shown).

The address buffer circuit includes a first transfer control unit 34 for inputting an inverted enable signal from the control line 23 via the inverter 32 and an enable signal from the control line 23 as an input. The transmission control unit 36 is further provided. The first transfer control section 34 includes a fifth MOS transistor Q5 connected between the first power source voltage source Vcc and the line 29 and between the line 29 and the second power source voltage source Vss. The sixth MOS transistor Q6 is connected. The fifth MOS transistor Q5 functions as a resistor having a gate connected to the second power supply voltage source Vss. The sixth MOS transistor Q6 is turned on when the inverted enable signal applied from the inverter 32 toward its gate has high logic, and is turned on through the fifth MOS transistor Q5. Bypass the first power supply voltage (Vcc) supplied to (29) toward the second power supply voltage source (Vss). As a result, the line 29 has a low logic first transmission control signal such as (e) of FIG. 4 having a voltage level divided by internal resistance values of the fifth and sixth MOS transistors Q5 and Q6. Is generated. The voltage level of the low logic transmission control signal may be expressed by the following Equation 1.

VL ₂₉ = R _Q6 × (Vcc-Vss) / (R _Q5 + R _Q6 ) (Equation 1)

In Equation 1, VL ₂₉ is a voltage level of the low logic transmission control signal, and R _Q5 and R _Q6 are internal resistance values of the fifth and sixth MOS transistors Q5 and Q6. The VL ₂₉ has a width of 0.2V or less by setting the channel width of the fifth MOS transistor Q5 to be much smaller than the channel width of the sixth MOS transistor Q6. In addition, when the sixth MOS transistor Q6 is turned off, the line 29 is supplied with a first power supply voltage Vcc via the fifth MOS transistor Q5. A high logic transmission control signal having a voltage level of one power supply voltage Vcc is generated.

On the other hand, the second transfer control unit 36 includes a seventh MOS transistor Q7 connected between the first power source voltage source Vcc and the line 31 and the line 31 and the second power source voltage source Vss. And an eighth MOS transistor Q connected to each other. The eighth MOS transistor Q8 functions as a resistor having a gate connected to the first power source voltage source Vcc. The seventh MOS transistor Q7 is turned on when the enable signal applied from the control line 23 to its gate has a low logic and is turned on from the first power source voltage source Vcc. A power supply voltage Vcc is supplied to the line 31. As a result, the line 31 has a high logic second transmission control signal such as (f) of FIG. 4 having a voltage level divided by internal resistance values of the seventh and eighth MOS transistors Q7 and Q8. Is generated. The voltage level of the high logic second transmission control signal can be expressed by the following equation (2).

VH ₃₁ = R _Q8 × (Vcc-Vss) / (R _Q7 + R _Q8 ) (Equation 2)

In Equation 2, V _H31 is the voltage level of the low logic transfer control signal, and R _Q7 and R _Q8 are internal resistance values of the fifth and sixth MOS transistors Q7 and Q8. The VL31 has a width of about 0.7V by setting the channel width of the eighth MOS transistor Q8 to be smaller than the channel width of the seventh MOS transistor Q7. When the seventh MOS transistor Q7 is turned off, the second power supply voltage is blocked in the line 31 because the first power supply voltage Vcc is blocked by the fifth MOS transistor Q5. A low logic second transmission control signal having a voltage level of (Vss) is generated.

Then, the third MOS transistor Q3 receives the power supply voltage from the first power supply voltage source Vcc when the low logic first transmission control signal is applied from the line 29 to the gate thereof. Transmit to the first MOS transistor Q1 in (22). Similarly, the fourth MOS transistor Q4 receives the power supply voltage from the second power supply voltage source Vss when the high logic second transmission control signal is applied from the line 31 to its gate. Transfer to the second MOS transistor Q2 in (22). As a result, the inverter 22 operates only when the enable signal has low logic to invert and buffer the address signal on the input line 21. In addition, the inverter 22 does not operate when the enable signal has a high logic, thereby making the input line of the latch circuit 28 in a floating state (that is, high impedance). The high logic of the address signal inverted by the inverter 22 has a voltage level of the first power supply voltage Vcc, and the low logic of the inverted address signal has a second power supply voltage Vss. That is, the voltage difference between the high logic and the low logic of the inverted address signal becomes the first power supply voltage Vcc to the second power supply voltage Vss so that the latch circuit can correctly recognize the address signal. Therefore, the address buffer circuit of the present invention can accurately buffer the logic state of the input address signal even when noise occurs in the power supply voltage Vcc and ground voltage Vss power lines.

As described above, the address buffer circuit of the present invention can prevent an inverter that inverts and buffers the address signal in the standby mode, thereby preventing unnecessary power consumption. In addition, the address buffer circuit of the present invention increases the voltage difference between both logics of the inverted address signal supplied to the latch path so that the latch circuit can recognize the address signal accurately. For this reason, the address buffer circuit of the present invention provides an advantage of accurately buffering the logic state of the address signal even when the power supply voltage changes.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (4)

An address input buffer of a semiconductor memory device, comprising: an input line for inputting an address signal, a control line for inputting an enable signal for controlling a buffering operation, buffer means for buffering the address signal on the input line; Latch means for latching the address signal of the buffer from the buffer means toward an output line according to the enable signal, first switching means for switching a power supply voltage to be supplied to the buffer means, and the control line A first switching control means connected to the first switching means for controlling the switching operation of the first switching means according to the enable signal, and a second switching means for switching the ground voltage to be supplied to the buffer means. And switching between the control line and the second switching means in accordance with the enable signal. And an second switching control means for controlling the ring operation. The data input buffer according to claim 1, wherein said buffer means is a CMOS inverter. 2. The data input buffer according to claim 1, wherein said first switching means is a PMOS and said second switching means is an NMOS. 2. The data input buffer according to claim 1, wherein the first switching control means and the second switching control means are CMOS inverters for driving the first and second switching means when the enable signal is in a low state.