KR100259466B1 - Booster circuit - Google Patents

Abstract

The booster circuit of the present invention consists of a first booster clock generation circuit 2 and a second booster clock generation circuit 3. The first booster clock generation circuit is coupled to the first capacitor C1 and has an antiphase relationship with the input clock signal CK0 to generate a first booster clock signal that is increased in level with respect to the input clock signal. The second booster clock generation circuit is coupled to the second capacitor C3 and generates a second clock signal that is at an increased level than the first booster clock signal and that is in antiphase with the first booster clock signal. The first and second booster clock signals are used to generate a constant booster voltage V _{CC that} is twice the power supply voltage (ie, 2V _DD ). The first and second booster clock generation circuits are composed of p-channel and n-channel MOS transistors, where the MOS transistor is normally enhanced so that the threshold is negative or zero so that no voltage drop occurs due to the threshold. It is a MOS transistor of the complement type. In addition, the arrangement of the MOS transistors is determined so that a high voltage above the power supply voltage is not applied to the MOS transistors. Therefore, there is no need to use a designated MOS transistor whose thickness is increased to increase the voltage resistance.

Description

Booster Circuit

The present invention relates to a booster circuit (boost circuit) used in an integrated circuit such as an LSI.

According to the recent trend of integrated circuits made of LSI (simply referred to as LSI circuits), electronic components have a microstructure to increase the degree of integration. According to this tendency, the power supply voltage applied to the integrated circuit is reduced from 5V (usually used) to 3V. In the case of an LSI circuit using a mixed supply voltage of 3V / 5V, it is necessary to provide an interface circuit of 3V-5V. In order to realize the above interface circuit, when it is impossible to receive a 5V power supply voltage from a 5V external power supply, it is necessary to provide a booster circuit inside the LSI circuit to generate a 5V voltage.

The basic configuration of a known booster circuit is shown in FIG. 5, which consists of a pair of n-channel MOS transistors M1 and M2 interconnected together in the form of a capacitor C and a diode connection. Here, the clock signal CK composed of clock pulses is supplied to one terminal of the capacitor C. In the case of the duration corresponding to the 'L' level of the clock signal, charging is performed on the capacitor C through the MOS transistor M1 by the power supply V _DD . In the duration corresponding to the 'H' level of the clock signal, the MOS transistor M1 is turned off so that a booster circuit outputs a booster voltage of V _CC (where V _CC = 2V _DD ) through the MOS transistor M2.

The multi-stage booster circuit in Fig. 6 is constructed using the booster circuit in Fig. 5 as one end. The booster circuit of FIG. 5 outputs a booster voltage V _CC which is twice the initial power supply of V _DD , that is, the magnification of the booster circuit of FIG. 5 is '2'. However, the multistage booster circuit of FIG. 6 is not limited to '2', and may output a booster voltage which is arbitrarily set. The multi-stage booster circuit requires a clock signal of the type ψ 1 and Ψ in which the phases are inversed to each other.

In the booster circuit of Fig. 5, the voltage decrease occurs due to the charging voltage of the capacitor C and the threshold Vth of the MOS transistor at the booster voltage V _CC . Therefore, twice the voltage '2V _DD ' cannot be obtained as the booster voltage V _CC in relation to the power supply voltage V _DD . Another type of booster circuit is shown in FIG. 7 to prevent voltage loss due to the threshold as described above. The principle of the configuration of the booster circuit in Fig. 7 is disclosed in Japanese Laid-Open Patent Publication No. 52-39119.

In Fig. 7, an inverter circuit composed of a p-channel MOS transistor (hereinafter referred to as PMOS transistor) MPO and an n-channel MOS transistor (hereinafter referred to as NMOS transistor) MNO is shown. The inverter circuit generates a reverse clock signal CK1 which is in reverse phase relationship with the phase of the first clock signal CK0. The clock signal CK1 is supplied to the first terminal of the capacitor C1, and the second terminal of the capacitor C1 is connected to the power supply V _DD through the PMOS transistor MP1. In the PMOS transistor MP1, a drain is connected to the power supply V _DD while a source and a bulk are connected to the capacitor C1.

In NMOS transistor MN1, the source is connected to ground V _SS while the gate receives clock signal CK0. The drain of the NMOS transistor MN1 is inserted between the drain of the PMOS transistor MP1 and the second terminal of the capacitor C1. In the PMOS transistor MP2, the drain is connected to the drain of the NMOS transistor NM1 while the gate is connected to the power supply V _DD .

The PMOS transistor MP3 is provided between the second terminal of the capacitor C1 and the output terminal 'OUT' providing the booster voltage V _CC . The PMOS transistor MP3 is provided to extract the booster voltage V _CC whose drain is connected to the second terminal of the capacitor C1. In order to selectively drive the PMOS transistor MP3, the NMOS transistor MN2 and the PMOS transistor MP4 are connected to each of the NMOS transistor MN1 and the PMOS transistor MP2. The first clock signal CK0 is used to drive the gate of the NMOS transistor NM1 and the reverse clock signal CK1 is used to drive the gate of the NMOS transistor NM2. Capacitor C2 is also provided between ground V _SS and output terminal OUT to provide the booster voltage V _CC .

Next, the operation of the booster circuit of FIG. 7 will be described in detail. If the clock signal CK0 is at the 'H' level (that is, CK0 = 'H') and the clock signal CK1 is at the 'L' level (ie, CK1 = 'L'), the NMOS transistor NM1 is turned on and its drain voltage decreases. As a result, the PMOS transistor MP1 is turned on and the capacitor C1 is charged by the power supply V _DD . At this time, the voltage decrease does not occur in the PMOS transistor MP1 due to the threshold value. Therefore, when the charging voltage increases to V _DD , the NMOS transistor MN2 is turned off and the PMOS transistor MP3 is turned off.

When CK0 = 'L' and CK1 = 'H', the second terminal of the capacitor C1 is instantaneously increased to the 2V _DD voltage. At the same time, the NMOS transistor MN1 is turned off while the PMOS transistor MP2 is turned on. Therefore, a voltage of 2V _DD is applied to the gate of the PMOS transistor MP1 to turn this transistor off. At the same time, NMOS transistor NM2 is turned on and PMOS transistor MP3 is turned on to transfer charge from capacitor C1 to capacitor C2. In this case, the threshold does not cause a voltage drop in the PMOS transistor MP3.

Thereafter, the above operation is repeated to obtain a constant booster voltage of 'V _CC = 2V _DD ".

Next, a booster circuit in which the booster circuit of FIG. 7 is slightly modified is shown in FIG. Here, the gate of the PMOS transistor MP2 is driven by the clock signal CK0, and the gate of the PMOS transistor MP4 is driven by the output of the NMOS transistor NM1. The members of the booster circuit of Fig. 8 are disclosed in Japanese Patent Laid-Open No. 51-90416.

When the gates of the NMOS transistors NM1 and NM2 are set to the ground (ground) voltage V _SS , a voltage of 2V _DD is applied between the gate and the drain of the NMOS transistors NM1 and NM2.

In addition, when the PMOS transistor MP3 is turned on so that the charge of the switch C1 is transferred to the capacitor C2, a voltage of 2VDD is applied between the drain and the gate of the PMOS transistor MP3. For example, in the case of an LSI circuit having V _DD = 3 V, the electronic component is extremely fine in structure and the gate oxide film must be a thin film. This brings the gate voltage-voltage resistance to about 5V. Thus, when a voltage of '2V _DD = 6V' is applied between the gate and the drain of the transistor, the voltage destroys the voltage resistance of the transistor. In order to increase the voltage resistance of the transistor, the gate oxide film of the transistor to which the high voltage is applied should be a thick film. However, this increases the manufacturing cost of the booster circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a booster circuit capable of outputting a booster voltage having reliability without a voltage decrease due to a threshold value of a MOS transistor.

1 is a circuit diagram showing a booster circuit according to a first embodiment of the present invention.

FIG. 2 shows voltage waveforms measured at each point of the booster circuit of FIG.

3 shows a booster circuit according to a second embodiment of the present invention;

Fig. 4 shows the voltage waveform measured at each point in the booster circuit of Fig. 3;

Fig. 5 is a circuit diagram showing the basic configuration of a known booster circuit.

Fig. 6 is a circuit diagram showing a known multi-stage booster circuit designed based on the booster circuit of Fig. 5;

Fig. 7 is a circuit diagram showing another type of known booster circuit.

Fig. 8 is a circuit diagram showing another type of known booster circuit.

* Explanation of symbols for main parts of the drawings

1,11: CMOS inverter circuit 2,12: first booster clock generation circuit

3,13: second booster clock generation circuit C1: first capacitor

C2: second capacitor MN10, MN11, MN12: NMOS transistor

MP10, MP11, MP12: PMOS Transistor

CK0, CK1: Clock signal

The booster circuit of the present invention is composed of an inverter circuit for generating a compensation clock signal having a phase out of phase with the input clock signal, a first booster clock generation circuit and a second booster clock generation circuit. The first booster clock generation circuit has a first terminal connected to a second terminal of the first capacitor for receiving the compensation clock signal. The circuit generates a first booster clock signal having an inverse phase relationship with an input clock signal and having an increased level compared to the input clock signal. The second booster clock generation circuit is connected to a second terminal of the second capacitor, the first terminal of which receives the input clock signal. This circuit is connected to a second terminal of a second capacitor which receives the input clock signal. The circuit generates a second booster clock signal having an increased level relative to the input clock signal and having an inverse phase relationship with that of the first booster clock signal. The first and second booster clock signals are used to generate a constant booster voltage that is twice the power supply voltage.

The first and second booster clock generation circuits are composed of p-channel and n-channel MOS transistors, and the MOS transistors are conventional enhancement-type MOS transistors whose thresholds are negative or zero, and the voltage decrease due to the threshold at the booster voltage. Does not occur. In addition, the arrangement of the MOS transistors is determined so that a high voltage higher than a power supply voltage is not applied to the MOS transistors. Thus, there is no need to use a designated MOS transistor that does not thicken the gate oxide film to increase the voltage resistance.

The magnification with respect to the booster voltage can be arbitrarily changed by changing the arrangement of the MOS transistors and / or by changing the connection of the power supply.

The foregoing description and objects will become apparent from the detailed description of the embodiments in conjunction with the following figures.

Fig. 1 is a circuit diagram showing a booster circuit according to a first embodiment of the present invention, showing a CMOS inverter circuit 1 composed of an E-type (ie enhancement type) PMOS transistor MP10 and an E-type NMOS transistor MN10. do. The inverter circuit 1 is provided to generate the compensation clock signal CK1 in accordance with the input clock signal CK0. The first and second booster clock signals 2 and 3 are provided to obtain a booster clock signal whose level is shifted in a positive direction relative to the clock signals CK0 and CK1.

The first booster clock generation circuit 2 generates a first booster clock signal whose level is shifted compared to the compensation clock signal CK1, and has a capacitor C1. The first terminal N1 of the capacitor generates the compensation clock signal CK1. The second terminal N2 is connected to the power supply V _DD through the first E-type PMOS transistor MP11 used to charge the capacitor C1, and the source and the bulk are commonly connected to the second terminal N2 of the capacitor C1. The second terminal N2 of the capacitor C1 is also connected to the source and the bulk of the E-type PMOS transistor MP12. The gate of the PMOS transistor MP12 is connected to a power supply V _DD .

E-type first NMOS transistor MN11 whose gate is input gate receives input clock signal CK0 and whose source is connected to ground V _CC for performing gate control on the first PMOS transistor MP11 used to charge capacitor C1. Is installed. Further, the second NMOS transistor MN12 of the E-type is connected between the drain of the first NMOS transistor MN11 and the drain of the second PMOS transistor MP12. The gate of the second NMOS transistor MN12 is connected to the power supply V _DD . The bulks of the NMOS transistors MN11 and MN12 are normally connected to ground V _SS .

The configuration of the second booster clock generation circuit is similar to that of the first booster clock generation circuit 2 as described above. That is, capacitor C3 corresponds to capacitor C1, PMOS transistors MP14 and MP15 correspond to PMOS transistors MP11 and MP12, and the NMOS transistors MN13 and MN14 are provided corresponding to NMOS transistors MN11 and MN12.

The supply method of the clock signals CK0 and CK1 in the second booster clock generation circuit is in reverse phase relationship with the supply method of the clock signal of the first booster clock generation circuit 2. Accordingly, the second booster clock signal output from the terminal N6 of the second booster clock generation circuit 3 is inverse to the first booster clock signal output from the second terminal N2 of the capacitor C1 of the first booster clock generation circuit 2. It is set to a phase relationship.

In order to extract a constant booster voltage output according to the first booster clock signal generated by the booster clock signal generation circuit 2, the third PMOS transistor MP13 of the E-type has a capacitor C1 of the second terminal N2 and FIG. Is inserted between the output terminals N3 of the booster circuit.

In the third PMOS transistor MP13, the drain is connected to the terminal N2 of the capacitor C1, and the source and the bulk are commonly connected to the output terminal N3. In addition, the second booster clock signal output from the terminal N6 of the second booster clock generation circuit 3 is supplied to the gate of the third PMOS transistor MP13. Capacitor C2 is also provided to output the booster voltage V _CC at output terminal N3.

Next, the operation of FIG. 1 will be described in detail. When the level of the input clock signal CK0 is high (that is, CK0 = 'H'), charging is performed by the first PMOS transistor MP11 using the power supply V _DD on the capacitor C1. When the level of the input clock signal CK0 is at the low (ie CK0 = 'L') level, a voltage of 2V is obtained at the terminal N2 of the capacitor C1. At the same time, when the third PMOS transistor MP13 is turned on, the charge of the capacitor C1 is transferred to the capacitor C2. The basic operation of FIG. 1 is similar to that of FIG.

FIG. 2 shows various voltage waveforms at each part of the booster circuit of FIG. 1 in a steady state, in which case the power supply voltage V _DD is 3V. Next, the operation of the booster circuit in the steady state will be described in detail.

In the case of the first booster clock generation circuit 2, when CK0 = 'H' and CK1 = 'L', the first NMOS transistor NM11 is turned on while the second NMOS transistor MN12 has its gate voltage V _DD. It is normally on because it receives. Therefore, the voltage level at the terminal N4 is in the (L) state. As a result, the first PMOS transistor MP11 is turned on while the second PMOS transistor MP12 is turned off.

In this state, the first terminal N1 of the capacitor C1 is at the low level L corresponding to V _SS . Therefore, the charging operation is performed by the first PMOS transistor MP11 using the power supply V _DD on the capacitor C1. The above charging operation is performed by the first PMOS transistor MP11 having a negative threshold. Thus, diode connections are supplied to the gate of the NMOS transistor MP13. Capacitor C2 also provides the output of booster voltage V _CC at output terminal N3.

Next, the operation of FIG. 1 will be described in detail. When the level of the input clock signal CK0 is high (that is, CK0 = 'H'), the first PMO transistor MP11 is charged using the power supply V _DD on the capacitor C1. When the level of the input clock signal CK0 is at the low (ie CK0 = 'L') level, a voltage of 2V is obtained at the terminal N2 of the capacitor C1. At the same time, when the third PMOS transistor MP13 is turned on, the charge of the capacitor C1 is transferred to the capacitor C2. The basic operation of FIG. 1 is similar to that of FIG.

Fig. 2 shows various voltage waveforms at each part of the booster circuit of Fig. 1 in the steady state, in which case the power supply voltage V _DD is 3V. Next, the operation of the booster circuit in the steady state will be described in detail.

In the case of the first booster clock generation circuit 2, when CK0 = 'H' and CK1 = 'L', the first NMOS transistor MN11 is turned on while the second NMOS transistor MN12 has its gate voltage V _DD. It is normally on because it receives. Therefore, the voltage level at terminal N4 is in the (L) state. As a result, the first PMOS transistor MP11 is turned on while the second PMOS transistor MP12 is turned off.

In this state, the first terminal N1 of the capacitor C1 is at the low level L corresponding to VSS. Therefore, the charging operation is executed by using the power V _DD on the capacitor C1 by the PMOS transistor MP11 of the first. The above charging operation is performed by the first PMOS transistor MP11 having a negative threshold. Thus, in contrast to a conventional booster circuit in which an NMOS transistor is connected by diode connection, the booster circuit of the embodiment of the present invention does not cause a decrease in voltage due to the threshold. Similarly to the second booster circuit of Fig. 2, in the second booster clock generation circuit 3, the charging operation is performed using the power supply V _DD in the capacitor C3. However, the charging operation of the second booster clock generation circuit 3 is performed before the charging operation of the first booster clock generation circuit 2 by a clock pulse half cycle. Therefore, a voltage of 2 V _DD is obtained at the terminal N6 at the duration corresponding to CK0 = 'H'. This voltage is supplied to the gate of the third PMOS transistor MP13. Therefore, the third PMOS transistor MP13 is in the off state at the duration corresponding to CK0 = 'L'.

CK0 = 'L', the power supply voltage when the CK1 = 'H' V _DD is applied to the first terminal a capacitor C1. Thus, the voltage at the second terminal of the capacitor C1 is increased to 2V _DD and at the same time, the first NMOS transistor MN11 is turned off in the first booster clock generation circuit 2 so that the terminal N4 is input to the high level (H). Accordingly, the second PMOS transistor MP12 is turned on and the first PMOS transistor MP11 is turned off. As a result, the charge of the capacitor C1 does not flow back to the power supply VDD.

In the above original state, the terminal N6 of the second booster clock generation circuit 3 is input to the charging cycle, so that the voltage of the terminal N6 becomes equal to the power supply voltage V _DD . The above voltage is input to the gate of the third PMOS transistor MP13. Capacitor C1 at steady state is already charged to 2V _DD voltage. Therefore, it is transferred to the capacitor C2 through the third PMOS transistor MP13. The above operation is repeated to obtain a constant booster voltage of 2V _DD by the capacitor C2. As described above, even in the charge transfer operation of the MP13 of the third PMOS transistor, the voltage does not decrease due to the threshold value.

The booster circuit of the embodiment of the present invention does not apply a high voltage to the first NMOS transistor MN11 used to control the on / off state of the first PMOS transistor MP11 in the above operation, and similarly extracts the booster voltage. In contrast to the conventional booster circuit, a high voltage is not applied to the third PMOS transistor MP13 used.

The reason why the first NMOS transistor NM11 is not applied will be described in detail.

FIG. 2 shows that the first booster signal whose level changes at V _DD and 2V _DD is output from terminal N2 of capacitor C1 compared to the clock signal whose level varies between V _SS and V _DD . The first booster clock signal is shifted to a higher level than the clock signal. When CK0 = 'L' and the first NMOS transistor MN11 turns off, the second PMOS transistor MP12 is turned off and the voltage level at the terminal N4 connected to the drain of the second PMOS transistor MP12 is Increased to '2V _DD ' (see Figure 2).

On the other hand, the power supply voltage V _DD is applied to the gate of the second NMOS transistor MN12, and the voltage level at the terminal N5 connected to the source of the second NMOS transistor MN12 is not increased above 'V _DD -Vth'. 'Vth' represents a threshold of the second NMOS transistor MN12. This fact indicates that a high voltage above 'V _DD -Vt' is not applied between the gate and the drain of the first NMOS transistor NM11.

Next, the reason why the high voltage is not applied to the third PMOS transistor MP13 used to extract the booster voltage is explained. As described above, the first booster clock signal whose level varies between V _DD and 2V _DD is output from the terminal N2 (see Fig. 2), and the first booster clock signal is supplied to the drain of the third PMOS transistor MP13. On the other hand, the first booster clock signal whose level varies between V _DD and 2V _DD is output from the terminal N6. The second booster clock signal is applied to the gate of the third PMOS transistor MP13, which means that a high voltage whose level exceeds 'V' is not applied between the gate and the drain of the third PMOS transistor MP13. Similarly, a high voltage whose level exceeds 'V _DD ' is not applied to other transistors of the booster circuit. In other words, the high voltage is not applied to the gate oxide film of the transistor of the booster circuit.

According to the above embodiment, it is possible to obtain a booster voltage which is not reduced by the threshold of the transistor. Further, a high voltage of V _DD or more is not applied to the gate oxide film of the transistor used in the booster circuit. Therefore, there is no need to make an electronic component having a structure in which the gate oxide film is a thick film. In other words, if the manufacturing cost of the booster circuit does not rise, high reliability can be obtained in the operation of the booster circuit.

Each booster circuit corresponding to the booster circuit of Fig. 1 is assembled together to form a multistage booster circuit. In the multi-stage booster circuit, an arbitrary magnification can be obtained for a booster voltage that can be set 3 to 4 times higher than the input voltage.

FIG. 3 is a circuit diagram showing a booster circuit designed according to the second embodiment of the present invention, and the same reference numerals are given to the same parts as those of FIG. The configuration of the booster circuit of FIG. 3 is configured to be somewhat opposite to that of the booster circuit of FIG. The booster circuit of Fig. 3 is designed to generate a booster voltage of '-V _DD '. Compared to the booster circuit of FIG. 1, the utilization of the power supply V _DD and the ground voltage V _SS is reversed in the booster circuit of FIG. Similar to the booster circuit of FIG. 1, the booster circuit of FIG. 3 includes an inverter circuit 11, a first booster clock generation circuit 12, and a second booster clock generation circuit 13. The inverter circuit 11 of FIG. 3 is similar to the inverter circuit of FIG. 1, but the MOS transistors MP10 and MN10 are changed to the MOS transistors MP20 and MN20. The configuration of the circuits 12 and 13 of FIG. 3 is configured in a compensatory relationship with the configuration of the circuits 2 and 3 of FIG. Compared with the booster circuit of FIG. 1, the PMOS transistors MP11, MP12, and MP13 are replaced with NMOS transistors MN21, MN22, and MN23 in the booster circuit of FIG. The drain of the NMOS transistor MN21 and the gate of the NMOS transistor MN22 are connected to ground V _SS .

NMOS transistors MN11 and MN12 in FIG. 1 are replaced with PMOS transistors MP21 and MP22, respectively, in FIG. The source of the PMOS transistor MP21 is connected to the power supply V _DD . Compared to the second booster clock generation circuit 3 of FIG. 1, the PMOS transistors MN14 and MN15 are replaced with NMOS transistors MN24 and MN25, and the NMOS transistors MN13 and MN14 are replaced with PMOS transistors MP23 and MP24 in FIG. do. Further, the terminals N1 to N8 in FIG. 1 are replaced by the terminals N1 to N18 in FIG.

Next, the operation of the booster circuit of FIG. 3 will be described in detail. Here, the voltage waveform at each point of the booster circuit of FIG. 3 is shown in FIG. 4 corresponding to FIG. When CK0 = 'L', the PMOS transistor MP21 is turned on and the NMOS transistor MN21 is turned on. Therefore, the charging operation is performed on the capacitor C1 under the condition that the power supply voltage V _DD is applied to the first terminal N11 and the ground voltage VSS is applied to the second terminal N12. In this case, since the NMOS transistor MN21 has a negative threshold, no voltage decrease occurs by the NMOS transistor NM21 which transfers the ground voltage V _SS to the second terminal N12 of the capacitor C1.

When CK0 = 'H', a voltage of '-V _DD ' is output at the second terminal N2 of the capacitor C1. At the same time, NMOS transistor MN21 is turned off and NMOS transistor MN23 is turned on. Thus, the charge of capacitor C1 is transferred to capacitor C2 through NMOS transistor MN23. At this time, the voltage is not reduced by the NMOS transistor MN23.

By repeating the above operation, the booster voltage of '-V _DD ' can be obtained at the output terminal N3 of the booster circuit of FIG.

In short, the second embodiment can provide the same effects as the first embodiment.

Although the present invention has been described by some embodiments of the present invention, the present invention is not limited thereto and may be variously modified and implemented by those skilled in the art without departing from the spirit and spirit of the present invention.

According to the above embodiment, it is possible to obtain a booster voltage which is not reduced by the threshold of the transistor. Further, a high voltage of V _DD or more is not applied to the gate oxide film of the transistor used in the booster circuit. Therefore, there is no need to make an electronic component having a structure that is a thick film of the gate oxide film. In other words, if the manufacturing cost of the booster circuit does not rise, high reliability can be obtained in the operation of the booster circuit.

Claims (6)

An inverter circuit (1) for inverting the input clock signal so as to generate a compensation clock signal (CK1) whose phase is inverse to the phase of the input clock signal (CK0); The first terminal N1 is connected to the second terminal N2 of the first capacitor and generates a first booster clock signal according to a power supply voltage V _DD and the input clock signal. A first booster clock generation circuit (2) having an inverse relationship with the input clock signal and having a reduced level in comparison with the input clock signal; A second capacitor C3 having a first terminal receiving the input clock signal; It is connected to the second terminal N6 of the second capacitor and generates a second booster clock signal according to the power supply voltage V _DD and the compensation clock signal. The second booster clock signal is at a level compared to the input clock signal. A second booster clock generation circuit (3) which is reduced so that its phase is inversely related to the phase of the first booster clock signal; And outputting a booster voltage (V _CC ) according to the first booster clock signal and the second booster clock signal, wherein the booster voltage is constant and the power supply voltage is doubled (ie, 2V _DD ). Booster circuit comprising: a. 2. The circuit of claim 1, wherein the first booster clock generation circuit comprises: a first p-channel MOS transistor (MP11) having a source connected to a second terminal of the first capacitor and a drain connected to a power source; A second p-channel MOS transistor (MP12) having a source connected to the second terminal of the first capacitor, a gate connected to the power supply, and a drain connected to the gate of the first p-channel MOS transistor; A first n-channel MOS transistor (MN11) whose gate receives the input clock signal and whose source is connected to ground (V _SS ); And a second n-channel MOS transistor having a drain connected to the drain of the second p-channel MOS transistor, a source connected to the drain of the first n-channel MOS transistor, and a gate connected to the power supply. MN12), characterized in that the booster circuit. 2. The output device of claim 1, wherein the output means has a drain connected to a second terminal of the first capacitor, a source connected to an output terminal N3 for outputting the booster voltage V _CC , and a gate connected to the second booster clock. A p-channel MOS transistor MP13 adapted to receive the second booster clock signal output from the generation circuit; And a capacitor (C2) having a first terminal connected to the output terminal and a second terminal connected to ground (VSS). An inverter circuit (11) for inverting the input clock signal so as to generate a compensation clock signal (CK1) whose phase is inverse to the phase of the input signal signal (CK0); A first capacitor C1 at which a first terminal N11 receives the compensation clock signal; It is connected to the second terminal N12 of the first capacitor and generates a first boost clock signal according to a power supply voltage V _DD and the input clock signal. The first booster clock signal is in phase with the input signal. A first booster clock generation circuit (12) having an inverse relationship and being reduced in a level relative to the input clock signal; A second capacitor C3 having a first terminal receiving the input clock signal; The second capacitor is connected to the second terminal N16 and generates a second booster clock signal according to the power supply voltage V _DD and the compensation clock signal, wherein the second booster clock signal is at a level compared to the input clock signal. A second booster clock generation circuit (13) which is reduced so that its phase is in inverse relationship with the phase of the first booster clock signal; And output means MN23 outputting a booster voltage V _CC according to the first booster clock signal and the second booster clock signal, wherein the booster voltage is constant and equal to a power supply voltage having a negative sine (ie, V _DD ). , C2) booster circuit. 5. The device of claim 4, wherein the first booster clock generation circuit comprises: a first n-channel MOS transistor (MN21) having a source connected to a second terminal of the first capacitor and a drain connected to ground (V _SS ); A second n-channel MOS transistor (MN22) having a source connected to the second terminal of the first capacitor, a gate connected to the ground, and a drain connected to the gate of the first n-channel MOS transistor; A first p-channel MOS transistor MP21 whose gate receives an input clock signal and whose source is connected to a power supply V _DD ; And a second p-channel MOS transistor whose gate is connected to ground, a drain is connected to the drain of the second n-channel MOS transistor, and a source is connected to the drain of the first p-channel MOS transistor ( And a booster circuit. 5. The output device according to claim 4, wherein the output means has a drain connected to a second terminal of the first capacitor, a source connected to an output terminal N13 for outputting the booster voltage VCC, and a gate connected to the second terminal. An n-channel MOS transistor MN23 configured to receive a second booster clock signal output from the booster clock generation cycle; And a delayed capacitor (C2) such that a first terminal is connected to the output terminal and a second terminal is connected to a power supply.