JPH0951669A - Booster circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a booster circuit which can obtain step-up voltage without causing a voltage drop of threshold component and realize high reliability without causing a rise in the cost. SOLUTION: In the first booster clock generating circuit 2, a clock CK1 is supplied to a terminal N1 of a capacitor C1, and a terminal N2 is charged with VDD, when the CK1 is 'L', through the first PMOS transistor MP11. As the use for controlling the first PMOS transistor MP11, the first NMOS transistor MN11 connecting the source to VSS, second PMOS transistor MP12 connecting the source to the terminal N2 and further the second NMOS transistor MN12 between these transistor MN11, MP11 are interposed. In order to take out step-up voltage when the CK1 is 'H', the third PMOS transistor MP13 is provided, and in order to drive a gate of this transistor MP13, the second booster clock generating circuit 3, having a similar constitution to the first booster clock generating circuit 2, is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit used in a large scale semiconductor integrated circuit (LSI) or the like.

[0002]

2. Description of the Related Art In recent years, LSIs have been miniaturized and highly integrated, and the power supply voltage has been increased from the conventional 5V to 3V.
Some are made down to V. 3V / 5V mixed LSI
Then, a 3V-5V interface circuit is required.
However, in order to realize such an interface circuit, when the external power supply of 5V cannot be supplied due to the substrate layout, it is necessary to form a booster circuit inside to generate 5V.

As shown in FIG. 5, a conventionally known basic boosting circuit is composed of a capacitor C and two diode-connected n-channel MOS transistors M1 and M2. When the clock is supplied to one end of the capacitor C, the capacitor C is charged from the power supply VDD through the MOS transistor M1 when the clock is "L", and the MOS transistor M1 is turned off when the clock becomes "H". As a result, a boosted voltage Vcc = 2VDD is output via the MOS transistor M2.

Based on the booster circuit of FIG. 5, if it is constructed in multiple stages as shown in FIG. 6, for example, a necessary boosting factor can be obtained without being limited to the double voltage. However, in FIG. 6, the clocks φ1 and φ2 are in opposite phases to each other.

In the basic booster circuit of FIG. 5, since the charging voltage of the capacitor and the boosting voltage of the output have a decrease corresponding to the threshold value Vth of the MOS transistor, a complete double voltage 2VDD with respect to the power supply voltage VDD can be obtained. I can't. A circuit shown in FIG. 7 is conceivable as a booster circuit in which there is no loss due to the decrease in the threshold value. The configuration principle of this booster circuit is shown in Japanese Patent Laid-Open No. 52-39119.

In FIG. 7, p-channel MOS transistors (hereinafter referred to as PMOS transistors) MP0 and n
An inverter composed of a channel MOS transistor (hereinafter referred to as an NMOS transistor) MN0 produces a clock CK1 having a phase opposite to that of the input clock CK0. The clock CK1 is supplied to the first terminal of the capacitor C1. The second terminal of the capacitor C1 is connected to the power supply VDD through the PMOS transistor MP1. PMO
The S-transistor MP1 has a drain on the side of the power supply VDD,
The source and bulk are connected to the capacitor C1 side.

On the other hand, an NMOS transistor MN1 whose source is connected to the ground VSS and whose clock is supplied with the clock CK0 is prepared, and its drain is connected to the gate of the PMOS transistor MP1. Further, the PMOS transistor MP2 is interposed between the drain of the NMOS transistor MN1 and the second terminal of the capacitor C1. PM
The OS transistor MP2 is an NMOS transistor MN
The first side is the drain, and the gate is connected to the power supply VDD.

A PMOS transistor MP3 having a drain on the side of the capacitor C1 is provided between the second terminal of the capacitor C1 and the output terminal for the boosted voltage in order to take out the boosted voltage. In order to selectively drive the PMOS transistor MP3, the NMOS transistors MN1 and PMO are
An NMOS transistor MN2 and a PMOS transistor MP4 are provided corresponding to the S transistor MP2. The gate of the NMOS transistor MN2 is driven by the clock CK1 having a phase opposite to that of the NMOS transistor MN1. A capacitor C2 is provided at the boosted voltage output end.

The operation of this booster circuit is as follows.
When the clock is CK0 = "H" and CK1 = "L", N
The MOS transistor MN1 is turned on and the drain voltage thereof is lowered, whereby the PMOS transistor MP1 is turned on and the capacitor C1 is charged from VDD. At this time, since the PMOS transistor MP1 has no voltage drop due to the threshold value, the charging voltage can be obtained up to VDD. Meanwhile, the NMOS transistor MN2 is turned off, and thus the PMO
The S transistor MP3 is off.

When CK0 = "L" and CK1 = "H", the second terminal of the capacitor C1 instantaneously rises to 2VDD. At the same time, the NMOS transistor MN1 is turned off, the PMOS transistor MP2 is turned on, and 2VDD is given to the gate of the PMOS transistor MP1 to turn it off. At this time, the NMOS transistor M
N2 is turned on, and thus the PMOS transistor MP3 is turned on, and the charge of the capacitor C1 is transferred to the capacitor C2. Also at this time, there is no decrease due to the threshold value of the PMOS transistor MP3. After that, the same operation is repeated to obtain a constant boosted voltage VCC = 2VDD.

In the booster circuit shown in FIG. 8, the gate drive of the PMOS transistor MP2 is performed by the clock CK0, and the gate drive of the PMOS transistor MP4 is performed by the drain output of the preceding NMOS transistor MN1 by slightly modifying FIG. It is the one. The configuration principle of this booster circuit is disclosed in Japanese Patent Laid-Open No. 51-90416.

[0012]

In the booster circuits of FIGS. 7 and 8, when the gates of the NMOS transistors MN1 and MN2 are at VSS, a voltage of 2 VDD is applied between their gates and drains. Further, when the PMOS transistor MP3 is turned on to transfer the charge of the capacitor C1 to the capacitor C2, the PMOS transistor M3
A voltage of 2 VDD is still applied between the drain and gate of P3. For example, in an LSI with VDD = 3V, the element is extremely miniaturized, the gate oxide film is thin, and the gate breakdown voltage is about 5V. I will not drip. Making the gate oxide film thick only in the transistors to which these high voltages are applied causes a high cost.

The present invention has been made in consideration of the above circumstances, and it is possible to obtain a boosted voltage without causing a voltage drop corresponding to a threshold value, and realize high reliability without increasing a cost. It is intended to provide a booster circuit.

[0014]

SUMMARY OF THE INVENTION A booster circuit according to the present invention comprises, firstly, (a) a capacitor having first and second terminals, a first terminal supplied with a first clock; , A first p-channel MO whose source is connected to the second terminal of the capacitor and whose drain is connected to the high potential side terminal of the power supply.
An S-transistor and a second p-channel transistor whose source is connected to the second terminal of the capacitor, whose gate is connected to the high-potential side terminal of the power source, and whose drain is connected to the gate of the first p-channel MOS transistor. A channel MOS transistor and a first n-channel MOS transistor whose gate is supplied with a second clock whose phase is inverted from that of the first clock and whose source is connected to the low potential side terminal of the power source A second n connected to the high potential side terminal of the power supply, a drain connected to the drain of the second p-channel MOS transistor, and a source connected to the drain of the first n-channel MOS transistor.
A first boosted clock generation circuit having a channel MOS transistor, which obtains a first boosted clock obtained by level-shifting the first clock at a second terminal of the capacitor; and (b) the first boosted clock. A second boost clock generation circuit having a configuration similar to that of the generation circuit, the second boost clock generation circuit obtaining a second boost clock that is phase-inverted from the first boost clock; and (c) the first boost clock obtained. A third p-channel MOS transistor in which the drain is connected to the second terminal of the capacitor, the source is connected to the boosted voltage output terminal, and the gate is supplied with the second boosted clock obtained from the second boosted clock generation circuit. It is characterized by having and.

Secondly, the booster circuit according to the present invention comprises:
(A) A capacitor having first and second terminals, the first clock being supplied to the first terminal, a source connected to the second terminal of the capacitor, and a drain on the low potential side of the power supply. A first n-channel MOS transistor connected to the terminal, a source connected to the second terminal of the capacitor, a gate connected to the high potential side terminal of the power supply, and a drain connected to the first n-channel MOS transistor A second n-channel MOS transistor connected to the gate of the first clock and a second clock whose phase is inverted from that of the first clock are supplied to the gate, and the source is connected to the high potential side terminal of the power supply. 1 p-channel MOS transistor, the gate is connected to the low potential side terminal of the power source, the drain is connected to the drain of the second n-channel MOS transistor, There the first p-channel MOS
A first boosted clock generation circuit having a second p-channel MOS transistor connected to the drain of the transistor, and obtaining a first boosted clock obtained by level-shifting the first clock to the second terminal of the capacitor. When,
(B) a second boost clock generation circuit that has a configuration similar to that of the first boost clock generation circuit, and that obtains a second boost clock that is phase-inverted from the first boost clock;
(C) A drain connected to the second terminal of the capacitor from which the first boost clock is obtained, a source connected to the boost voltage output terminal, and a second gate obtained from the second boost clock generation circuit at the gate. And a third n-channel MOS transistor to which the boosting clock is applied.

[0016]

In the booster circuit of the first invention, like the booster circuit of FIG. 7, the first boosted clock generation circuit has a high potential side terminal (hereinafter VDD) of the clock-controlled capacitor. Charging from the side terminal) using the first PMOS transistor to obtain the first boost clock at the second terminal of the capacitor. 3rd from this boost clock
A boosted voltage of 2 VDD can be obtained by using the PMOS transistor of. If these first and third PMOS transistors are of a normal E type, that is, the threshold value is negative (or zero), there is no threshold voltage drop for positive voltage transfer by these transistors. Also, the first P
First NMOS for controlling gate of MOS transistor
Between the transistor and the second PMOS transistor,
A second NMOS transistor whose gate is supplied with VDD is interposed. This prevents a voltage higher than VDD from being applied between the drain and the gate of the first NMOS transistor when it is turned off.

On the other hand, the third PMOS for extracting the boosted voltage
A second boost clock generation circuit having a configuration similar to that of the first boost clock generation circuit for generating a second boost clock having a phase opposite to that of the first boost clock generation circuit for driving the gate of the transistor is provided. The second boosting clock is applied to the gate of the third PMOS transistor. As a result, it is possible to prevent a voltage exceeding VDD from being applied between the drain and gate of the third PMOS transistor. From the above, without using a thick gate oxide film for some of the transistors used,
It is possible to obtain sufficient reliability.

Contrary to the booster circuit according to the first aspect of the invention, the booster circuit according to the second aspect of the invention uses the capacitor charging by the low potential side terminal of the power source (hereinafter referred to as the VSS side terminal) in the negative direction. One that obtains doubled boosted voltage, that is, VSS
In the case of = 0V, the voltage -VDD is obtained,
The booster circuit according to the first aspect of the present invention has a completely complementary structure in which the transistors of the respective parts are of opposite conductivity type and the power supply relationship is reversed. In this case as well, a boosted voltage that does not drop by the threshold value can be obtained, and high reliability can be obtained without increasing the cost.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a booster circuit according to an embodiment of the present invention. E type PMOS transistor MP10 and E
Type NMOS transistor MN10 CMOS
The inverter 1 is provided to generate a complementary clock CK1 from the input clock CK0. First and second boosted clock generation circuits 2 and 3 are provided to obtain boosted clocks obtained by level-shifting these clocks CK0 and CK1 in the positive direction.

The first boosted clock generation circuit 2 obtains a first boosted clock obtained by level-shifting the first clock CK1, and the first clock CK1 is the first terminal N1.
Is connected to the VDD terminal through the E-type first PMOS transistor MP11 for charging the capacitor. The drain of the PMOS transistor MP11 is on the VDD side, and the source and the bulk are common to the second terminal side N2.
Connected to. The source and the bulk of the E-type second PMOS transistor MP12 are also connected to the second terminal N2 of the capacitor C1.
The gate of P12 is connected to the VDD terminal.

In order to control the gate of the first PMOS transistor MP11 for charging the capacitor, the second clock CK0 is input to the gate and the E-type first NMOS transistor MN11 whose source is connected to the VSS terminal is connected. It is provided. Between the drain of the NMOS transistor MN11 and the drain of the second PMOS transistor MP12, an E-type second NMOS transistor MN is provided.
12 are intervening. This NMOS transistor MN12
Has its gate connected to the VDD terminal. These NMOS
The bulks of the transistors MN11 and MN12 are commonly connected to VSS.

The second boost clock generation circuit 3 has the same structure as the first boost clock generation circuit 2. That is,
The capacitor C3 corresponds to the capacitor C1
PMO corresponding to each of the transistors MP11 and MP12
S-transistors MP14 and MP15 are provided, and NMOS transistors corresponding to the NMOS transistors MN11 and MN12, respectively.
Transistors MN13 and MN14 are provided. The second boost clock generation circuit 3 has a clock CK that is in a phase opposite to that of the first boost clock generation circuit 2.
0 and CK1 are given. As a result, with respect to the first boosting clock obtained at the terminal N2 of the first boosting clock generating circuit 2, the second boosting clock having the opposite phase can be obtained at the corresponding terminal N6.

In order to extract a constant boosted voltage output from the first boosted clock obtained by the first boosted clock generation circuit 2, the second terminal N2 and the output terminal N of the capacitor C1 are output.
3 between E-type third PMOS transistor MP
13 are inserted. This PMOS transistor MP13
Has a drain on the side of the second terminal N2 of the capacitor C1, and a source and a bulk are commonly connected to the output terminal N3. The gate of this PMOS transistor MP13 has a second voltage obtained at the terminal N6 of the second boost clock generation circuit 3.
The boost clock of is given. A capacitor C2 for holding the boosted voltage is provided at the output terminal.

The operation of the booster circuit thus constructed will be described below. First PM when clock CK0 is "H"
VDD is applied to the capacitor C1 through the OS transistor MP11.
Is charged and the clock CK0 becomes "L", 2VDD is obtained at the second terminal N2 of the capacitor C1 and at the same time, the third PMOS transistor MP13 is turned on,
The charge is transferred from the capacitor C1 to the capacitor C2 at the output end. The basic operation is the same as that of the booster circuit shown in FIG.

FIG. 2 shows the voltage waveform of each part in the steady state of the circuit in the case of VDD = 3V. The operation in the steady state will be specifically described as follows. First
Focusing on the boost clock generation circuit 2 side of
When K0 is "H" and therefore clock CK1 is "L",
The first NMOS transistor MN11 is turned on and the second NMOS transistor MN11 is turned on.
Since the NMOS transistor MN12 is always turned on with VDD given to its gate, the terminal N4 becomes "L". This turns on the first PMOS transistor MP11 and turns off the second PMOS transistor MP12.

At this time, the first terminal N of the capacitor C1
Since 1 is "L" (= Vss), the capacitor C1 is charged with VDD through the first PMOS transistor MP11. In the charging operation by the first PMOS transistor MP11, since the threshold value is negative, unlike the conventional case where the diode-connected NMOS transistor is used, a voltage drop corresponding to the threshold value does not occur.

On the other hand, on the side of the second boost clock generation circuit 3, before the clock half cycle, by the same operation as that of the first boost clock generation circuit 2 described above, VDD is applied to the capacitor C3.
Is charged, and the terminal N while the clock CK0 is "H"
Boosted clock 2VDD is obtained at 6, and this is the third PM
It is given to the gate of the OS transistor MP13. Therefore, the third PMOS transistor MP13 is off while the clock CK0 is "L".

Then, when the clock CK0 becomes "L", the clock CK1 becomes "H", that is, VDD is given to the first terminal N1 of the capacitor C1, and therefore the second terminal N2.
Is boosted to 2 VDD. At this time, on the side of the first boost clock generation circuit 2, the first NMOS transistor MN11 is turned off, the terminal N4 is turned to "H", the second PMOS transistor MP12 is turned on, and the first PMOS transistor MP11 is turned on. It is turned off and no charge flows to the VDD terminal.

At this time, the terminal N6 on the side of the second boost clock generating circuit 3 is in the charging cycle and is VDD, which is supplied to the gate of the third PMOS transistor MP13. In the steady state, the output capacitor C2 is already charged with 2V DD, so the third PMOS transistor MP13 is turned on, and the capacitor C1 outputs the P
The charges are transferred to the capacitor C2 via the MOS transistor MP13. By repeating the above operation, a constant boosted voltage 2VDD is obtained in the capacitor C2. Even in the charge transfer operation by the third PMOS transistor MP13, the voltage drop by the threshold value does not occur.

In the above operation, the first NMOS transistor MN11 for controlling the on / off of the first PMOS transistor MP11 and the third PM for extracting the boosted voltage.
No high voltage is applied to the OS transistor MP13 as in the conventional case. This will be described below. As shown in FIG. 2, the terminal N2 has V
A boosted clock level-shifted from DD to 2 VDD can be obtained. When the clock CK0 is "L" and the first NMOS transistor MN11 is turned off, the second PMOS transistor MP12 is turned on and its drain-side terminal N
4 goes up to 2 VDD as shown in FIG.

However, the second NMOS transistor MN
Reference numeral 12 has its gate supplied with VDD, and its source-side terminal N5 can only rise to VDD-Vth, where Vth is the threshold value of the second NMOS transistor MN12.
Therefore, the gate of the first NMOS transistor MN11
No voltage higher than VDD-Vth is applied between the drains.

Next, a third PMO for extracting the boosted voltage
Looking at the S-transistor MP13, as shown in FIG. 2, the first boosting clock of VDD to 2VDD obtained at the terminal N2 is applied to the drain, and the gate is opposite to the first boosting clock obtained at the terminal N6. A second boost clock of the phase, varying between VDD and 2VDD, is provided. Therefore,
No voltage exceeding VDD is applied between the drain and gate of the third PMOS transistor MP13. With respect to the transistors other than these, no voltage exceeding VDD is applied to the gate oxide film.

As described above, according to this embodiment, it is possible to obtain a boosted voltage without a voltage drop corresponding to the threshold value of the transistor. Moreover, since a voltage higher than VDD is not applied to the gate oxide film of the transistor used, it is not necessary to form a device having a particularly thick gate oxide film, and therefore a sufficiently high reliability is obtained without increasing the cost. be able to. By arranging a plurality of stages based on the circuit shown in FIG. 1, it is possible to obtain a voltage of arbitrary boosting ratio such as 3 times or 4 times.

FIG. 3 shows a booster circuit according to another embodiment of the present invention. Contrary to the embodiment of FIG. 1, this booster circuit is an example of obtaining a boosted voltage obtained by doubling the power supply voltage to the VSS side, that is, a boosted voltage of -VDD. The first boosting clock generation circuit 2 and the second boosting clock generation circuit 3 have a completely complementary configuration to the embodiment of FIG. That is, the first, second and third PMOS transistors MP11, MP1
2, 1st, 2nd and 3rd N corresponding to MP13
MOS transistors MN21, MN22, MN23 are provided. The drain and N of the NMOS transistor MN21
The gate of the MOS transistor MN23 is connected to the VSS terminal.

Further, the first and second NMOS transistors MN11 and MN12 of FIG.
PMOS transistors MP23 and MP24 are provided. The source of the PMOS transistor MP23 is connected to the VDD terminal.

The operation waveforms of the booster circuit of this embodiment in the steady state are shown in FIG. 4 in correspondence with FIG. In brief, in this embodiment, when the clock CK0 is "L", the first PMOS transistor MP21 is turned on and the first NMOS transistor MN21 is turned on, so that the capacitor C1 has the first terminal N1. Is VDD, second
The terminal N2 is charged to VSS. At this time, since the threshold value of the first NMOS transistor MN21 is positive, no voltage drop occurs during the transfer of VSS through the first NMOS transistor MN21.

When the clock CK0 becomes "H", -VDD is obtained at the second terminal N2 of the capacitor C1. At the same time, the first NMOS transistor MN21 is turned off and the third NMOS transistor MN21 is turned off.
Since the MOS transistor MN22 is on, the charge of the second terminal N2 is transferred to the capacitor C2 at the output end.
Also at this time, there is no voltage drop due to the third NMOS transistor MN23. By repeating the above operation, -VDD
A boosted voltage is obtained. Also in this embodiment, the same effect as in the previous embodiment can be obtained.

[0038]

As described above, according to the present invention, the PMOS transistor is used for charging VDD to the capacitor and transferring the voltage boosted to the VDD side, while conversely charging VSS and boosting the voltage to the VSS side. By using an NMOS transistor for voltage transfer, a boosted voltage can be obtained without causing a voltage drop corresponding to a threshold value, and an excessive boosted voltage is not applied to the gate oxide film of the transistor used. Therefore, it is possible to obtain a booster circuit that realizes high reliability without increasing cost.

[Brief description of drawings]

FIG. 1 shows a booster circuit according to an embodiment of the present invention.

FIG. 2 shows operation waveforms of the booster circuit according to the embodiment.

FIG. 3 shows a booster circuit according to another embodiment of the present invention.

FIG. 4 shows operation waveforms of the booster circuit of the embodiment.

FIG. 5 shows a conventional booster circuit.

FIG. 6 shows a conventional booster circuit.

FIG. 7 shows a conventional booster circuit.

FIG. 8 shows a conventional booster circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CMOS inverter, 2 ... 1st step-up clock generation circuit, 3 ... 2nd step-up clock generation circuit, C1, C2
C3 ... Capacitor, MP11 ... First PMOS transistor, MP12 ... Second PMOS transistor, MP13 ... Third PMOS transistor, MN11 ... First NMOS transistor, MN12 ... Second NMOS transistor, M
N21 ... first NMOS transistor, MN22 ... second N
MOS transistor, MN23 ... Third NMOS transistor, MP21 ... First PMOS transistor, MP22 ...
Second PMOS transistor.

Claims (2)

[Claims] 1. (a) A capacitor having first and second terminals, a first clock being supplied to the first terminal, a source connected to a second terminal of the capacitor, and a drain A first p-channel MOS transistor connected to the high potential side terminal of the power supply, a source connected to the second terminal of the capacitor, a gate connected to the high potential side terminal of the power supply, and a drain of the first A second p-channel MOS transistor connected to the gate of the p-channel MOS transistor, and a second clock whose phase is inverted from that of the first clock are supplied to the gate, and the source is the low potential side terminal of the power supply. A first n-channel MOS transistor connected to the power source, a gate connected to the high potential side terminal of the power source, and a drain connected to the drain of the second p-channel MOS transistor. Is connected, a second n-channel MO having a source connected to a drain of said first n-channel MOS transistor
A first boost clock generation circuit having an S-transistor to obtain a first boost clock generated by level-shifting the first clock at a second terminal of the capacitor; and (b) the first boost clock generation circuit. A second boost clock generation circuit that has a configuration similar to that of the circuit, and that obtains a second boost clock that is a phase inversion of the first boost clock; and (c) the capacitor that obtains the first boost clock. A third p-channel MOS transistor having a drain connected to the second terminal, a source connected to the boosted voltage output terminal, and a gate to which the second boosted clock obtained from the second boosted clock generation circuit is applied. A booster circuit comprising: 2. (a) A capacitor having first and second terminals, a first clock being supplied to the first terminal, a source connected to a second terminal of the capacitor, and a drain A first n-channel MOS transistor connected to the low potential side terminal of the power supply, a source connected to the second terminal of the capacitor, a gate connected to the high potential side terminal of the power supply, and a drain of the first A second n-channel MOS transistor connected to the gate of the n-channel MOS transistor, and a second clock whose phase is inverted from that of the first clock are supplied to the gate, and the source is a high potential side terminal of the power supply. A first p-channel MOS transistor connected to the second power supply, a gate connected to a low potential side terminal of the power supply, and a drain connected to the drain of the second n-channel MOS transistor. Is connected, a second p-channel MO having a source connected to the drain of said first p-channel MOS transistor
A first boost clock generation circuit having an S-transistor to obtain a first boost clock generated by level-shifting the first clock at a second terminal of the capacitor; and (b) the first boost clock generation circuit. A second boost clock generation circuit that has a configuration similar to that of the circuit, and that obtains a second boost clock that is a phase inversion of the first boost clock; and (c) the capacitor that obtains the first boost clock. A third n-channel MOS transistor to which a drain is connected to the second terminal, a source is connected to the boosted voltage output terminal, and a second boosted clock obtained from the second boosted clock generation circuit is applied to the gate. A booster circuit comprising: