306055 A7 _B7 五、發明説明（1 ) 發明背景 發明領域_ 本發明關於L S I積體電路所用的升壓電路。 習知技藝_ 依據L S I積體電路（簡稱L S I電路）的近來趨勢 ，以相小結構製造電子元件而使集積度較高。歸因於此趨 勢，施於積體電路的源電壓從（傳流使用的）5 V降到3 V »至於利用3V/5V混合源電壓的一些LS I電路， 須提供3 V - 5 V介面電路。爲實現此介面電路，須提供 5 V外部電源。但若L S I電路不能從外部電源接收5 V 源電壓，則須在L S I電路內提供升壓電路，以產生5 V 源電壓。 經濟部中央標準局員工消費合作社印製 習知升壓電路的基本組態顯示於圖5 »圖5的此升壓 電路包括電容器C及以二極體連接形式互連的一對n通道 MOS電晶體Ml和M2。由時脈組成的時脈信號CK送 到電容器C的一端子。對應於時脈信號〜L <位準的期間 中，電源VDD經由MO S電晶體Μ 1對電容器C充電。對 應於時脈信號' Η >位準的期間中，MOS電晶體Ml關 閉，因而升壓電路經由MOS電晶體M2輸出Vcc升壓（ 其中 V cc= 2 V DD)。 圖6的多級升壓電路使用圖5的升壓電路做爲單級。 圖5的升壓電路輸出升壓Vcc，僅爲VDD之原來源電壓的 二倍，易言之，圖5之升壓電路的倍率爲' 2 >。但圈6 一 4 - (請先閲讀背面之注意事項再填寫本頁) 本紙张尺度逋用中國國家標準（CNS )八4規格（2丨0Χ297公釐） A7 B7 經濟部中央標準局員工消费合作杜印製 五、發明説明（ 2 ) 1 I 的 多 級 升 壓 電路 可輸 出 倍 率不 限於 2 而 任 意 .設 定 的 升 1 壓 e 多 級 升 壓電 路需 要 2 種時 脈信 號 » 亦 即 反 相 的 φ 1 和 1 Ψ 2 〇 1 I 闉 5 的 升壓 電路 中 ♦ 壓降 會因 Μ 0 S 電 晶 體 臨 限 值 請 先 閱 1 V *t h 而 發 生 在電 容器 C 的 充電 電壓 和 升 壓 V CC ° 所 以 不 讀 背 1 1 I 能 得 到 二 倍 電壓 〜2 V D Ε ，做 爲升 壓 V C C 〇 爲 避 免 上 述 臨 之 注 意 1 1 I 限 值 所 造 成 的電 壓損 失 » 另一 種升 壓 電 路 提 出 如 m.7 〇 曰 事 項 1 I 再 本 特 許 公 開 5 2 -3 9 1 19 揭示 圖 7 之 升 壓 電 路 構 造 的 填 % 本 裝 原 理 〇 頁 '--- 1 1 圖 7 中 ，提 供由 Ρ 通 道Μ 0 S 電 晶 體 ( 下 文 稱 爲 1 1 P Μ 0 S 電 晶體 和η 通 道 MO S電 晶 體 ( 下 文 稱 爲 1 I N Μ 〇 S 電 晶體 )組 成 的 反相 電路 〇 此 反 相 電 產 生 與 原 時 1 訂 | 脈 信 m C Κ 0反 相的 反 時 脈信 號C Κ 1 〇 時 脈 信 號 C Κ 1 1 1 送 到 電 容 器 C 1 的第 一 端 子。 電容 器 C 1 的 第 二 端 子 經 由 1 1 P Μ 〇 S 電 晶體 Μ Ρ 1 接 到電 源V D D 0 Ρ Μ 〇 S 電 晶 體 1 1 Μ Ρ 1 中 汲殛 接到 電 源 V 〇〇 ，而 源 極 接 到 電 容 器 C 1 0 k I N Μ 〇 S電 晶體 Μ Ν 1中 ，源 極 接 地 V S S » 而 閘 極 接 1 I 收 時 脈 信 號 C Κ 0。 Ν Μ 0 S 電晶 體 Μ Ν 1 的 汲 極 接 到 1 1 I Ρ Μ 0 S 電 晶體 Μ Ρ 1 的 閘極 。P Μ 0 S 電 晶 體 IUZ. Μ Ρ 2 插 1 1 在 Ν Μ 〇 S 電晶 體Μ Ν 1 的汲 極與 電 容 器 C 1 的 第 二 端 子 1 1 之 間 9 Ρ Μ 0 S 電晶 體 rise. Μ P 2 中， 汲 極 接 到 Ν Μ 〇 S 電 晶 1 體 Μ Ν 1 的 汲極 ，而 閘 極 接到 電源 V D D 〇 1 | Ρ Μ 0 S電 晶體 Μ Ρ 3設 在電 容 器 C 1 的 第 二 端 子 與 1 I 提 供 升 壓 Υ c c的 輸出 端 子 、0 U 丁 之 間 0 Ρ Μ 0 S 電 晶 1 1 1 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X 297公釐） -5 - 306055 B7 經濟部中央樣準局貝工消费合作社印製 五、發明説明（ 3 ) \ 1 | 體 Μ Ρ 3 抽 取 升 壓 V c c ,» 其 中 其 汲 極 接 到 零 容 器 C 1 的 第 1 二 端 子 〇 爲 選 擇 性 驅 動 Ρ Μ 0 S 電 晶 體 Μ Ρ 3 9 提 供 分 別 1 連 接 Ν Μ 0 S 電 晶 體 Μ Ν 1 和 Ρ Μ 0 S 電 晶 體 ELS. Μ Ρ 2 的 請 先 閲 1 I N Μ 0 S 電 晶 體 Μ N 2 和 Ρ Μ 0 S 電 晶 體 Μ Ρ 4 0 原 時 脈 1 信 號 C Κ 0 用 來 驅 動 Ν Μ 0 S 電 晶 體 Ν Μ 1 的 閘 極 9 而 反 背 1 1 I 時 脈 信 號 C Κ 1 用 來 驅 動 Ν Μ 0 S 電 晶 體 Ν Μ 2 的 閛 極 〇 之 注 意 1 1 I 再 者 9 電 容 器 C 2 設 在 地 V S S 與輸 出 端 子 0 U Τ 之 間 以 輸 事 項 1 I 再 出 升 壓 V C C 〇 填 寫 本 裝 | 接 著 詳 述 圖 7 之 升 壓 電 路 的 運 作 〇 若 時 脈 信 號 頁 1 1 C Κ 0 在 Η 〆 位 準 ( 亦 即 c Κ 0 = Η ) 而 時 脈 信 1 號 C Κ 1 在 L 位 準 ( 亦 即 C Κ 1 = - L 〆 ) 則 1 1 N Μ 0 S 電 晶 體 Μ N 1 開 啓 因 而 汲 極 電 壓 降 低 〇 造 成 1 訂 I P Μ 0 S 電 晶 體 Μ P 1 開 啓 » 所 以 電 源 V D D 對 電 容 器 1 1 I C 1 充 電 0 此 時 4uf. 搬 壓 降 發 生 在 Ρ Μ 〇 S 電 晶 腊 Μ Ρ 1 〇 1 1 因 此 充 電 電 壓 可 增 達 V D D ο 另 — 方 面 Ν Μ 0 S 電 晶 體 1 1 Μ Ρ 2 關 閉 t 所 以 Ρ Μ 0 S 竜 晶 體 Μ Ρ 3 關 閉 〇 ’丨 若 C Κ 0 = L 且 C Κ 1 Η 則 電 容 器 C 1 1 I 的 第 二 端 子 暫 時 增 爲 2 V D D 電 壓 〇 同 時 Ν Μ 0 S 電 晶 體 1 1 I Μ Ν 1 關 閉 而 Ρ Μ 0 S 電 晶 體 Μ Ρ 2 開 啓 〇 所 以 2 1 1 1 V D D 窜 壓 施 於 P Μ 〇 S 電 晶 體 Μ Ρ 1 的 閛 極 再 關 閉 〇 此 時 1 1 > Μ Μ 0 S 電 晶 體 ruz. Μ Ν 2 開 啓 而 Ρ Μ 〇 S 電 晶 體 Μ Ρ 3 1 開 啓 因 而 電 容 器 C 1 的 電 荷 轉 移 到 電 容 器 C 2 〇 在 此 情 1 1 形 黑 壓 降 發 生 在 Ρ Μ 0 S 電 晶 體 Μ Ρ 3 〇 I 其 後 重 複 上 述 運 作 因 而 可 得 V C C = 2 V D D 的 1 1 1 本紙張尺度適用中國國家揉率（CNS ) A4規格（21 OX297公釐） -6 - 經濟部中央樣準局貝工消費合作社印褽 A7 __________B7_ 五、發明説明（4 ) 恆升壓。 接著，稍修改圖7的升壓電路來設計圖8的升壓電路 。時脈信號CKO驅動PMO S電晶體MP 2的閘極，而 NMO S電晶體MN 1的汲極輸出驅動PMO S電晶體 MP4的閘極。日本特許公開5 1 — 9041 6揭示圖8 之升壓電路構造的原理。 若NMO S電晶體MN 1和MN 2的閘極設爲_地電壓 V ss，則2 V DD電壓施於NMO S電晶體MN 1和MN 2 的閘極與汲極之間。此外，當PMO S電晶體MP 3開啓 因而電容器C1的電荷轉移到電容器C2時，2V DD電壓 施於PMO S電晶體MP 3的汲極和閘極之間。在VDD = 3V之LSI電路的情形，電子元件的結構極小，因而閘 極氧化物膜必須薄。這令閘極電壓阻力約爲5 V。所以， 若'2 VDD= 6 V /電壓施於電晶體的閘極和汲極之間， 則此電壓會打破電晶體的電壓阻力》爲增加電晶體的電壓 阻力，應使施加此高壓的電晶體閘極氧化物膜厚。但造成 升壓電路的製造成本較高。 發明概要 本發明的目檩是提供能以高可靠度輸出升壓的升壓電 路，而不發生MO S電晶體臨限值所造成的壓降。 本發明的升壓電路使用反相電路以產生與輸入時脈信 號反相的互補時脈信號，及第一升壓時脈產生電路和第二 升壓時脈產生電路。第一升壓時脈產生電路接到第一電容 本紙張尺度逋用中國國家橾準（CNS ) Α4規格（210Χ 297公釐） ^1. - I - - - I —^1 In ^^1 an --- τ» U3-β (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（5 ) 器的第二端子（第一端子接收互補時脈信號）。此電路產 生與输入時脈信號反相且相較於输入時脈信號位準增加的 第一升壓時脈信號。第二升壓時脈產生電路接到第二電容 器的第二端子（第一端子接收輸入時脈信號）。此電路產 生相較於輸入時脈信號位準增加且與第一升壓時脈信號反 相的第二升壓時脈信號。第一和第二升壓時脈信號用來產 生相當於源電壓二倍的恆升壓。 . 第一和第二升壓時脈產生電路使用P通道和η通道 MO S電晶體。此處，MO S電晶體通常是臨限值爲負或 零的增強型MO S電晶體，因而臨限值所造成的壓降不發 生在升壓。此外，決定MO S電晶體的配置，使得高於源 電壓的高壓不施於MO S電晶體。因此，不需使用閘極氧 化物膜變厚以增加電壓阻力的特定MO S電晶體。 附帶一提，修改MO S電晶體配置和/或改變電源連 接，可任意改變升壓倍率。 圖式簡述 V圖1是顯示依據本發明第一實施例所設計之升壓電路 的電路圖； V圖2顯示在圖1之升壓電路之數點所測的電壓波形； 4 3是顯示依據本發明第二實施例所設計之升壓電路 的電路圖； \/圖4顯示在圖3之升壓電路之數點所測的電壓波形： V圖5是顯示習知升壓電路基本組態的電路圖； 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） — — — — — 裝—— —II 訂 In A (請先閲讀背面之注意事項再填寫本頁) -8 - 經濟部中央揉準局員工消費合作社印裝 A7 _______B7_ 五、發明説明（6 ) _ 6是顯示根據圖5之升壓電路所設計之習知多級升 壓電路的電路圖； 7是顯示另一種習知升壓電路的電路圖； j 8是顯示另一種習知升壓電路的電路圖。 較佳實施例說明 圖1是顯示依據本發明第一實施例所設計之升壓電路 的電路圖。提供由E型（亦即增強型）PMO S電晶體 MP 1 〇和E型NMOS電晶體MN1 〇組成的CMOS 反相電路1。反相電路1根據輸入時脈信號C K 〇產生互 補時脈信號C K 1 »爲得到相較於時脈信號c K 〇和 c K 1位準在正向偏移的升壓時脈信號，提供第一和第二 升壓時脈產生電路2和3。 第一升壓時脈產生電路2產生相較於互補時脈信號 C K 1位準偏移的第一升壓時脈信號。第一升壓時脈產生 電路2有電容器C1 ，其中第一端子N1接收互補時脈信 號CK 1 ，而第二端子N 2經由用於將電容器C 1充電的 E型第一 PMOS電晶體MP 1 1接到電源VDD。第一 PMO S電晶體MP 1 1中，汲極接到電源VDD，而源極 接到電容器C 1的第二端子N 2。電容器C 1的第二端子 N2也接到E型第二PMOS電晶體MP12的源極。第 二PMOS電晶體MP 1 2的閘極接到電源VDD。 爲對用於將電容器C 1充電的第一PMO S電晶體 MP 1 1進行閘極控制，提供E型第一 NMO S電晶體 本紙張尺度遑用中國國家橾準（CNS ) A4洗格（2丨0乂29：；公釐〉 — — — — — — 裝 I —II 訂 1 备 (請先閲讀背面之注意事項再填寫本頁) -9 - 經濟部中央樣準局貝工消費合作杜印製 A7 _ B7 _ 五、發明説明（7 ) MN1 1 ，其中閘極接收輸入時脈信號CKO，而源極接 地Vss»此外，E型第二NMOS電晶體MN1 2插在第 一NMOS電晶體MN11的汲極與第二PMOS電晶體 MP12的汲極之間。 第二升壓時脈產生電路3的組態具有上述第一升壓時 脈產生電路2的類似組態。亦即，電容器C 3對應於電容 器Cl ; PMOS電晶體MP14和MP15對應.於 PMOS電晶體MP 1 5對應於PMOS電晶體MP 1 1 和MP12;NMOS電晶體MN13和MN14對應於 NMOS電晶體Ml 1和MN1 2。第二升壓時脈產生電 路3之時脈信號C K 0和C K 1的供應方式與第一升壓時 脈產生電路2反相。因此，使出現在第二升壓時脈產生電 路3之端子N 6的第二升壓時脈信號與出現在第一升壓時 脈產生電路2之電容器C 1之第二端子N 2的第一升壓時 脈信號反相。 爲根據第一升壓時脈產生電路2所產生的第一升壓時 脈信號來抽取恆升壓，E型第三PMO S電晶體MP 1 3 插在圖1之電容器C 1的第二端子N 2與升壓電路的輸出 端子N3之間。第三PMOS電晶體MP 1 3中，汲極接 到電容器C 1的第二端子N 2，而源極接到輸出端子N 3 。此外，出現在第二升壓時脈產生電路3之端子N 6的第 二升壓時脈信號送到第三PMOS電晶體MP13的閘極 。再者，壓電變換器C 2在输出端子N 3輸出升壓Vcc。 接著*詳述圖1之升壓電路的運作。若输入時脈信號 本紙張尺度逋用中國國家揉準（CNS ) A4規格（210X 297公釐） ' -10 - I - (H —I- an 1 .. nn I m 、vs (請先閲讀背面之注意事項再填寫本頁) 3G6055 A7 ____B7_ 五、發明説明（8 ) CK〇的位準高（亦即CKO=、H>)，則使用電源 V DD由第一 PMOS電晶體MP 1 1對電容器C 1充電。 若輸入時脈信號CK0的位準低（亦即CK0 =、L 一） ，則在電容器C 1的第二端子N 2得到2 VDD電壓。同時 ’第三PMO S電晶體MP 1 3開啓，因而電容器C 1的 電荷轉移到電容器C 2。其基本運作類似圖6的上述升壓 電路。 圖2顯示在穩態之圖1之升壓電路數點的各種電壓波 形，其中源電壓VDD設爲3 V。接著，解釋在穩態下之升 壓電路的運作。 至於第一升壓時脈產生電路2，若CK0='H<因 而CK1=、L> ，則第一NMOS電晶體MN11開啓 ，而第二NMO S電晶體MN 1 2正常在Ο N狀態，這是 因爲其閘極接收源電壓VDD。所以，在晞子N 4的電壓位 準低（L)。因此，第一PMOS電晶體Μ P 1 1開啓， 而第二PMO S電晶體ΜΡ 1 2關閉。 在上述狀態，電容器C 1的第一端子Ν 1在對應於 經濟部中央標準局員工消費合作社印裳 (請先閲讀背面之注意事項再填寫本頁) V ss的低位準（L )。所以，使用電源V DD由第一P MOS電晶體ΜΡ11對電容器C1進行充電作業。有' 負>臨限值的第一PMOS電晶體ΜΡ11進行充電作業 。因此，相較於NMO S電晶體依據二極體連接法而連接 的傳統升壓電路，本實施例的升壓電路不發生臨限值所造 成的壓降。 如同第一升壓時脈產生電路2，在第二升壓時脈產生 本紙張尺度通用中國國家揉準（CNS ) A4规格（ 210 X297公釐） -11 - A7 B7 經濟部中央樣準局員工消费合作社印製 五、發明説明（ 9 ) 1 | 電 路 3， 使 用 電 源 V ο Ε ，對 電 容 器 C 3進 行充 電 作 業 〇 但 在 1 第 升壓 時 脈 產 生 電路 2 的 充 電 作 業之 前的 一 半 時 脈 周 期 1 1 進 行第 二 升 壓 時 脈產 生 電 路 3 的 充電 作業 〇 所 以 對 應 1 | 於 C Κ 0 = Η - 的期 間 中 在 端 子Ν 6得 到 2 V D Ε •電 壓 請 先 聞 1 0 此 電壓 送 到 第 二 Ρ Μ 0 S 電 晶 體 Μ Ρ 13 的 閘 極 〇 因 此 讀 背 Si 1 I > 對 應於 C Κ 1 = 、L 〆 的 期 間 中 ，第 三P Μ 0 S 電 晶 體 之 注 意 1 1 1 Μ Ρ 13 在 0 F F 狀態 〇 事 項 1 I 再 若C Κ 0 = L ^ 因 而 C Κ 1 =、 Η 一 則 源 電 壓 填 % 本 裝 1 V D D 施於 電 容 器 C 1的 第 — 端 子 Ν 1 ° 所以 在 電 容 器 C 頁 ___^ 1 1 1 之 第二 端 子 Ν 2 的電 壓 增 達 2 V D D電 壓。 此 時 第 一 升 1 1 壓 時 脈產 生 電 路 2 中， 第 一 Ν Μ 0 S電 晶體 Μ Ν 1 1 關 閉 1 > 因 而端 子 Ν 4 在 高位 準 ( Η ) 〇 因此 ，第 二 Ρ Μ 0 S 電 訂 I 晶 體 Μ Ρ 1 2 開 啓 ，而 第 — Ρ Μ 0 S電 晶體 Μ Ρ 1 1 關 閉 1 1 1 〇 因 此， 電 容 器 C 1的 電 荷 不 流 回 到電 源V D D 〇 1 1 在上 述 狀 態 第二 升 壓 時 脈 產 生電 路3 的 端 子 Ν 6 在 1 1 充 電 周期 因 而 端 子Ν 6 的 電 壓 相 當於 源電 壓 V D D 〇 此 電 Μ 1 壓 送 到第 三 Ρ Μ 〇 S電 晶 體 Μ Ρ 1 3的 閘極 〇 在 穩 態 電 1 | 容 器 C 2 已 被 2 V D D電 壓 充 電 〇 因 此， 第三 Ρ Μ 0 S 電 晶 1 I 體 Μ Ρ 1 3 開 啓 ， 因而 電 容 器 C 1 的電 荷經 由 第 三 1 1 Ρ Μ 0 S 電 晶 體 Μ Ρ 1 3 轉 移 到 電 容器 C 2 0 重 複 上 述 運 1 1 作 所以 SSSme 尾 容 器 C 2 可 得 到 2 V D D ® 升壓 〇 即 使 在 上 述 1 第 二 Ρ Μ 0 S 電 晶 體Μ Ρ 1 3 的 電 荷轉 移運 作 t 臨 限 值 所 1 1 造 成 的壓 降 也 不 會 發生 0 | 本實 施 例 的 升 壓電 路 異 於 傅 統 升壓 電路 • 上 述 運 作 中 1 1 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X297公釐） -12 - 306055 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（ 10) 1 | ， 高 壓不施 於用 來控制 第一 Ρ Μ 0 S 電 晶 體 ΠΪ2. Μ Ρ 1 1 之 1 1 〇 N /OF F狀 態的第 一 Ν Μ 〇 S 電 晶 體 Μ Ν 1 1 ; 同 樣 1 I 地 » 髙壓不 施於 用來抽 取升 壓 的 第 Ρ Μ 0 S 電 晶 體 Μ Ρ 1 | 請 1 1 3 〇 先 1 聞 以下說 明高 壓不施 於第 --- Ν Μ 〇 S 電 晶 體 •Μ Ν 1 1 的 請 背 1 έ I 原 因 0 之 注 1 | 意 I 圖2顯 示相 較於位 準在 V S S 和 V D D 之 間 變 化 的 時 脈 信 事 項 1 I 再 1 號 9 位準在 V D D 與2 V D D之 間 變 化 的 第 _. 升 壓 時 脈 信 號 出 填 寫 本 裝 I 現 在 電容器 C 1 的第二 端子 Ν 2 〇 第 — 升 壓 時 脈 信 號 的 位 頁 1 | 準 高 於時脈 信號 。若C Κ 0 = L - 而 第 一 Ν Μ 0 S 電 晶 1 I 體 Μ S 1 1 關閉 ，則第 二 Ρ Μ 0 S 電 晶 體 Μ Ρ 1 2 開 啓 ♦ 1 1 | 因 而 接到第 二 P Μ 0 S 電晶 體 Μ Ρ 1 2 之 汲 極 之 端 子 Ν 4 1 訂 的 電 壓位準 增達 "2 V D D ( 見 圖 2 ) 〇 1 1 另一方 面， 源電壓 V d D 施 於 第 二 Ν U 0 S 電 晶 體 Μ Ν 1 1 1 2 的閘極 :接 到第二 Ν Μ 0 S 電 晶 體 Μ Ν 1 2 源 極 之 端 1 1 子 Ν 5的電 壓位 準不能 髙於 V D D — V t h 〆 其 中 V t h 劣. 1 代 表第二 Ν Μ 0 S電 晶體 Μ Ν 1 2 的 臨 限 值 〇 這 表 示 1¾ 1 1 I 於 V D D ~ V th /的高 壓不 施 於 第 一 Ν Μ 0 S 電 晶 體 Μ Ν I 1 I 1 1 的閘極 和汲 極之間 〇 1 1 接著， 以下 說明高 壓不 施 於 用 來 抽 取 升 壓 之 第 二 1 1 P Μ 0 S電 晶體 Μ Ρ 1 3的 原 因 〇 1 如前述 ，位 準在V Cb3 DD與 2 V D D 之 間 變 化 的 第 —- 升 壓 時 1 1 脈 信 號出現 在端 子Ν 2 (見 圖 2 ) ; 此 第 — 升 壓 時 脈 信 號 1 •1 | 送 到 第三P Μ 0 S電晶 體Μ Ρ 1 3 的 汲 極 〇 另 一 方 面 > 位 1 1 1 本紙張尺度逋用中國國家揉準（CNS ) A4规格（210 X 297公釐） -13 _ A7 B7 五、發明説明（11) 準在V DD與2 v DD之間變化的第二升壓時脈信號出現在端 子N 6。第二升壓時脈信號與第一升壓時脈信號反相。此 第二升壓時脈信號送到第三PMOS電晶體MP13的閘 極。這表示位準超過~ VDDe的高壓不施於第三PMO S 電晶體Μ P 1 3的汲極和閘極之間。同樣地，位準超過、 的高壓不送到升壓電路的其它電晶體。易言之，高 壓不施於升壓電路的電晶體閘極氧化物膜。 依據本實施例，可得到不被電晶體臨限值降低的升壓 。此外，高於V DD的高壓不施於用在升壓電路的電晶體閘 極氧化物膜。所以，不需提供閘極氧化物膜厚的電子元件 。易言之，升壓電路製造成本不增加，在升壓電路運作可 .得到高可靠度》 附帶一提，對應於圖1之升壓電路的升壓電路組合一 起，形成多級升壓電路。此多級升壓電略中，可得到升壓 的任意倍率，可設定髙於輸入電壓的3倍或4倍。 經濟部中央標隼局貝工消費合作社印製 I:—. ^^1 I - - . I In - I - ^ 11« —I— n i -- - i I- ------- (請先閲讀背面之注意事項再填寫本頁) 圖3是顯示依據本發明第二實施例所設計之升壓電路 的電路圖，其中相當於圖1的組件由相同數字代表。圖3 的升壓電路的組態有些與圖1的上述升壓電路相反。圖3 的升壓電路產生' -VDD>升壓。相較於圖1的升壓電路 ，電源V DD和地V ss的施加在圖3的升壓電路相反。如同 圖1的升壓電路，圖3的升壓電路含有反相電路1 1 、第 —升壓時脈產生電路1 2、第二升壓時脈產生電路1 3。 圖3的反相電路11類似圖1的反相電路1;但數字改變 而使MOS電晶體MP 2 0和MN2 0取代MOS電晶體 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐} '~ -14 - A7 · B7 經濟部中央標隼局員工消费合作社印製 五、 發明説明（12) 1 I Μ P 1 0 和Μ Ν 1 0 ο 圖3之電 路 1 2 和 1 3 的 組態 與 圖 1 1 之 電 路 2和 3的 組 態 互捕。相 較 於 圖 1 的 升 壓 電路 t 1 1 Ρ Μ 0 S 電晶 體Μ Ρ 1 1 、Μ Ρ 1 2 > Μ Ρ 1 3 分別 被 圖 1 I 請 1 3 之 升 壓 電路 的Ν Μ 0 S電晶體 Μ Ν 2 1 Μ Ν 2 2 、 先 閲 1 I Μ Ν 2 3 取代 。Ν Μ 0 S電晶體 Μ Ν 2 .1 的 汲 極 和 讀 背 Λ 1 1 | Ν Μ 0 S 電晶 體Μ Ν 2 2的閘極 接 地 V S S 〇 之 洼 意 1 1 I 圖 3 的Ρ MO S 電 晶體Μ Ν 2 1 和 Μ 2 2 取 代圖 1 的 事 項 1 I 再 1 Ν Μ 0 S 電晶 體Μ Ν 1 1和Μ Ν 1 2 〇 Ρ Μ 0 S 電晶 體 填 窝 袈 Μ Ρ 2 1 的源 極接 到 電 源 V dd。 頁 1 1 相 較 於圖 1的 第 二 升壓時脈 產 生 電 路 3 Ρ Μ 0 S 電 1 | 晶 體 Μ Ρ 14 和Μ Ρ 1 5被圖3 的 Ν Μ 0 S 電 晶 體Μ N 1 1 2 4 和 Μ Ν 2 5取 代 而Ν Μ 0 S 電 晶 體 Μ Ν 1 3和 訂 | Μ Ν 1 4 被Ρ Μ 0 S 電 晶體Μ Ρ 2 3 和 Μ Ρ 2 4 取代 〇 此 1 1 外 圖 3 的端 子Ν 1 1 至Ν 1 8 取 代 pm 圖 1 的 端 子 Ν 1 至 1 Ν 8 〇 1 1 接 著 ，詳 述圖 3 之 升壓電路 的 運 作 ο 在 圖 3 之升 壓 電 r I 路 數 圖 的 電壓 波形 顯 示 在對應於 圖 2 的 圖 4 0 若 C Κ 0 = 1 I L - » 則Ρ Μ 0 S 電 晶體Μ Ρ 2 1 開 啓 而 Ν Μ 0 S 電 1 1 I 晶 體 |UL Μ Ν 2 1 開啓 〇 因 此，若源 電 壓 V D D 施 於 第 —端 子 1 1 I Ν 1 1 t 而地 電壓 V S S 施於第二 端 子 N 1 2 » 則 對電 容 器 1 1 C 1 進 行 充電 作業 0 在 此情形， Ν Μ 0 S 電 晶 體 Μ Ν 2 1 1 1 有 正 臨 限 值。 所以 t 將 地電壓V S S 轉 移 到 電 容 器 Cl 之 第 I 二 端 子 N 12 的Ν Μ 〇 S電晶體 Μ Ν 2 1 不 造 成 壓降 0 I 若 C Κ 〇 Η ，則、- V D D 40 電 壓 出 現 在電 容 器 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15 - A7 B7 五、發明説明（IS) C 1的第二端子N2。同時，NMOS電晶體MN 2 1關 閉，而NMO S電晶體MN 2 3開啓。因此’電容器C 1 的電荷經由NMO S電晶體MN 2 3轉移到電容器C 2 ° 此時，NMOS電晶體MN2 3不造成懕降。 重複上述運作，在圓3之升壓電路的輸出端子N 1 3 可得到、_ V DD >升壓。 簡言之，第二實施例可提供上述第一實施例的.相同效 果。 由於發明範疇是由申請專利範圍而非上文來界定’故 本發明能以數個形式來實施而不悖離主要特徵的精神’因 此本實施例是說明而非限制。 I— I n I r^*衣 I I 訂—— H Μ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局属工消费合作社印製 本紙張尺度逋用中固國家榡準（CNS ) Α4洗格（210X 297公釐） 16 -306055 A7 _B7 V. Description of the invention (1) Background of the invention Field of the invention _ The present invention relates to a booster circuit used in an L S I integrated circuit. Conventional skills _ According to the recent trend of L S I integrated circuits (referred to as L S I circuits), electronic components are manufactured with a relatively small structure to achieve a high degree of accumulation. Due to this trend, the source voltage applied to the integrated circuit is reduced from 5 V (used for current transmission) to 3 V »As for some LS I circuits that use a mixed source voltage of 3V / 5V, a 3 V-5 V interface must be provided Circuit. To implement this interface circuit, a 5 V external power supply must be provided. However, if the L S I circuit cannot receive a 5 V source voltage from an external power source, a boost circuit must be provided in the L S I circuit to generate a 5 V source voltage. The basic configuration of the conventional booster circuit printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is shown in Fig. 5 And M2. The clock signal CK composed of clocks is sent to a terminal of the capacitor C. During the period corresponding to the clock signal ~ L < level, the power supply VDD charges the capacitor C via the MOS transistor M1. During the period corresponding to the clock signal 'H > level, the MOS transistor M1 is turned off, so the boost circuit outputs Vcc boost via the MOS transistor M2 (where V cc = 2 V DD). The multi-stage booster circuit of FIG. 6 uses the booster circuit of FIG. 5 as a single stage. The boost circuit of FIG. 5 outputs boosted Vcc, which is only twice the original source voltage of VDD. In other words, the boost circuit of FIG. 5 has a magnification of '2 >. But the circle 6 1 4-(please read the precautions on the back before filling in this page) This paper uses the Chinese National Standard (CNS) 84 specifications (2 丨 0Χ297mm) A7 B7 Employee consumption cooperation of the Central Standards Bureau of the Ministry of Economic Affairs Du Yinzhuang 5. Description of invention (2) The multi-stage booster circuit of 1 I can output at any rate not limited to 2 but arbitrary. The set multiplier booster circuit for boosting 1 pressure e requires 2 kinds of clock signals »that is, inverting φ 1 and 1 Ψ 2 〇1 I 闉 5 in the booster circuit ♦ The voltage drop will be due to the threshold of Μ 0 S transistor. Please read 1 V * th and the charging voltage and boost V CC ° So without reading back 1 1 I can get twice the voltage ~ 2 VD Ε as a boosted VCC. To avoid the above-mentioned attention to the voltage loss caused by the 1 1 I limit »Another boost circuit is proposed as m.7 〇Issue 1 I Republished Patent Publication 5 2 -3 9 1 19 Reveals the structure of the booster circuit of FIG. 7 Principle 〇 page '--- 1 1 In Figure 7, the P channel MOS transistor (hereinafter referred to as 1 1 P MOS transistor and η channel MO S transistor (hereinafter referred to as 1 IN Μ 〇S Inverter circuit composed of transistors. This inverted electricity generates an order with the original time 1 | pulse signal m C Κ 0 inverse clock signal C Κ 1 〇 clock signal C Κ 1 1 1 sent to the capacitor C 1 The first terminal of the capacitor C. The second terminal of the capacitor C 1 is connected to the power supply VDD 0 Ρ Μ 〇S transistor 1 1 Μ Ρ 1 via the 1 1 P Μ 〇S transistor Μ Ρ 1 connected to the power supply V 〇〇, The source is connected to the capacitor C 10 k IN MOS transistor MN 1, the source is grounded VSS »and the gate is connected to 1 I to receive the clock signal C K 0. The drain of the transistor MN 1 is connected to the gate of the transistor 1 Μ Ρ 1. P Μ 0 S transistor IUZ. Μ Ρ 2 inserted 1 1 between the drain of Ν Μ 〇S transistor Μ Ν 1 and the second terminal 1 1 of capacitor C 1 9 Ρ Μ 0 S transistor rise. Μ P In 2, the drain is connected to the drain of Ν Μ〇S transistor 1 body Μ Ν 1, and the gate is connected to the power supply VDD 〇1 | Ρ Μ 0 S transistor Μ Ρ 3 is provided in the second terminal of the capacitor C 1 Between 1 I and the output terminal that provides boost Υ cc, 0 U D, 0 Ρ Μ 0 S transistor 1 1 1 This paper size is applicable to China National Standards (CNS) A4 specification (210X 297 mm) -5-306055 B7 Printed by Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (3) \ 1 | Body Μ Ρ 3 extracts the boost V cc, »where its drain is connected to the first two terminals of the zero container C 1 〇 To selectively drive P Μ 0 S transistor Μ Ρ 3 9 to provide 1 connection Ν Μ 0 S transistor Μ Ν 1 and Ρ Μ 0 S transistor ELS. For Μ Ρ 2 please read 1 IN Μ 0 S transistor Μ N 2 and Ρ Μ 0 S transistors The body ΜΡ 4 0 original clock 1 signal C Κ 0 is used to drive the gate of Ν Μ 0 S transistor Ν Μ 1 and the reverse 1 1 I clock signal C Κ 1 is used to drive Ν Μ 0 S transistor Note of the N poles of Ν Μ 2 1 1 I and 9 The capacitor C 2 is placed between the ground VSS and the output terminal 0 U Τ with the input item 1 I and then the boosted VCC. Fill in this package | Next, detailed description of FIG. 7 The operation of the booster circuit. If the clock signal page 1 1 C Κ 0 is at Η 〆 level (ie c Κ 0 = Η) and the clock signal No. 1 C Κ 1 is at L level (ie C Κ 1 =-L 〆) Then 1 1 N M 0 S transistor M N 1 is turned on and the drain voltage is reduced. This causes 1 order IP M 0 S transistor M P 1 is turned on »so the power supply VDD charges the capacitor 1 1 IC 1 0 this时 4uf. The voltage drop occurs at P Μ 〇S electric crystal wax Μ Ρ 1 〇1 1 so the charging voltage can be increased to VDD ο Another-aspects Ν Μ 0 S electricity Body 1 1 Μ Ρ 2 is closed t so Μ Μ 0 S 竜 晶 Μ Ρ 3 is closed. If C Κ 0 = L and C Κ 1 Η, the second terminal of the capacitor C 1 1 I temporarily increases to 2 VDD voltage. At the same time, Ν Μ 0 S transistor 1 1 I Μ Ν 1 is turned off and Ρ Μ 0 S transistor Μ Ρ 2 is turned on. So 2 1 1 1 VDD channeling voltage is applied to P Μ 〇S transistor Μ Ρ 1's prong and then closed 〇 At this time 1 1 > Μ Μ 0 S transistor ruz. Μ Ν 2 is turned on and Ρ Μ 〇S transistor Μ Ρ 3 1 is turned on so that the charge of the capacitor C 1 is transferred to the capacitor C 2 〇 In this case 1 1 black The pressure drop occurs at Ρ Μ 0 S transistor Μ Ρ 3 〇I and then repeat the above operation so that VCC = 2 VDD of 1 1 1 This paper scale is applicable to the Chinese national rubbing rate (CNS) A4 specification (21 OX297 mm) -6-Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed A7 __________B7_ V. Description of the invention (4) Constant boost. Next, the boost circuit of FIG. 7 is slightly modified to design the boost circuit of FIG. 8. Clock signal CKO drives the gate of PMOS transistor MP 2 and the drain output of NMOS transistor MN 1 drives the gate of PMOS transistor MP4. Japanese Patent Publication 5 1 — 9041 6 discloses the principle of the construction of the boost circuit of FIG. 8. If the gates of the NMOS transistors MN 1 and MN 2 are set to _ground voltage V ss, a 2 V DD voltage is applied between the gates and the drains of the NMOS transistors MN 1 and MN 2. In addition, when the PMOS transistor MP3 is turned on and the charge of the capacitor C1 is transferred to the capacitor C2, a 2V DD voltage is applied between the drain and gate of the PMOS transistor MP3. In the case of an LSI circuit with VDD = 3V, the structure of the electronic component is extremely small, so the gate oxide film must be thin. This makes the gate voltage resistance approximately 5 V. Therefore, if '2 VDD = 6 V / voltage is applied between the gate and the drain of the transistor, this voltage will break the voltage resistance of the transistor. "In order to increase the voltage resistance of the transistor, the voltage of this high voltage should be applied. The thickness of the crystal gate oxide film. However, the manufacturing cost of the booster circuit is higher. SUMMARY OF THE INVENTION The object of the present invention is to provide a boost circuit capable of outputting boost with high reliability without occurrence of voltage drop caused by the threshold of the MOS transistor. The booster circuit of the present invention uses an inverting circuit to generate a complementary clock signal that is inverse to the input clock signal, and a first boosting clock generating circuit and a second boosting clock generating circuit. The first step-up clock generation circuit is connected to the first capacitor. The paper size is based on the Chinese National Standard (CNS) Α4 specification (210Χ 297 mm) ^ 1.-I---I — ^ 1 In ^^ 1 an --- τ »U3-β (Please read the precautions on the back before filling in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention Description (5) The second terminal of the device (the first terminal receives Complementary clock signal). This circuit generates a first boosted clock signal that is inverse to the input clock signal and has an increased level compared to the input clock signal. The second boost clock generation circuit is connected to the second terminal of the second capacitor (the first terminal receives the input clock signal). This circuit generates a second boosted clock signal that increases in level compared to the input clock signal and is inverse to the first boosted clock signal. The first and second boost clock signals are used to generate a constant boost equivalent to twice the source voltage. The first and second boost clock generation circuits use P-channel and n-channel MOS transistors. Here, the MO S transistor is usually an enhanced MO S transistor with a negative or zero threshold, so the voltage drop caused by the threshold does not occur in the boost. In addition, the configuration of the MOS transistor is determined so that the high voltage higher than the source voltage is not applied to the MOS transistor. Therefore, it is not necessary to use a specific MOS transistor whose gate oxide film is thickened to increase the voltage resistance. Incidentally, by modifying the configuration of the MO S transistor and / or changing the power connection, the boost ratio can be changed arbitrarily. BRIEF DESCRIPTION OF THE DRAWINGS V FIG. 1 is a circuit diagram showing a booster circuit designed according to the first embodiment of the present invention; V FIG. 2 shows a voltage waveform measured at several points of the booster circuit of FIG. 1; 4 3 is a display basis The circuit diagram of the booster circuit designed in the second embodiment of the present invention; \ / FIG. 4 shows the voltage waveforms measured at several points of the booster circuit in FIG. This paper scale is applicable to China National Standard (CNS) A4 specification (210X 297mm) — — — — — Packing — — II Order In A (please read the precautions on the back before filling out this page) -8-Central Ministry of Economic Affairs Printed and printed on A7 by the Consumer Cooperative of the Ministry of Accreditation. V. Invention description (6) _ 6 is a circuit diagram showing a conventional multi-stage booster circuit designed according to the booster circuit of FIG. 5; 7 is a circuit diagram showing another conventional booster circuit ; J 8 is a circuit diagram showing another conventional boost circuit. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a circuit diagram showing a booster circuit designed according to the first embodiment of the present invention. A CMOS inverter circuit 1 composed of an E-type (ie enhanced) PMOS transistor MP 1 〇 and an E-type NMOS transistor MN1 〇 is provided. The inverter circuit 1 generates a complementary clock signal CK 1 »according to the input clock signal CK 〇 In order to obtain a boosted clock signal that is shifted in the forward direction compared to the clock signals c K 〇 and c K 1, it provides the first One and second boost clock generation circuits 2 and 3. The first step-up clock generation circuit 2 generates a first step-up clock signal whose level is shifted compared to the complementary clock signal C K 1. The first boost clock generation circuit 2 has a capacitor C1, wherein the first terminal N1 receives a complementary clock signal CK1, and the second terminal N2 is via an E-type first PMOS transistor MP1 for charging the capacitor C1 1 Connect to the power supply VDD. In the first PMOS transistor MP 1 1, the drain is connected to the power supply VDD, and the source is connected to the second terminal N 2 of the capacitor C 1. The second terminal N2 of the capacitor C1 is also connected to the source of the E-type second PMOS transistor MP12. The gate of the second PMOS transistor MP 1 2 is connected to the power supply VDD. In order to control the gate of the first PMOS transistor MP 1 1 used to charge the capacitor C 1, the E-type first NMO S transistor is provided. The paper size is not in accordance with the Chinese National Standard (CNS) A4 (2丨 0 乂 29:; mm> — — — — — — Pack I —II Order 1 (please read the notes on the back before filling out this page) -9-Dumplings of Beige Consumption Cooperation of the Central Bureau of Samples of the Ministry of Economic Affairs System A7 _ B7 _ 5. Description of the invention (7) MN1 1, where the gate receives the input clock signal CKO, and the source is grounded Vss »In addition, the E-type second NMOS transistor MN1 2 is inserted in the first NMOS transistor MN11 Between the drain of the second PMOS transistor MP12 and the drain of the second PMOS transistor MP12. The configuration of the second boost clock generation circuit 3 has a similar configuration as the first boost pulse generation circuit 2 described above. That is, the capacitor C 3 Corresponds to capacitor C1; PMOS transistors MP14 and MP15 correspond. PMOS transistors MP 15 correspond to PMOS transistors MP 1 1 and MP12; NMOS transistors MN13 and MN14 correspond to NMOS transistors Ml 1 and MN1 2. Second The supply mode of the clock signals CK 0 and CK 1 of the boost clock generation circuit 3 is inverse to that of the first boost clock generation circuit 2 Therefore, the second boost clock signal appearing at the terminal N 6 of the second boost clock generating circuit 3 and the second terminal N 2 appearing at the capacitor C 1 of the first boost clock generating circuit 2 The first boost clock signal is inverted. To extract the constant boost according to the first boost clock signal generated by the first boost clock generation circuit 2, the E-type third PMOS transistor MP 1 3 is inserted in 1 between the second terminal N 2 of the capacitor C 1 and the output terminal N 3 of the booster circuit. In the third PMOS transistor MP 1 3, the drain is connected to the second terminal N 2 of the capacitor C 1, and the source It is connected to the output terminal N3. In addition, the second boosted clock signal appearing at the terminal N6 of the second boosted clock generation circuit 3 is sent to the gate of the third PMOS transistor MP13. Furthermore, piezoelectric conversion The C 2 outputs the boosted Vcc at the output terminal N 3. Then * details the operation of the boost circuit shown in Figure 1. If the clock signal is input, the paper size is based on the Chinese National Standard (CNS) A4 specification (210X 297 mm ) '-10-I-(H —I- an 1 .. nn I m, vs (please read the precautions on the back before filling this page) 3G6055 A7 ____B7_ V. Invention (8) The level of CK〇 is high (that is, CKO =, H>), then the power supply V DD is used to charge the capacitor C 1 from the first PMOS transistor MP 1 1. If the level of the input clock signal CK0 is low (That is, CK0 =, L1), then a 2 VDD voltage is obtained at the second terminal N 2 of the capacitor C 1. At the same time, the third PMOS transistor MP 1 3 is turned on, so that the charge of the capacitor C 1 is transferred to the capacitor C 2. The basic operation is similar to the boost circuit shown in Fig. 6 above. Fig. 2 shows various voltage waveforms at several points of the booster circuit of Fig. 1 in a steady state, in which the source voltage VDD is set to 3 V. Next, the operation of the boost circuit in steady state is explained. As for the first boost clock generation circuit 2, if CK0 = 'H < thus CK1 =, L >, then the first NMOS transistor MN11 is turned on, and the second NMOS transistor MN 1 2 is normally in the ON state, which This is because its gate receives the source voltage VDD. Therefore, the voltage level at S4 is low (L). Therefore, the first PMOS transistor MP 1 1 is turned on, and the second PMOS transistor MP 1 2 is turned off. In the above-mentioned state, the first terminal Ν 1 of the capacitor C 1 is printed corresponding to the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) V ss low level (L). Therefore, the capacitor C1 is charged by the first P MOS transistor MP11 using the power supply V DD. The first negative PMOS transistor MP11 with 'negative> threshold performs charging operation. Therefore, compared to the conventional booster circuit in which NMOS transistors are connected in accordance with the diode connection method, the booster circuit of this embodiment does not experience a voltage drop caused by the threshold. Like the first step-up clock generation circuit 2, the paper standard is generated at the second step-up clock according to the Chinese National Standard (CNS) A4 specification (210 X297 mm) -11-A7 B7 Employee of the Central Sample Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative V. Description of the invention (9) 1 | Circuit 3, using the power supply V ο Ε, to charge the capacitor C 3 〇 But half the clock cycle before the charging operation of the first step-up clock generation circuit 2 1 1 Perform the charging operation of the second step-up clock generation circuit 3. Therefore, it corresponds to 1 | During the period of C Κ 0 = Η-2 VD is obtained at the terminal N 6 • The voltage should be heard first 1 0 This voltage is sent to the first The gate of the second P Μ 0 S transistor Μ Ρ 13 so read back Si 1 I > during the period corresponding to C Κ 1 =, L 〆, the attention of the third P Μ 0 S transistor 1 1 1 Μ Ρ 13 In the 0 FF state 〇 Matter 1 I If C Κ 0 = L ^ so C Κ 1 =, Η a source voltage is filled% V D D is applied to the first terminal Ν 1 ° of the capacitor C 1. Therefore, the voltage at the second terminal Ν 2 of the capacitor C page ___ ^ 1 1 1 increases to a voltage of 2 V D D. At this time, in the first rising 1 1 pressure clock generation circuit 2, the first N M 0 S transistor M N 1 1 is turned off 1 > thus the terminal N 4 is at a high level (H). Therefore, the second P M 0 S Electric order I crystal Μ Ρ 1 2 is turned on, and the first — Ρ Μ 0 S transistor Μ Ρ 1 1 is turned off 1 1 1 〇 Therefore, the charge of the capacitor C 1 does not flow back to the power supply VDD 〇1 1 in the above state second rise The terminal N 6 of the clock generation circuit 3 is charged at 1 1, so the voltage of the terminal N 6 is equivalent to the source voltage VDD. This electric M 1 is sent to the gate of the third P M 0 S transistor M P 1 3. In the steady state 1 | the container C 2 has been charged by the 2 VDD voltage. Therefore, the third P Μ 0 S transistor 1 I body Μ Ρ 1 3 is turned on, so the charge of the capacitor C 1 passes through the third 1 1 Ρ Μ 0 S Transistor Μ Ρ 1 3 transferred to capacitor C 2 0 Repeat the above operation 1 1 so the SSSme tail container C 2 can get 2 VDD ® boost. Even in the above 1 The charge transfer operation of the second P MOS transistor Μ Ρ 1 3 t will not cause a voltage drop caused by the threshold 1 1 | The boost circuit of this embodiment is different from the conventional boost circuit • The above operation 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X297 mm) -12-306055 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention Instructions (10) 1 |, high pressure is not applied To control the first Μ Μο S transistor ΠΪ2. Μ Ρ 1 1 1 1 〇N / OF F state of the first Ν Μ 〇S transistor Μ Ν 1 1; the same 1 I place »high pressure is not applied To extract the boosted P Μ 0 S transistor Μ Ρ 1 | please 1 1 3 〇 first 1 heard the following instructions high pressure is not applied to the first --- Ν Μ 〇S transistor • Μ Ν 1 1 please back 1 έ I Reason 0 Note 1 | Italian I Figure 2 shows the VSS and V compared to the level The clock signal items that change between DD 1 I and the 9th level of the No. 1 change between VDD and 2 VDD. The boost clock signal is filled out. The second terminal Ν 2 of the capacitor C 1 is present. Page — Bit 1 of the boost clock signal is higher than the clock signal. If C Κ 0 = L-and the first Ν Μ 0 S transistor 1 I body Μ S 1 1 is closed, then the second Ρ Μ 0 S transistor Μ Ρ 1 2 is turned on 1 1 | thus received the second P Μ 0 S Transistor Μ Ρ 1 2 The drain terminal Ν 4 1 sets the voltage level up to " 2 VDD (see FIG. 2) 〇1 1 On the other hand, the source voltage V d D is applied to the second NU 0 S transistor Μ Ν 1 1 1 2 gate: connected to the second Ν Μ 0 S transistor Μ Ν 1 2 source terminal 1 1 sub-N 5 voltage level cannot be higher than VDD-V th 〆 V th is inferior. 1 represents the threshold value of the second Ν Μ 0 S transistor Μ Ν 1 2 〇 This means that 1 ¾ 1 1 I VDD ~ V th / high voltage is not applied to the first Ν Μ 0 S transistor Μ Ν Between the gate and the drain of I 1 I 1 1 〇1 1 Next, the following explains the reason why the high voltage is not applied to the second 1 1 P MOS transistor Μ Ρ 1 3 used to extract boost. 〇1 As mentioned above , The level changes between V Cb3 DD and 2 VDD The 1 1 pulse signal appears at the terminal N 2 (see Figure 2); this first — the boost pulse signal 1 • 1 | is sent to the drain of the third P MOS transistor Μ Ρ 1 3. On the other hand > Bits 1 1 1 This paper scale uses the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -13 _ A7 B7 5. Description of the invention (11) The standard varies between V DD and 2 v DD The second boost clock signal appears at terminal N 6. The second boost clock signal is inverse to the first boost clock signal. This second boost clock signal is sent to the gate of the third PMOS transistor MP13. This means that the high voltage exceeding ~ VDDe is not applied between the drain and gate of the third PMOS transistor M P 1 3. In the same way, the high voltage exceeding the level is not sent to other transistors of the booster circuit. In other words, high voltage is not applied to the transistor gate oxide film of the booster circuit. According to this embodiment, it is possible to obtain a boosted voltage that is not reduced by the threshold of the transistor. In addition, the high voltage higher than V DD is not applied to the transistor gate oxide film used in the booster circuit. Therefore, there is no need to provide electronic components with a thick gate oxide film. In short, the manufacturing cost of the booster circuit does not increase, and high reliability can be obtained during the operation of the booster circuit. Incidentally, the booster circuit corresponding to the booster circuit of FIG. 1 is combined to form a multi-stage booster circuit. In this multi-stage booster strategy, any boosting rate can be obtained, which can be set to 3 times or 4 times the input voltage. Printed by the Beigong Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs I: —. ^^ 1 I--. I In-I-^ 11 «—I— ni--i I- ------- (please (Read the precautions on the back before filling this page.) FIG. 3 is a circuit diagram showing a booster circuit designed according to the second embodiment of the present invention, in which the components corresponding to FIG. 1 are represented by the same numbers. The configuration of the booster circuit of FIG. 3 is somewhat opposite to that of the booster circuit of FIG. 1. The boost circuit of Figure 3 generates' -VDD> boost. Compared to the boost circuit of FIG. 1, the power supply V DD and the ground V ss are applied to the boost circuit of FIG. 3 in reverse. Like the booster circuit of FIG. 1, the booster circuit of FIG. 3 includes an inverter circuit 1 1, a first boost clock generation circuit 1 2, and a second boost clock generation circuit 13. The inverting circuit 11 of FIG. 3 is similar to the inverting circuit 1 of FIG. 1; however, the numbers change to replace the MOS transistors MP 2 0 and MN2 0 with MOS transistors. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm } '~ -14-A7 · B7 Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economy V. Description of the invention (12) 1 I Μ P 1 0 and Μ Ν 1 0 ο Circuit group 1 2 and 1 3 of Figure 3 State and the configuration of circuits 2 and 3 of Fig. 1 1. The boost circuit t 1 1 Ρ Μ 0 S transistors Μ Ρ 1 1, Μ Ρ 1 2 > Μ Ρ 1 3 respectively It is replaced by the NM MOS transistor Μ Ν 2 1 Μ Ν 2 2 of the boost circuit of FIG. 1 I 1 3, the first reading 1 I Μ Ν 2 3. The Ν Μ 0 S transistor Μ Ν 2.1. Pole and read back Λ 1 1 | The gate ground of Ν Μ 0 S transistor Μ Ν 2 2 VSS 〇 The meaning of 1 1 I PMOS transistors Μ Ν 2 1 and Μ 2 2 of FIG. 3 replace FIG. 1 Matter 1 I then 1 Ν Μ 0 S transistor Μ Ν 1 1 and Μ Ν 1 2 〇Ρ Μ 0 S transistor filling The source of the loop Μ Ρ 2 1 is connected to the power supply V dd. Page 1 1 Compared to the second step-up clock generation circuit 3 of FIG. 1 3 Ρ Μ 0 S electrical 1 | crystal Μ Ρ 14 and Μ Ρ 1 5 are shown 3 Ν Μ 0 S transistors Μ N 1 1 2 4 and Μ Ν 2 5 substitution and Ν Μ 0 S transistor Μ Ν 1 3 and set | Μ Ν 1 4 is Μ Μ 0 S transistor Μ Ρ 2 3 and M Ρ 2 4 replaces this 1 1. In addition, the terminals N 1 1 to N 1 8 of FIG. 3 replace pm The terminals N 1 to 1 of FIG. 1. N 8 〇1 1 Next, the operation of the booster circuit of FIG. 3 is described in detail. The voltage waveform of the boost voltage r I channel number diagram of FIG. 3 is shown in FIG. 4 corresponding to FIG. 2 0. If C Κ 0 = 1 IL-»then Μ Μ 0 S transistor Μ Ρ 2 1 is turned on and Ν Μ 0 S electricity 1 1 I crystal | UL Μ Ν 2 1 is turned on. Therefore, if the source voltage VDD is applied to the first terminal 1 1 I Ν 1 1 t and the ground voltage VSS is applied to the second terminal N 1 2 », then the capacitor 1 1 C 1 Perform charging operation 0 In this case, Ν Μ 0 S transistor Μ Ν 2 1 1 1 has a positive threshold. So t transfers the ground voltage VSS to the NMMOS transistor MN2 1 of the second terminal N12 of the capacitor Cl does not cause a voltage drop. If C Κ 〇Η, then, -VDD 40 voltage appears in the capacitor 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -15-A7 B7 V. Description of the invention (IS) C 1 second terminal N2. At the same time, the NMOS transistor MN 2 1 is turned off, and the NMOS transistor MN 2 3 is turned on. Therefore, the charge of the capacitor C 1 is transferred to the capacitor C 2 via the NMOS transistor MN 2 3. At this time, the NMOS transistor MN2 3 does not cause a collapse. Repeating the above operation, the output terminal N 1 3 of the booster circuit of circle 3 can be boosted by _V DD >. In short, the second embodiment can provide the same effects as the first embodiment described above. Since the scope of the invention is defined by the scope of patent application rather than the above, the present invention can be implemented in several forms without departing from the spirit of the main features. Therefore, this embodiment is illustrative rather than limiting. I— I n I r ^ * Cloth II Order——H Μ (Please read the precautions on the back before filling in this page) The paper scale printed by the Industrial and Consumer Cooperatives of the Central Bureau of Industry and Commerce of the Ministry of Economic Affairs is used in the national standard of China. (CNS) Α4 wash grid (210X 297mm) 16-