JPH0322483A - Thin-film transistor - Google Patents

Thin-film transistor

Info

Publication number
JPH0322483A
JPH0322483A JP15753789A JP15753789A JPH0322483A JP H0322483 A JPH0322483 A JP H0322483A JP 15753789 A JP15753789 A JP 15753789A JP 15753789 A JP15753789 A JP 15753789A JP H0322483 A JPH0322483 A JP H0322483A
Authority
JP
Japan
Prior art keywords
film
gate
voltage
ferroelectric
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15753789A
Other languages
Japanese (ja)
Other versions
JP2855663B2 (en
Inventor
Kenichi Yanai
梁井 健一
Tsutomu Tanaka
勉 田中
Kenichi Oki
沖 賢一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1157537A priority Critical patent/JP2855663B2/en
Publication of JPH0322483A publication Critical patent/JPH0322483A/en
Application granted granted Critical
Publication of JP2855663B2 publication Critical patent/JP2855663B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To enable realization of a sufficiently low OFF current being necessary for holding data, even when a gate bias is zero, by making a gate insulation film contain a ferroelectric film. CONSTITUTION:Inside an operating semiconductor layer 5, an electric field directed toward a gate insulation film 2 is generated, a spontaneous polarization P0<-> is formed and an energy band for electrons is put in a state being equivalent to the one wherein a negative gate voltage is impressed in a conventional TFT structure. In an address period when data are written in, on the other side, a positive voltage being equivalent to Ec or above is impressed on a gate, the direction of the electric field is reversed and the state of a ferroelectric film P0<+> is brought about. Therefore the energy band is put in a reverse state of storage and TFT is set in an ON operation. As for a concrete method of formation, a Ti film to be a gate electrode 1 is formed on a glass substrate 11 by a sputtering method. Next, a PbTiO3 film as the ferroelectric film is formed by a vacuum evaporation method. Subsequently, a silicon nitride film 4 and an a-Si:H film 5 as the operating semiconductor layer is formed by a plasma CVD method. Moreover, an n<+> a-Si:H film 6 as a contact layer and a Ti film 7 as a metal film are stacked and patterned, so as to form a source electrode S and a drain electrode D.

Description

【発明の詳細な説明】 〔概 要〕 液晶駆動用薄膜トランジスタの構造に関し、闇値電圧を
正の電圧とすることができる薄膜トランジスタの新規な
構造を提供することを目的とし、 ゲート電極と動作半導体層との間に介在するゲート絶縁
膜を、強誘電体膜を含む絶縁膜とした構或とする。
[Detailed Description of the Invention] [Summary] Regarding the structure of a thin film transistor for driving a liquid crystal, an object of the present invention is to provide a novel structure of a thin film transistor that can make the dark voltage a positive voltage. The gate insulating film interposed between the gate insulating film and the gate insulating film is an insulating film including a ferroelectric film.

〔産業上の利用分野〕[Industrial application field]

本発明は、液晶駆動用薄膜トランジスタ(TPT)の構
造に関する。
The present invention relates to the structure of a thin film transistor (TPT) for driving a liquid crystal.

TPT駆動液晶ディスプレイは、大容量で鮮明なフルカ
ラー表示が行なえることから、OA端末などのフラット
ディスプレイとして現在盛んに開発が行なわれている。
TPT-driven liquid crystal displays are currently being actively developed as flat displays for office automation terminals and the like because they have a large capacity and can display clear, full-color displays.

〔従来の技術〕[Conventional technology]

TPT駆動の液晶表示装置では、各画素ごとにTPTを
配設することを要するため、製造工程が複雑となり、そ
の結果、製造歩留りやスループットが低くなるなどの問
題があった。
In TPT-driven liquid crystal display devices, it is necessary to provide a TPT for each pixel, which complicates the manufacturing process, resulting in problems such as low manufacturing yield and throughput.

この問題を解決するために、TPTをマトリクス状に配
列するTPT基板上で、バスラインのクロスオーバーを
原理的に皆無としたゲート接続方式対向マトリクス型の
薄膜トランジスタマトリクスを、本発明者らは特願昭6
1−212696号.特願昭61−212697号その
他で提案した。
In order to solve this problem, the present inventors have applied for a patent application to develop a gate-connected opposed matrix type thin film transistor matrix that has no bus line crossover in principle, on a TPT substrate in which TPTs are arranged in a matrix. Showa 6
No. 1-212696. This was proposed in Japanese Patent Application No. 61-212697 and elsewhere.

第7図は上記ゲート接続方式の薄膜トランジスタマトリ
クスの等価回路図であって、図示したよう、薄膜トラン
ジスタT+ ,T2は、ゲートがそれぞれスキャンハス
ラインSn,Sn+1に接続され、ドレインはスキャン
バスラインS n+1, S n+2に接続されている
FIG. 7 is an equivalent circuit diagram of the thin film transistor matrix of the gate connection method, and as shown, the gates of the thin film transistors T+ and T2 are connected to the scan line Sn and Sn+1, respectively, and the drains are connected to the scan line Sn and Sn+1, respectively. Connected to S n+2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従ってこの方式では、データを保持する非選択期間には
、非選択スキャンバスラインの電位がすべて同電位とな
るため、非選択スキャンバスライン上の薄膜トランジス
タはすべて、ゲート電圧■6とドレイン電圧■ゎが同じ
電圧となる。そのためTPT特性として、ゲートバイア
スが0の状態で、オフ電流値が充分低くなることが必要
となる。
Therefore, in this method, during the non-selection period during which data is retained, all the potentials of the non-selected scan canvas lines are at the same potential, so that all the thin film transistors on the non-selected scan canvas lines have the gate voltage 6 and the drain voltage 2 have the same voltage. Therefore, as a TPT characteristic, it is necessary that the off-state current value be sufficiently low when the gate bias is 0.

なお、同図のLCは液晶セル、VSはソース電圧、Dm
,Dm+1はデータバスラインである。
In addition, in the same figure, LC is a liquid crystal cell, VS is a source voltage, and Dm
, Dm+1 are data bus lines.

実際の薄膜トランジスタマトリクスで、上記要請を実現
するのは必ずしも容易とは言いがたい。
It cannot be said that it is necessarily easy to realize the above requirements with an actual thin film transistor matrix.

そこで、薄膜トランジスタマトリクスの闇値電圧を、目
的に応じて正または負方向にシフトし得ることが望まし
い。
Therefore, it is desirable to be able to shift the dark voltage of the thin film transistor matrix in the positive or negative direction depending on the purpose.

本発明は上記要請に鑑み、闇値電圧を正の電圧とするこ
とができる薄膜トランジスタの新規な構造を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION In view of the above-mentioned requirements, an object of the present invention is to provide a novel structure of a thin film transistor in which the dark voltage can be set to a positive voltage.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は第1図に示すように、薄膜トランジスタのゲー
ト絶縁膜2を、強誘電体膜を含む膜とした。
In the present invention, as shown in FIG. 1, the gate insulating film 2 of the thin film transistor is a film containing a ferroelectric film.

例えば、動作半導体層5を水素化アモルファスシリコン
(a −S i : H)膜とした場合、ゲート絶縁膜
2をSiN(窒化シリコン)膜と強誘電体膜との二層膜
とし、動作半導体層5との界面特性の良好なSiN(窒
化シリコン)膜を動作半導体3 4 層5側に、強誘電体膜をゲート電極1に接する側に配設
する。
For example, when the active semiconductor layer 5 is a hydrogenated amorphous silicon (a-Si:H) film, the gate insulating film 2 is a two-layer film of a SiN (silicon nitride) film and a ferroelectric film, and the active semiconductor layer A SiN (silicon nitride) film having good interface characteristics with the active semiconductor 3 4 layer 5 is provided on the side of the active semiconductor 3 4 layer 5 , and a ferroelectric film is provided on the side in contact with the gate electrode 1 .

動作半導体層5は上述のように一方の主面はゲート絶縁
膜2に接し、他方の主面にはn” a−Si層のような
コンタクト層6と金属膜7が積層されて、ソース電極S
およびドレイン電極Dが形威されている点は、従来と何
ら変わりはない。
As described above, one main surface of the active semiconductor layer 5 is in contact with the gate insulating film 2, and the other main surface is laminated with a contact layer 6 such as an n'' a-Si layer and a metal film 7, forming a source electrode. S
There is no difference from the conventional method in that the drain electrode D is formed.

〔作 用〕[For production]

第2図は強誘電体の周知のメモリー作用を示す図であっ
て、横軸は外部から印加される電界、縦軸は自発分極P
である。すなわち、外部から印加される電圧が0の時、
強誘電体は2つの状態P。″″とP0−をとることがで
き、どちらの状態をとるかは、その前に印加される電界
の履歴によることになる。負の臨界電圧Ec一以下の電
圧を印加した後電圧を上昇した場合には経路Aを、正の
臨界電圧Ec”を印加した後電圧を下降させた場合には
、経路Bを通り、ヒステリシスを描く。
Figure 2 is a diagram showing the well-known memory effect of ferroelectric materials, where the horizontal axis is the externally applied electric field and the vertical axis is the spontaneous polarization P.
It is. In other words, when the externally applied voltage is 0,
A ferroelectric substance has two states P. ``'' and P0-, and which state is taken depends on the history of the electric field applied before. If the voltage is increased after applying a voltage equal to or less than the negative critical voltage Ec, route A is used, and if the voltage is lowered after applying a positive critical voltage Ec, route B is routed to avoid hysteresis. draw.

本発明はこれを利用したものであって、TPT駆動のた
めにゲートに印加される基本的な電圧波形を、第3図に
示すように、データを保持する非選択期間の直前に、E
c一以上に相当する負の電圧を印加しておき、非選択期
間中強誘電体の状態がP.−となるようにする。
The present invention takes advantage of this, and as shown in FIG. 3, the basic voltage waveform applied to the gate for TPT driving is changed to E
A negative voltage corresponding to c1 or more is applied, and the state of the ferroelectric substance is P.during the non-selection period. −.

このように駆動した時の本発明の動作原理を、第4図に
より説明する。
The operating principle of the present invention when driven in this manner will be explained with reference to FIG.

即ち、a ivf=Qの関係より、動作半導体層5内部
には、ゲート絶縁膜2に向かう電界ができる。そのため
同図(a)に示すような自発分極P1が形威され、電子
に対するエネルギバンドは、(+))に示すように上側
に曲がる空乏状態、即ち通常のTPT構造で負のゲート
電圧が印加されたのと等価な状態となる。
That is, due to the relationship a ivf=Q, an electric field directed toward the gate insulating film 2 is generated inside the active semiconductor layer 5 . Therefore, a spontaneous polarization P1 as shown in the figure (a) is formed, and the energy band for electrons is a depletion state that curves upward as shown in (+), that is, when a negative gate voltage is applied in a normal TPT structure. The state is equivalent to that of

一方データを書き込むアドレス期間には、Ec以上に相
当する正の電圧がゲートに印加され、電界の向きが反対
となって、い)に示すように強誘電体膜はP。′″の状
態になるので、エネルギバンドは(d)に示す如く、上
記とは逆の蓄積状態となり、TPTはオン動作となる。
On the other hand, during the address period in which data is written, a positive voltage equal to or higher than Ec is applied to the gate, and the direction of the electric field is reversed, so that the ferroelectric film becomes P as shown in a). '', the energy band is in an accumulation state opposite to the above, as shown in (d), and the TPT is turned on.

5 6 このように本発明によれば、強誘電体のメモリ作用によ
り、ゲートバイアスーOの時でも、通常のTPTで負の
ゲート電圧を印加するのと等価なTPTのチャネル状態
が実現でき、データの保持に必要な充分低いオフ電流を
実現できる。
5 6 As described above, according to the present invention, due to the memory effect of the ferroelectric material, even when the gate bias is -0, it is possible to realize a TPT channel state equivalent to applying a negative gate voltage to a normal TPT. A sufficiently low off-state current necessary for data retention can be achieved.

〔実 施 例〕〔Example〕

本発明の一実施例を第5図により説明する。 An embodiment of the present invention will be described with reference to FIG.

ガラス基板11上に、ゲート電極1となるTi膜を約8
0nmの厚さにスパッタリング法により形或する。次に
強誘電体膜としてのP b T i O 3膜3を、約
5 0 0 nmの厚さに真空蒸着法により形威する。
A Ti film, which will become the gate electrode 1, is placed on the glass substrate 11 in a thickness of about 8
It is formed to a thickness of 0 nm by sputtering. Next, a P b Ti O 3 film 3 as a ferroelectric film is formed to a thickness of about 500 nm by vacuum evaporation.

次いで、プラズマCVD法により、窒化シリコン膜4を
約30nmの厚さに、動作半導体層としT(Da−S 
i : H (水素化アモルファスシリコン)膜5を約
50nmの厚さに形戒する。更にコンタクト層としての
厚さ約30nmのn”a−Si:H膜6と、金属膜とし
ての厚さ約100nmのTi膜7とを積層し、これをパ
クーニングしてソース電極Sおよびドレイン電極Dを形
威することにより、本実施例の薄膜トランジスタが完或
する。
Next, by plasma CVD method, the silicon nitride film 4 is made to have a thickness of about 30 nm as an active semiconductor layer T (Da-S
i: H (hydrogenated amorphous silicon) film 5 is formed to a thickness of about 50 nm. Furthermore, an n"a-Si:H film 6 with a thickness of about 30 nm as a contact layer and a Ti film 7 with a thickness of about 100 nm as a metal film are laminated, and these are punctured to form a source electrode S and a drain electrode D. By applying this, the thin film transistor of this example is completed.

以上述べた本実施例の薄膜トランジスタの電圧電流特性
は、P.一状態では第6図の曲綿Iに示すようにドレイ
ン電流が低下して、闇値が正の方向にシフトし、Po+
″状態では曲線■に示すようにドレイン電流は増大し、
闇値は負の方向にシフトする。そのため前記第3図に示
すように、非選択期間にEc一以下の電圧を印加し、ア
ドレス期間にはEc”以上の電圧を印加することによっ
て、非選択期間には第6図の曲線Iの特性で動作させる
ことができる。従ってゲートバイアスが0の時のオフ電
流が大幅に小さくなる。
The voltage-current characteristics of the thin film transistor of this example described above are as follows from P. In one state, as shown in curve I in Figure 6, the drain current decreases, the dark value shifts in the positive direction, and Po+
In the ``state, the drain current increases as shown in curve ■,
The darkness value shifts in the negative direction. Therefore, as shown in FIG. 3, by applying a voltage of less than Ec1 during the non-selection period and applying a voltage of Ec'' or more during the address period, the curve I of FIG. 6 is applied during the non-selection period. Therefore, the off-state current when the gate bias is 0 is significantly reduced.

なお、曲線■は本実施例の特性と比較のために掲げたも
ので、従来の薄膜トランジスタの特性を示す。
Note that the curve {circle around (2)} is shown for comparison with the characteristics of this example, and represents the characteristics of a conventional thin film transistor.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、ゲートバイアス=0
でも、データの保持に必要な充分低いオフ電流得ること
ができるので、鮮明な表示のTPT駆動液晶ディスプレ
イが実現できる。
As explained above, according to the present invention, gate bias=0
However, since a sufficiently low off-state current necessary for data retention can be obtained, a TPT-driven liquid crystal display with clear display can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第l図は本発明の構威説明図、 第2図は強誘電体のメモリ作用、 第3図はTPT駆動電圧波形、 第4図は本発明の原理説明図、 第5図は本発明一実施例説明図、 第6図は本発明一実施例の特性説明図、第7図はゲート
接続方式の等価回路図である。 図において、1はゲート電極、2はゲート絶縁膜、3は
強誘電体膜(PbTi03膜)、4はSiN膜、5は動
作半導体層(a−St:H膜)、6はコンタクト層(n
” a−S i : H膜)、7は金属膜(Ti膜)、
11はガラス基板を示す。
Fig. 1 is an explanatory diagram of the structure of the present invention, Fig. 2 is a memory effect of ferroelectric material, Fig. 3 is a TPT drive voltage waveform, Fig. 4 is an explanatory diagram of the principle of the present invention, and Fig. 5 is an illustration of the principle of the present invention. FIG. 6 is an explanatory diagram of characteristics of an embodiment of the present invention, and FIG. 7 is an equivalent circuit diagram of a gate connection method. In the figure, 1 is a gate electrode, 2 is a gate insulating film, 3 is a ferroelectric film (PbTi03 film), 4 is a SiN film, 5 is an active semiconductor layer (a-St:H film), and 6 is a contact layer (n
” a-S i: H film), 7 is a metal film (Ti film),
11 indicates a glass substrate.

Claims (2)

【特許請求の範囲】[Claims] (1)ゲート電極(1)と動作半導体層(5)との間に
介在するゲート絶縁膜(2)を、強誘電体膜(3)を含
む絶縁膜としたことを特徴とする薄膜トランジスタ。
(1) A thin film transistor characterized in that the gate insulating film (2) interposed between the gate electrode (1) and the active semiconductor layer (5) is an insulating film containing a ferroelectric film (3).
(2)前記動作半導体層(5)が水素化アモルファスシ
リコン膜からなり、前記ゲート絶縁膜(2)が、前記動
作半導体層に接する窒化シリコン膜(4)と、前記ゲー
ト電極と接する強誘電体膜(3)とを含む積層膜である
ことを特徴とする請求項1記載の薄膜トランジスタ。
(2) The active semiconductor layer (5) is made of a hydrogenated amorphous silicon film, and the gate insulating film (2) is made of a silicon nitride film (4) in contact with the active semiconductor layer and a ferroelectric material in contact with the gate electrode. The thin film transistor according to claim 1, wherein the thin film transistor is a laminated film including a film (3).
JP1157537A 1989-06-19 1989-06-19 Thin film transistor device Expired - Lifetime JP2855663B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1157537A JP2855663B2 (en) 1989-06-19 1989-06-19 Thin film transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1157537A JP2855663B2 (en) 1989-06-19 1989-06-19 Thin film transistor device

Publications (2)

Publication Number Publication Date
JPH0322483A true JPH0322483A (en) 1991-01-30
JP2855663B2 JP2855663B2 (en) 1999-02-10

Family

ID=15651849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1157537A Expired - Lifetime JP2855663B2 (en) 1989-06-19 1989-06-19 Thin film transistor device

Country Status (1)

Country Link
JP (1) JP2855663B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51136248A (en) * 1975-05-21 1976-11-25 Tokyo Electric Co Ltd Ferroelectric fet memory device
JPH02266570A (en) * 1989-04-07 1990-10-31 Casio Comput Co Ltd Thin film transistor for memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51136248A (en) * 1975-05-21 1976-11-25 Tokyo Electric Co Ltd Ferroelectric fet memory device
JPH02266570A (en) * 1989-04-07 1990-10-31 Casio Comput Co Ltd Thin film transistor for memory

Also Published As

Publication number Publication date
JP2855663B2 (en) 1999-02-10

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