JPH03224254A - Manufacture of ceramic circuit board - Google Patents
Manufacture of ceramic circuit boardInfo
- Publication number
- JPH03224254A JPH03224254A JP2019417A JP1941790A JPH03224254A JP H03224254 A JPH03224254 A JP H03224254A JP 2019417 A JP2019417 A JP 2019417A JP 1941790 A JP1941790 A JP 1941790A JP H03224254 A JPH03224254 A JP H03224254A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- board
- circuit board
- glass ceramic
- active metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000002241 glass-ceramic Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000012298 atmosphere Substances 0.000 claims abstract description 9
- 239000011261 inert gas Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 47
- 238000010304 firing Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 239000004020 conductor Substances 0.000 abstract description 15
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 11
- 239000010949 copper Substances 0.000 abstract description 8
- 239000005388 borosilicate glass Substances 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000011888 foil Substances 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000002131 composite material Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910001316 Ag alloy Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- DOIRQSBPFJWKBE-UHFFFAOYSA-N dibutyl phthalate Chemical compound CCCCOC(=O)C1=CC=CC=C1C(=O)OCCCC DOIRQSBPFJWKBE-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000002075 main ingredient Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Ceramic Products (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
セラミック回路基板の製造方法に関し、高周波特性と放
熱性が優れた高速伝送用のセラミック回路基板を実用化
することを目的とし、半導体素子の装着位置を窓開けし
たガラスセラミック基板と窒化アルミニウム基板とを活
性金属蝋を介して密着せしめ、不活性ガス雰囲気中で焼
成することを特徴としてセラミック回路基板の製造方法
を構成する。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a ceramic circuit board, the mounting position of a semiconductor element is opened for the purpose of commercializing a ceramic circuit board for high-speed transmission with excellent high frequency characteristics and heat dissipation. The method for manufacturing a ceramic circuit board is characterized in that a glass ceramic substrate and an aluminum nitride substrate are brought into close contact with each other via active metal wax, and fired in an inert gas atmosphere.
［産業上の利用分野］
本発明は光通信用セラミック回路基板の製造方法に関す
る。[Industrial Application Field] The present invention relates to a method of manufacturing a ceramic circuit board for optical communication.
大量の情報を高速に処理する必要から、情報処理技術の
進歩は著しく、光通信が広く行われるようになった。Due to the need to process large amounts of information at high speed, information processing technology has advanced significantly and optical communications have become widely used.
こ＼で、光通信の特徴は信号の多重化と共に高速伝送が
可能なことであり、この特徴を活かすためにＬＳＩやＶ
ＬＳＩなとの半導体素子は信号の高速化に適するように
素子構成がなされている。Here, the characteristics of optical communication are that high-speed transmission is possible along with signal multiplexing, and in order to take advantage of these characteristics, LSI and V
Semiconductor devices such as LSIs are configured to be suitable for increasing the speed of signals.
そこで、これらの半導体素子を搭載する回路基板も低損
失で、熱伝導性が良く、また電子回路は導体抵抗の少な
い金属材料を用いてパターン形成を行うことが必要であ
る。Therefore, it is necessary that the circuit board on which these semiconductor elements are mounted has low loss and good thermal conductivity, and that the electronic circuit is patterned using a metal material with low conductor resistance.
当初、多層セラミック回路基板の基板材料としてはアル
ミナ（Ａｊ！ｔ（ｈ）が使用され、また電子回路の構成
材料としてはタングステン（Ｗ）が使用されていた。Initially, alumina (Aj!t(h)) was used as a substrate material for multilayer ceramic circuit boards, and tungsten (W) was used as a constituent material for electronic circuits.
この理由はアルミナは耐熱性が優れた安定した酸化物で
あり、また熱伝導率は２０Ｗ／ｍ Ｋと比較的価れてい
るからである。The reason for this is that alumina is a stable oxide with excellent heat resistance and has a relatively high thermal conductivity of 20 W/mK.
然し、アルミナの融点は２０１５°Ｃと高く、焼結温度
として１６００°Ｃ程度が必要である。However, the melting point of alumina is as high as 2015°C, and a sintering temperature of about 1600°C is required.
そのため、アルミナからなるグリーンシートの上にスク
リーン印刷して導体線路を形成する構成材料としてはＷ
のように高融点（３３８７℃）の金属しか使用できない
からである。Therefore, the material used to form conductor lines by screen printing on green sheets made of alumina is W.
This is because only metals with a high melting point (3387°C) can be used, such as.
ニーで、Ｗの導体抵抗は約１０ ｍΩ／口と大きく、信
号の伝播遅延および伝送損失が大きく、高速伝送には不
利である。At the knee, the conductor resistance of W is as large as about 10 mΩ/mouth, resulting in large signal propagation delays and transmission losses, which is disadvantageous for high-speed transmission.
また、アルミナの誘電率は８〜１０と大きく、−方、多
層セラミック基板の単位層の厚さは約２００μｍと薄い
ことから、眉間の配線間に静電容量を生じ、漏話（Ｃｒ
ｏｓｓ−ｔａｌｋ）が起こることから伝送損失が増加す
ると云う問題もある。In addition, the dielectric constant of alumina is as high as 8 to 10, and on the other hand, the thickness of the unit layer of a multilayer ceramic substrate is as thin as approximately 200 μm, which causes electrostatic capacitance between the wiring between the eyebrows and crosstalk (Cr
There is also the problem that transmission loss increases due to the occurrence of oss-talk.
発明者等はこの問題を解決するために、第３図（Ａ）と
（Ｂ）に示すように、半導体素子の装着位置を窓開けし
たガラスセラミック多層基板と窒化アルミニウム基板（
ＡｌＮ）とを接合したセラミック回路基板を提案してい
る。In order to solve this problem, the inventors developed a glass-ceramic multilayer substrate and an aluminum nitride substrate (with openings for mounting the semiconductor elements), as shown in FIGS. 3(A) and 3(B).
We are proposing a ceramic circuit board bonded with AlN).
（特願平１−５５３１３８．特願平１−５５９１１８な
ど）発明者等は伝送損失が少なく、高周波特性の優れた
セラミック回路基板を実用化するためには、■ 誘電率
が少なく、電気的特性の優れたセラミックスを使用する
こと、
■ 導体パターンの構成材料として！１４（Ｃｕ）を使
用できること、
■ 基板の放熱性が優れていること、
■ ワイヤボンディングの配線距離が短いこと、などの
条件を備えていることが必要と考えた。(Japanese Patent Application No. 1-553138, Patent Application No. 1-559118, etc.) In order to put into practical use a ceramic circuit board with low transmission loss and excellent high frequency characteristics, the inventors believe that: Using superior ceramics, ■ As a constituent material for conductor patterns! 14 (Cu), 1. The substrate has excellent heat dissipation, and 2. The wiring distance for wire bonding is short.
そして、■に適した材料として硼珪酸ガラスとアルミナ
とからなる複合誘電体を選んだ。A composite dielectric made of borosilicate glass and alumina was selected as a material suitable for (2).
その理由は、硼珪酸ガラスの誘電率は組成比により異な
るもの＼４．１〜４．８とアルミナに較べれば遥かに少
なく、また電気的特性も優れている。The reason for this is that borosilicate glass has a dielectric constant of 4.1 to 4.8, which varies depending on the composition ratio, which is much lower than that of alumina, and it also has excellent electrical properties.
然し、そのま−では軟化温度が低く、スクリーン印刷法
で形成した銅からなる導体回路の焼成ができず、また機
械的強度も劣っている。However, until then, the softening temperature is low, making it impossible to fire conductor circuits made of copper formed by screen printing, and the mechanical strength is also poor.
そこで、軟化温度を上げ、また機械的強度を向上するた
めにアルミナとの複合誘電体とした。Therefore, in order to raise the softening temperature and improve mechanical strength, we created a composite dielectric with alumina.
これにより、複合誘電率は約５．６と少し増加するが、
軟化温度は１０００℃程度となり、そのため導体抵抗が
１．５１Ωと少ないＣｕを導体線路の構成材として使用
することが可能となる。As a result, the composite dielectric constant increases slightly to about 5.6, but
The softening temperature is about 1000° C., so Cu, which has a low conductor resistance of 1.51Ω, can be used as a material for forming the conductor line.
次に、■の半導体チップの放熱性を高める方法として半
導体チップをＡＩＮ基板の上に直接に装着するようにし
た。Next, as a method (2) to improve the heat dissipation of the semiconductor chip, the semiconductor chip was mounted directly on the AIN board.
すなわち、へＩＮ基板の熱伝導率は２６０ Ｗ／ｍ Ｋ
（理論値３２０ Ｗ／ｍ Ｋ）であって、アルミナ（α
−Ａｌ２Ｏ２）の熱伝導率が２０ Ｗ／ａ’にであるの
に較べて格段に優れている。That is, the thermal conductivity of the IN board is 260 W/m K
(theoretical value 320 W/m K) and alumina (α
-Al2O2), which has a thermal conductivity of 20 W/a'.
また、■のワイヤボンディング距離を短縮する方法とし
て、ガラスセラミックス基板に半導体チップを搭載する
のに充分な穴を設け、半導体チップをＡＩＮ基板に搭載
するようにした。In addition, as a method of shortening the wire bonding distance (2), a hole sufficient for mounting a semiconductor chip on the glass ceramic substrate was provided, and the semiconductor chip was mounted on the AIN substrate.
第３図（Ａ）、（Ｂ）において、ガラスセラミック基板
１はＣｕからなる導体回路がパターン形成されている複
数のガラスセラミックス層が積層されたものであり、表
面には半導体素子とボンディングするバッド２を含めて
導体回路が設けられている。In FIGS. 3(A) and 3(B), the glass ceramic substrate 1 is a stack of a plurality of glass ceramic layers on which conductor circuits made of Cu are patterned, and the surface has a pad for bonding with a semiconductor element. A conductor circuit including 2 is provided.
一方、ガラスセラミック基板１０半導体素子３の搭載位
置は穴開けされて、Ａ１Ｎ基板４が露出している。On the other hand, a hole is made at the mounting position of the glass ceramic substrate 10 and the semiconductor element 3, so that the A1N substrate 4 is exposed.
そして、同図（Ｂ）に示すように半導体素子３は厚膜法
などにより作られたメタライズ層５を介してＡｆＮ基板
４に装着され、ガラスセラミック基板１上のパッド２と
ワイヤボンディングするこはにより回路接続が行われて
いる。Then, as shown in FIG. 2B, the semiconductor element 3 is attached to the AfN substrate 4 via the metallized layer 5 made by the thick film method, etc., and wire bonded to the pad 2 on the glass ceramic substrate 1. The circuit connection is made by
然し、このような構造をとるセラミック回路基板の問題
点はガラスセラミック基板１とＡｆＮ基板４との密着強
度が不充分なことであり、充分な密着強度をもたせるた
めには多大の工数を要する点が問題であった。However, the problem with the ceramic circuit board having such a structure is that the adhesion strength between the glass ceramic substrate 1 and the AfN substrate 4 is insufficient, and it requires a large amount of man-hours to provide sufficient adhesion strength. was the problem.
以上記したように信号の高速伝送用の回路基板として、
ガラスセラミック基板とＡｌＮ基板とを接合した複合基
板の使用を提案しているが、両基板を多くの工数を要す
ることなく充分な密着強度で接合させることが課題であ
る。As mentioned above, as a circuit board for high-speed signal transmission,
Although the use of a composite substrate in which a glass ceramic substrate and an AlN substrate are bonded is proposed, the problem is how to bond both substrates with sufficient adhesion strength without requiring a large number of man-hours.
〔課題を解決するための手段］
上記の課題は半導体素子の装着位置を窓開けしたガラス
セラミック基板とＡｌＮ基板とを活性金属蝋を介して密
着せしめ、不活性ガス雰囲気中で焼成することを特徴と
してセラミック回路基板の製造方法を構成することによ
り解決することができる。[Means for Solving the Problem] The above problem is characterized in that a glass ceramic substrate with a window for mounting a semiconductor element and an AlN substrate are brought into close contact with each other via active metal wax, and then fired in an inert gas atmosphere. This problem can be solved by configuring a method for manufacturing a ceramic circuit board.
従来の方法としては、ガラスセラミック基板をグリーン
シートの段階でＡｌ２Ｎ基板と接合し、加圧した状態で
窒素（Ｎ２）などの不活性ガス雰囲気中で焼成したり、
既に焼成が終わったガラスセラミック基板の接合面にガ
ラスペーストを塗布し、これとＡｌＮ基板と密着させた
状態で焼成する方法などを用いていたが、充分な密着強
度を保持することは困難であった。Conventional methods include bonding a glass ceramic substrate to an Al2N substrate at the green sheet stage and firing it under pressure in an inert gas atmosphere such as nitrogen (N2).
Previously, a method was used in which glass paste was applied to the bonding surface of a glass-ceramic substrate that had already been fired, and the paste was then fired in close contact with the AlN substrate, but it was difficult to maintain sufficient adhesion strength. Ta.
そして、適当な方法としては、第２図に示すように焼成
の終わったガラスセラミック基板１（この例の場合は三
層構成）の下と、ＡｌＮ基板４の上にＣｕペーストをス
クリーン印刷した後、不活性雰囲気中で焼成するなどの
方法でメタライズ層６゜６′を作り、 この両者を眼部
７により溶着するなどの方法がとられていた。As shown in Fig. 2, an appropriate method is to screen print Cu paste under the fired glass ceramic substrate 1 (three-layer structure in this example) and on the AlN substrate 4. The metallized layer 6°6' is formed by firing in an inert atmosphere, and the two are welded together by the eye 7.
然し、この方法は多大の工数を要して実用的な方法では
なかった。However, this method required a large amount of man-hours and was not practical.
そのため、本発明は接合材として活性金属鑞を用いるも
のである。Therefore, the present invention uses active metal solder as a bonding material.
こ−で、活性金属鑞はチタン（Ｔｉ）やジルコン（Ｚｒ
）のような活性な金属を含む眼部であり、焼成に際して
活性金属が良く拡散し、相手方の元素と化合物を作るこ
とから良い接着を行うことができる。In this case, the active metal solder is titanium (Ti) or zircon (Zr).
), and the active metal diffuses well during firing and forms a compound with the other element, resulting in good adhesion.
そして活性金属鑞としてはＺｒ／Ａｇ／Ｃｕ合金、Ｔｉ
／Ａｇ／Ｃｕ合金などを挙げることができる。And as active metal solder, Zr/Ag/Cu alloy, Ti
/Ag/Cu alloy.
本発明は第１図に示すように、焼成の終わったガラスセ
ラミック基板１ （この例の場合は三層構成）とＡｌＮ
基板４とを活性金属鑞箔８を介して接合した状態で不活
性雰囲気中で加熱することにより密着性の優れた接合を
得るものである。As shown in FIG. 1, the present invention consists of a fired glass ceramic substrate 1 (three-layer structure in this example) and an AlN
A bond with excellent adhesion is obtained by heating the substrate 4 in an inert atmosphere while bonded to the substrate 4 via the active metal solder foil 8.
［実施例］
実施例１：
主剤： 硼硅酸ガラス ・・・５０重量％：
アルミナ ・・・５０〃バインダ：ポリメ
チルメタアクリレート（略称ＰＭＭＡ）
・・・１０重量％可塑剤： ジブチルフタレート
・・・５ 〃からなる厚さが３００μ冑のガラスセラ
ミック・グリーンシートにＣｕペーストをスクリーン印
刷してパターンニングを行い、８０°Ｃで３０分乾燥し
た。[Example] Example 1: Main ingredient: Borosilicate glass...50% by weight:
Alumina...50 Binder: Polymethyl methacrylate (abbreviated as PMMA)
...10% by weight plasticizer: dibutyl phthalate ...5 A glass ceramic green sheet with a thickness of 300 μm was patterned with Cu paste by screen printing, and then dried at 80°C for 30 minutes. .
このグリーンシートを四層積層し、１３０°Ｃ，３０Ｍ
Ｐａの条件で加圧し、Ｎ２雰囲気中で８５０°Ｃで４時
間加熱してバインダ抜きを行った後に１０００°Ｃで４
時間焼成してガラスセラミック基板を形成した。This green sheet was laminated in four layers at 130°C and 30M.
After pressurizing under Pa conditions and heating at 850°C for 4 hours in a N2 atmosphere to remove the binder, the
A glass ceramic substrate was formed by firing for a period of time.
次に、このガラスセラミック基板と市販のＡｌＮ基板（
熱伝導率： １５０Ｗ／ｍ Ｋ）との間に厚さが０゜１
ａ＋＋ａのＴｉ／Ａｇ／Ｃｕ合金を挟み、Ｎ、ｉ雰囲気
中で９００°Ｃで２０分に亙って焼成してセラミック回
路基板ができた。Next, this glass ceramic substrate and a commercially available AlN substrate (
Thermal conductivity: 150W/m K) and thickness 0°1
A ceramic circuit board was obtained by sandwiching a Ti/Ag/Cu alloy of a++a and firing at 900° C. for 20 minutes in an N, i atmosphere.
この基板の密着強度は２０ＭＰａであり、導体抵抗は２
−Ω／口であった。The adhesion strength of this board is 20 MPa, and the conductor resistance is 2
-Ω/mouth.
実施例２：
活性金属鑞として厚さが０．１ ｗｍのＺｒ／Ａｇ／Ｃ
ｕ合金を用いた以外は実施例１と全く同様にしてガラス
セラミック基板とＡｌＮ基板との接合体を焼成してセラ
ミック回路基板を作った。Example 2: Zr/Ag/C with a thickness of 0.1 wm as active metal solder
A ceramic circuit board was produced by firing a joined body of a glass ceramic substrate and an AlN substrate in exactly the same manner as in Example 1 except that the u alloy was used.
この基板の密着強度は２０ＭＰａであり、導体抵抗は２
ｍΩ／口であった。The adhesion strength of this board is 20 MPa, and the conductor resistance is 2
It was mΩ/mouth.
実施例３：
接合体の焼成温度を８５０°Ｃとした以外は実施例１と
全く同じ条件で焼成してセラミック回路基板を作った。Example 3: A ceramic circuit board was produced by firing under exactly the same conditions as in Example 1, except that the firing temperature of the joined body was 850°C.
この基板は焼成温度が低いために密着強度は１゜ＭＰａ
と少し低＼、また、導体抵抗は２ｍΩ／口であった。Because the firing temperature of this substrate is low, the adhesion strength is 1°MPa.
The conductor resistance was 2 mΩ/mouth.
実施例４：
接合体の焼成温度を９５０ ’Ｃとした以外は実施例１
と全く同じ条件で焼成してセラミック回路基板を作った
。Example 4: Example 1 except that the firing temperature of the joined body was 950'C.
A ceramic circuit board was made by firing under exactly the same conditions.
この基板は焼成温度が高すぎてガラスセラミック基板の
変形が生じ、密着強度は２０ＭＰａと良好であったが、
導体抵抗は４ｎ＋Ω／口と増加した。The firing temperature of this substrate was too high, causing deformation of the glass ceramic substrate, and the adhesion strength was good at 20 MPa.
The conductor resistance increased to 4n+Ω/mouth.
実施例５：
接合体の焼成を真空炉を用いて行った以外は実施例１と
全く同じ条件で焼成してセラミック回路基板を作った。Example 5: A ceramic circuit board was produced by firing under exactly the same conditions as in Example 1, except that the bonded body was fired using a vacuum furnace.
この基板の密着強度は２０ Ｍ Ｐａであり、導体抵抗
は２−Ω／口であった。The adhesion strength of this substrate was 20 MPa, and the conductor resistance was 2-Ω/hole.
以上説明したように本発明の実施によりガラスセラミッ
ク基板と＾ｊ２Ｎ基板とを簡単に接合することができ、
然も大きな密着強度を得ることができる。As explained above, by implementing the present invention, a glass ceramic substrate and a ^j2N substrate can be easily joined,
However, great adhesion strength can be obtained.
第１図は本発明に係るセラミック回路基板の構成を示す
部分断面図、
て
第２図は従来用いらば）た接合法を説明する部分断面図
、
第３図は発明者等が先に提案しているセラミック回路基
板の斜視図（Ａ）と部分断面図（Ｂ）、である。
図において、
１はガラスセラミック基板、
３は半導体素子、 ４はＡＩＭ基板、６．６′は
メタライズ層、
７は眼部、 ８は活性金属鑞箔、である。Fig. 1 is a partial sectional view showing the structure of the ceramic circuit board according to the present invention, Fig. 2 is a partial sectional view illustrating the bonding method conventionally used, and Fig. 3 is a partial sectional view illustrating the bonding method previously proposed by the inventors. 1 is a perspective view (A) and a partial cross-sectional view (B) of a ceramic circuit board. In the figure, 1 is a glass ceramic substrate, 3 is a semiconductor element, 4 is an AIM substrate, 6.6' is a metallized layer, 7 is an eye part, and 8 is an active metal solder foil.
Claims (1)
基板と窒化アルミニウム基板とを活性金属蝋を介して密
着せしめ、不活性ガス雰囲気中で焼成することを特徴と
するセラミック回路基板の製造方法。A method for manufacturing a ceramic circuit board, comprising: bonding a glass ceramic substrate with a window for mounting a semiconductor element to an aluminum nitride substrate via active metal wax, and firing the substrate in an inert gas atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019417A JP2687646B2 (en) | 1990-01-30 | 1990-01-30 | Manufacturing method of ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019417A JP2687646B2 (en) | 1990-01-30 | 1990-01-30 | Manufacturing method of ceramic circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03224254A true JPH03224254A (en) | 1991-10-03 |
| JP2687646B2 JP2687646B2 (en) | 1997-12-08 |
Family
ID=11998686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019417A Expired - Lifetime JP2687646B2 (en) | 1990-01-30 | 1990-01-30 | Manufacturing method of ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2687646B2 (en) |
-
1990
- 1990-01-30 JP JP2019417A patent/JP2687646B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2687646B2 (en) | 1997-12-08 |
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