JPH04125994A - Multilayered ceramic substrate and manufacture thereof - Google Patents

Multilayered ceramic substrate and manufacture thereof

Info

Publication number
JPH04125994A
JPH04125994A JP24625890A JP24625890A JPH04125994A JP H04125994 A JPH04125994 A JP H04125994A JP 24625890 A JP24625890 A JP 24625890A JP 24625890 A JP24625890 A JP 24625890A JP H04125994 A JPH04125994 A JP H04125994A
Authority
JP
Japan
Prior art keywords
pins
pin
ceramic
firing
laminated body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24625890A
Other languages
Japanese (ja)
Other versions
JP3184207B2 (en
Inventor
Hiroshi Nakajima
寛 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Chemi Con Corp
Original Assignee
Nippon Chemi Con Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Chemi Con Corp filed Critical Nippon Chemi Con Corp
Priority to JP24625890A priority Critical patent/JP3184207B2/en
Publication of JPH04125994A publication Critical patent/JPH04125994A/en
Application granted granted Critical
Publication of JP3184207B2 publication Critical patent/JP3184207B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To improve the joining strength between pins and a multilayered ceramic substrate by inserting each pin having a projecting section at part into a laminated body of green sheets and simultaneously sintering the laminated body of green sheets, pins and gold via conductors respectively formed below the pins in advance. CONSTITUTION:Each pin 12 having a projecting section 14 is erected at a prescribed location of a laminated body of green sheets 10. While each the pin 12 is inserted into the laminated body at the time of pressing the laminated body, a gold via conductor 16 is arranged below each pin 12 in advance. After inserting the pins 12, this multilayered ceramic substrate is formed by simultaneously sintering the laminated body of green sheets 10, pins 12, and conductors 16. Therefore, a decline in the joining strength between the pins and this ceramic substrate caused by clearances produced between the pins and substrate can be prevented.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、セラミック多層基板に端子ピンを立設する製
造方法の改良、およびこの方法によって製造されるセラ
ミック多層基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a manufacturing method for erecting terminal pins on a ceramic multilayer board, and to a ceramic multilayer board manufactured by this method.

[従来の技術] 近年の電子回路の小型化・高密度化に対応して、セラミ
ック基板の多層化が進められているが、この目的により
適切に適合するものとして、近年では特に低温焼成基板
が注目されている。
[Prior Art] In response to the miniaturization and higher density of electronic circuits in recent years, ceramic substrates are becoming more multilayered. Attention has been paid.

従来の基板材料としては、熱放散、熱膨脹係数、寸法安
定性等の観点から優れた特性を有するアルミナ多層基板
が重要な位置を占めていた。しかしながら、アルミナの
焼成条件としては一般に1500℃以上の高温を必要と
するため、導体材料としては耐熱性金属であるMOやW
等に使用範囲が限定されていた。また、高温焼成に耐え
る必要があるため、抵抗体材料等についても一定の制約
が余儀なくされていた。
As a conventional substrate material, an alumina multilayer substrate, which has excellent properties from the viewpoint of heat dissipation, thermal expansion coefficient, dimensional stability, etc., has occupied an important position. However, since the firing conditions for alumina generally require a high temperature of 1500°C or higher, the conductor material is MO or W, which is a heat-resistant metal.
The scope of use was limited. Further, since it is necessary to withstand high-temperature firing, certain restrictions have been imposed on resistor materials and the like.

このようなアルミナ多層基板の問題点を克服し、導体材
料、抵抗体材料等の電子部品の使用範囲拡大を図るべく
、焼成温度が一般に900℃程度と低くても十分な品質
の基板を作製し得る材料の開発が行われ、この結果近年
では、700°C以下〜1000℃程度でも焼成できる
カラス粉末等のような規程かの材料を用いることにより
、例えば多層配線基板として基板と導体ペーストとを同
時に焼成できる低温焼成基板が実用化されている。一般
に低温焼成基板は、導体のスクリーン印刷が可能であり
、高伝導度を有し、高周波特性に優れる等の利点を有す
る。
In order to overcome these problems of alumina multilayer substrates and expand the scope of use of electronic components such as conductor materials and resistor materials, we have created substrates of sufficient quality even at low firing temperatures, generally around 900°C. As a result, in recent years, materials such as glass powder, which can be fired at temperatures of 700°C or less to 1000°C, have been developed, and by using materials that meet regulations such as glass powder, it has become possible to combine substrates and conductive pastes, for example, into multilayer wiring boards. Low-temperature firing substrates that can be fired at the same time have been put into practical use. In general, low-temperature fired substrates have advantages such as being able to be screen printed with conductors, having high conductivity, and having excellent high frequency characteristics.

このような低温焼成基板を使用することにより、導体材
料や抵抗体材料の使用範囲が拡大され、より高性能の基
板を提供することができるため、これと共に基板の用途
も更に拡大し、より高密度化が求められる混成集積口F
!f1(ハイブリッドIC)等にも低温焼成基板が広く
使用されるに至っている。
By using such low-temperature fired substrates, the scope of use of conductor materials and resistor materials can be expanded, and higher performance substrates can be provided. Mixed accumulation port F where density is required
! Low-temperature fired substrates have come to be widely used in f1 (hybrid IC) and the like.

一般にセラミック基板上には、外部との電気的な接続を
得るための端子ピンが所定の位置に立設されるが、従来
よりセラミック基板として多用されているものは、前記
したように酸化アルミニウムからなるアルミナ基板であ
り、アルミナ基板の焼成は1500〜1600’Cの高
温で行われるため、焼成前のグリーンシートの段階で、
ピンを所定の位置に予め取り付けておくことはできなか
った。
Ceramic substrates generally have terminal pins standing upright at predetermined positions for electrical connection with the outside world, but as mentioned above, the ceramic substrates that have been commonly used are made of aluminum oxide. Since the alumina substrate is fired at a high temperature of 1500 to 1600'C, at the green sheet stage before firing,
It was not possible to pre-install the pins in place.

従来の製造方法においては、第2図に示すように、焼結
時にアルミナ基板30の表面に形成したW、No等の高
融点材の導体パターン32にNiメツキ34を施し、こ
こにA!11/Cu合金等のろう付は剤36を塗布した
端子ピン38を配置して、ろう付けにより立設していた
。このため、端子ピン38の折り曲げや引張り等の機械
的強度が十分ではなかった。また、ピンの配置作業の際
には、基板が焼成により収縮し所定の#C続位置が変動
するため、端子ピン毎に位置決めを行わなければならな
い等、工程が煩雑でもあった。
In the conventional manufacturing method, as shown in FIG. 2, Ni plating 34 is applied to a conductor pattern 32 of a high melting point material such as W or No formed on the surface of an alumina substrate 30 during sintering, and A! 11/Cu alloy, etc., terminal pins 38 coated with agent 36 are arranged and erected by brazing. For this reason, the mechanical strength of the terminal pin 38, such as bending and tension, was not sufficient. Furthermore, when arranging the pins, the substrate shrinks due to firing and the predetermined #C connection position changes, so the process is complicated, such as having to position each terminal pin.

このような問題点の解決を図るべく、本出願人は先に特
願平2−194056号として、ガラスセラミック材か
らなる低温焼成用セラミックから構成した多層または単
層のグリーンシートの所定位置に棒状のピンを立設し、
その後低温で焼成を行うことを特徴とする低温焼成回路
基板の製造方法を提案した。しかしながら、セラミック
多層基板にピンを立設する場合、ピン材の金属とセラミ
ックとの間の熱膨脹係数が異なるため、ピンとセラミッ
クとの間に隙間が生じてしまい、接合強度が低下する傾
向があることが分った。
In order to solve these problems, the present applicant previously proposed in Japanese Patent Application No. 2-194056 a rod-shaped green sheet at a predetermined position of a multi-layer or single-layer green sheet made of a ceramic for low-temperature firing made of glass-ceramic material. Set up the pin of
We proposed a method for manufacturing low-temperature firing circuit boards, which is characterized by subsequently firing at a low temperature. However, when placing pins upright on a ceramic multilayer board, the metal pin material and the ceramic have different coefficients of thermal expansion, which tends to create gaps between the pin and the ceramic, resulting in a decrease in bonding strength. I understand.

[発明が解決しようとする課題] 本発明は、グリーンシートに端子ピンを予め立設して同
時焼成することにより製造するセラミック多層基板を改
良し、ピン材の金属とセラミックとの間の熱膨脹係数の
相異によるピンとセラミックとの間の隙間の発生に起因
する接合強度の低下を回避し、接合強度を向上させ得る
セラミック多層基板およびその製造方法を提供すること
を目的とする。
[Problems to be Solved by the Invention] The present invention improves a ceramic multilayer board manufactured by arranging terminal pins in advance on a green sheet and firing them simultaneously, and improves the coefficient of thermal expansion between the metal of the pin material and the ceramic. It is an object of the present invention to provide a ceramic multilayer substrate and a method for manufacturing the same that can avoid a decrease in bonding strength due to the generation of gaps between pins and ceramics due to differences in bonding strength, and can improve bonding strength.

[課題を解決するための手段] 本発明によれば、ガラスセラミック材からなる低温焼成
用セラミックから構成したグリーンシートの所定位置に
棒状のピンを立設し、その後低温で焼成を行うことから
なり、一部に凸部を有するピンをプレスの際に打ち込み
、ピンの下に金ビア導体を予め配置し、同時焼成するこ
とを特徴とするセラミック多層基板の製造方法が提供さ
れる。
[Means for Solving the Problems] According to the present invention, rod-shaped pins are erected at predetermined positions of a green sheet made of a ceramic for low temperature firing made of a glass ceramic material, and then firing is performed at a low temperature. Provided is a method of manufacturing a ceramic multilayer substrate, which is characterized in that a pin having a portion of a convex portion is driven in during pressing, a gold via conductor is previously placed under the pin, and co-firing is performed.

金ビア導体は、金を含有するビア導体であり、次の条件
: 1700〜1000℃にて大気中で変質せず硬度も低下
しない、 ■基板の導体である金属体と強固に接合する、を充足す
るものを使用すれば好適である。
A gold via conductor is a via conductor that contains gold, and meets the following conditions: ■ It does not change in quality in the atmosphere at 1700 to 1000 degrees Celsius, and its hardness does not decrease. ■ It firmly joins to the metal body that is the conductor of the board. It is preferable to use one that satisfies the requirements.

更に本発明によれば、前記した方法により製造されたセ
ラミック多層基板が提供される。
Further, according to the present invention, there is provided a ceramic multilayer substrate manufactured by the method described above.

本発明に使用し得るガラスセラミック材からなる低温焼
成用セラミックとして、例えば鉛ホウゲイ酸ガラスーア
ルミナ等を例示することができ、このようなセラミック
を用いて、好ましくは700〜1ooo℃の温度で焼成
を行う。
Examples of low-temperature firing ceramics made of glass-ceramic materials that can be used in the present invention include lead borosilicate glass-alumina. I do.

グリーンシートに立設するピンの材質は、通常使用され
るものでよく、例えばAu−Pt−AQ金合金を使用す
ることができる。
The material of the pins erected on the green sheet may be any commonly used material, such as Au-Pt-AQ gold alloy.

ピンの凸部は、適切にはピンの径の200〜300%程
度の径を有するものとする。
The convex portion of the pin preferably has a diameter of about 200 to 300% of the diameter of the pin.

このような凸部を有するピンの下にピンと接合性の強い
金ビア導体を形成するが、この金ビア導体の径は、好ま
しくはピンの凸部の径と同程度とする。また、金ビア導
体の縦方向の厚さは、好ましくは0.2〜0.6 nr
g程度とする。
A gold via conductor having strong bonding properties with the pin is formed under the pin having such a convex portion, and the diameter of this gold via conductor is preferably approximately the same as the diameter of the convex portion of the pin. Further, the vertical thickness of the gold via conductor is preferably 0.2 to 0.6 nr.
It should be around g.

[作用コ 前記したように、本出願人は、先にセラミック材料とし
て、通常1000℃以下で低温焼成可能なガラスセラミ
ック材を用い、焼成によるピンの変質がなく、グリーン
シートの段階で端子ビンを立設して焼成を行うことがで
きる低温焼成回路基板の製造方法を提案した。
[Operations] As mentioned above, the applicant used a glass-ceramic material that can be fired at a low temperature of usually 1000°C or less as a ceramic material, so that the pins would not change in quality due to firing and the terminal pins could be formed at the green sheet stage. We proposed a method for manufacturing low-temperature firing circuit boards that can be fired while standing upright.

しかしながら、セラミック多層基板にピンを立設する場
合、ピン材の金属とセラミックとの間の熱膨脹係数が異
なるため、ピンとセラミックとの間に隙間が生じてしま
い、接合強度が低下する傾向があることか分った。
However, when placing pins upright on a ceramic multilayer board, the metal pin material and the ceramic have different coefficients of thermal expansion, which tends to create gaps between the pin and the ceramic, resulting in a decrease in bonding strength. I understand.

本発明はこのような問題点の解決を図るものであり、セ
ラミック多層基板を製造するに際し、一部に凸部を有す
るピンをプレスの際に打ち込み、ピンの下に金ビア導体
を予め配置し、同時焼成するものである。
The present invention aims to solve these problems, and when manufacturing a ceramic multilayer board, a pin having a partially convex portion is driven into the press, and a gold via conductor is placed under the pin in advance. , are fired simultaneously.

すなわち本発明は、ピンと接合性の強い金ビア導体の材
料的性質を利用すると共に、ビン自体を所定の形状とす
ることにより、構造面からの接合強度の向上をも企図す
るものである。
That is, the present invention utilizes the material properties of the gold via conductor, which has strong bondability with pins, and also attempts to improve the bonding strength from a structural perspective by shaping the via itself into a predetermined shape.

[実施例コ 以下に実施例により本発明を更に詳細に説明するが、本
発明は以下の実施例にのみ限定されるものではない。
[Example] The present invention will be explained in more detail with reference to Examples below, but the present invention is not limited to the following Examples.

第1図は、本発明のセラミック多層基板にピンを立設す
る概略を示す図である。第1図に示すように、ガラスセ
ラミック材からなる低温焼成用セラミックから構成した
グリーンシート10の所定位置に棒状のピン12を立設
し、このピンは一部に凸部14を有するものとした。
FIG. 1 is a diagram schematically showing how pins are erected on the ceramic multilayer substrate of the present invention. As shown in FIG. 1, a rod-shaped pin 12 was erected at a predetermined position on a green sheet 10 made of a ceramic for low-temperature firing made of a glass ceramic material, and this pin had a convex portion 14 in a part. .

このピンをプレスの際に打ち込むが、ピンの下には金ビ
ア導体16を予め配置した。これをプレス後に同時焼成
することにより、セラミック多層基板を製造した。
This pin was driven in during pressing, and a gold via conductor 16 was previously placed under the pin. A ceramic multilayer substrate was produced by pressing and then simultaneously firing.

ガラスセラミック材として鉛ホウケイ酸ガラスーアルミ
ナを使用し、ピンの材質はAu −Pt−AQ金合金た
はN1−Cr−A!金合金し、焼成は900℃で常法に
より行った。
Lead borosilicate glass-alumina is used as the glass ceramic material, and the pin material is Au-Pt-AQ gold alloy or N1-Cr-A! Gold alloy was used, and firing was performed at 900° C. in a conventional manner.

ピンは直径0.41lrl、長さ3.Onmのものを使
用した。ピンの凸部の大きさは直径0.8 in、長さ
0.2 Ilmとした。金ビア導体部分の大きさは、直
径0.8 in、長さ0.2 nn+とじた。
The pin has a diameter of 0.41lrl and a length of 3. Onm's one was used. The size of the convex portion of the pin was 0.8 inches in diameter and 0.2 Ilm in length. The size of the gold via conductor portion was 0.8 inch in diameter and 0.2 nn+ in length.

得られたセラミック多層基板は、ピンとセラミックとの
間の隙間の発生に起因する接合強度の低下が回避され、
接合強度が向上したものであった。
The obtained ceramic multilayer board avoids a decrease in bonding strength due to the generation of gaps between the pins and the ceramic, and
The bonding strength was improved.

[発明の効果] 以上説明したように本発明によれば、グリーンシートに
端子ピンを予め立設して同時焼成することにより製造す
るセラミック多層基板を改良し、ピン材の金属とセラミ
ックとの間の熱膨脹係数の相異によるピンとセラミック
との間の隙間の発生に起因する接合強度の低下を回避し
、接合強度を向上させ得るセラミック多層基板およびそ
の製造方法が提供される。
[Effects of the Invention] As explained above, according to the present invention, a ceramic multilayer board manufactured by erecting terminal pins in advance on a green sheet and co-firing is improved, and the gap between the metal of the pin material and the ceramic is improved. Provided are a ceramic multilayer substrate and a method for manufacturing the same, which can avoid a decrease in bonding strength due to the generation of gaps between pins and ceramics due to differences in thermal expansion coefficients, and can improve bonding strength.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のセラミック多層基板にピンを立設する
概略を示す図、第2図は従来の方法による端子ビンの立
設を示す図である。 10・・・グリーンシート 12・・・端子ピン14・
・・凸部      16・・・金ビア導体30・・・
アルミナ基板 32・・・導体パターン 34・・・N メツキ 36・・・ろう付は剤 38・・・端子ピン
FIG. 1 is a diagram schematically showing how pins are erected on a ceramic multilayer substrate according to the present invention, and FIG. 2 is a diagram illustrating how terminal pins are erected by a conventional method. 10... Green sheet 12... Terminal pin 14.
...Convex portion 16...Gold via conductor 30...
Alumina substrate 32...Conductor pattern 34...N Plating 36...Brazing agent 38...Terminal pin

Claims (3)

【特許請求の範囲】[Claims] (1)ガラスセラミック材からなる低温焼成用セラミッ
クから構成したグリーンシートの所定位置に棒状のピン
を立設し、その後低温で焼成を行うことからなり、一部
に凸部を有するピンをプレスの際に打ち込み、ピンの下
に金ビア導体を予め配置し、同時焼成することを特徴と
するセラミック多層基板の製造方法。
(1) A rod-shaped pin is set upright at a predetermined position on a green sheet made of a glass-ceramic material for low-temperature firing, and then fired at a low temperature. A method for manufacturing a ceramic multilayer board, characterized by placing gold via conductors in advance under the pins and firing them at the same time.
(2)金ビア導体として、次の条件: 1 700〜1000℃にて大気中で変質せず硬度も低
下しない、 2 基板の導体である金属体と強固に接合する、を充足
するものを使用する請求項1記載の方法。
(2) Use a gold via conductor that satisfies the following conditions: 1. It does not change in quality or decrease in hardness in the atmosphere at 700 to 1000°C, and 2. It firmly joins to the metal body that is the conductor of the board. 2. The method according to claim 1.
(3)請求項1または2記載の方法により製造されたセ
ラミック多層基板。
(3) A ceramic multilayer substrate manufactured by the method according to claim 1 or 2.
JP24625890A 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same Expired - Fee Related JP3184207B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24625890A JP3184207B2 (en) 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24625890A JP3184207B2 (en) 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH04125994A true JPH04125994A (en) 1992-04-27
JP3184207B2 JP3184207B2 (en) 2001-07-09

Family

ID=17145848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24625890A Expired - Fee Related JP3184207B2 (en) 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3184207B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284836A (en) * 1997-04-08 1998-10-23 Hitachi Ltd Collectively laminated ceramic wiring board and its manufacture

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102466911B1 (en) * 2020-09-28 2022-11-14 주식회사 디아이티 Multilayer ceramic substrate having connecting means with frame and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284836A (en) * 1997-04-08 1998-10-23 Hitachi Ltd Collectively laminated ceramic wiring board and its manufacture

Also Published As

Publication number Publication date
JP3184207B2 (en) 2001-07-09

Similar Documents

Publication Publication Date Title
JP2573225B2 (en) Electronic component manufacturing method
JP3528037B2 (en) Manufacturing method of glass ceramic substrate
JPS6376279A (en) Connector and semiconductor package construction using the same the same
JPH04125994A (en) Multilayered ceramic substrate and manufacture thereof
JP3139758B2 (en) Ceramic multilayer substrate and method of manufacturing the same
JP3139759B2 (en) Ceramic multilayer substrate and method of manufacturing the same
JP3143467B2 (en) Ceramic multilayer substrate and method of manufacturing the same
JPH04125993A (en) Multilayered ceramic substrate and manufacture thereof
JP3075536B2 (en) Ceramic multilayer substrate and method of manufacturing the same
JPS63271994A (en) Ceramic wiring substrate
JPH0283995A (en) Ceramic multilayer circuit board and its applications
JP2898721B2 (en) Ceramic multilayer substrate and method of manufacturing the same
JP2001072473A (en) Production of ceramic substrate
JP2001015930A (en) Multilayer printed wiring board and manufacture thereof
JP2002076628A (en) Manufacturing method of glass ceramic substrate
JP3493294B2 (en) Circuit board
JP3225965B2 (en) Method for manufacturing low-temperature fired circuit board
JP2734404B2 (en) Ceramic wiring board and method of manufacturing the same
JP3905991B2 (en) Glass ceramic wiring board
JPS60137884A (en) Manufacture of ceramic multi-layer wiring circuit substrate
JPH0945844A (en) Jointed structure of low-temperature firing ceramic board with external i/o pin and manufacture thereof
JPS60132393A (en) Ceramic multilayer circuit board and method of producing same
JPH0210597B2 (en)
JPH03224254A (en) Manufacture of ceramic circuit board
JPH04199697A (en) Multilayer wiring board and hybrid ic provided therewith

Legal Events

Date Code Title Description
S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090427

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090427

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100427

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees