JPH03218060A - Inverter - Google Patents

Inverter

Info

Publication number
JPH03218060A
JPH03218060A JP2014206A JP1420690A JPH03218060A JP H03218060 A JPH03218060 A JP H03218060A JP 2014206 A JP2014206 A JP 2014206A JP 1420690 A JP1420690 A JP 1420690A JP H03218060 A JPH03218060 A JP H03218060A
Authority
JP
Japan
Prior art keywords
substrate
inverter
power
elements
ceramic piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2014206A
Other languages
Japanese (ja)
Other versions
JP2735920B2 (en
Inventor
Katsumi Okawa
克実 大川
Akira Kazami
風見 明
Susumu Ota
太田 晋
Sumio Ishihara
石原 純夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2014206A priority Critical patent/JP2735920B2/en
Publication of JPH03218060A publication Critical patent/JPH03218060A/en
Application granted granted Critical
Publication of JP2735920B2 publication Critical patent/JP2735920B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

Abstract

PURPOSE:To form a very thin inverter for high power use by a method wherein inverter main circuits for high power use and driving circuits to make the circuits drive are formed on the same substrate. CONSTITUTION:Holes 2a, in which the surface of a metal substrate 1 is exposed, are provided in a thin insulating resin layer 2 sticked on the substrate 1 and power elements 5, which are used as main circuits of an inverter, are mounted on the substrate 1 exposed in the holes 2a via ceramic pieces 4. Moreover, a plurality of elements 6 for small signal use for making the main circuits drive are arranged on other regions. Thereby, the heat dissipation property of the elements 5 can be remarkably enhanced. Moreover, elements 6 for small signal use can be fixed on the same substrate. As a result, an inverter circuit where the main circuits for high power are integrated with driving circuits is obtained. Moreover, by connecting a conductor layer 3' provided on the peripheral end sides of the holes with spot facing parts 9 provided in the vicinity of the layer 3', self noise of the elements 5 in the main circuits can be suppressed at the time of switching.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はインバータの主回路とその主回路を駆動させる
駆動回路とが同一基板上に構成されたイン/<−夕装U
:mし、特にハイパワーのインバータ装置に関する。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to an inverter in which a main circuit of an inverter and a drive circuit for driving the main circuit are constructed on the same substrate.
:m, and particularly relates to high-power inverter devices.

(口)従来の技術 従来から、パワー用の半導体素子を搭載したパワー用の
集積回路はその動作中に発生する熱放散を考慮していわ
ゆるヒートシンク(銅板)を使用する方式が多用されて
いる。この方式のパワー用の集積回路の中には回路パタ
ーンを一面に形成し、他面に銅よりなる熱伝導層を設け
たアルミナセラミック板を前記ヒートシンク(以後放熱
板と呼称する)に半田付して一体とする型がある。この
型のパワー用集積回路は第4図に示す如く、アルミナセ
ラミックス基板(51)の一生面に導電性のよい銅で回
路パターン(52》を形成し、その一部であるパッド部
(52’ )にパワー用半導体素子(53)をろう材に
よって固着する。ところで、銅の回路パターン(52》
は溶射法、メッキ法、メタライズ法、印刷法および蒸着
法の単独又はその組合せで形成するか、あるいは銅板を
ろう付する方法で固定し大軍流の回路パターン(52)
が形成される.半導体素子(53)の電極と前記回路パ
ターン〈52)の一部を構成するパッド部(52′)を
導電性金属細線(61)で接続し、前記アルミナセラミ
ックス基板(5l》の他面に被着した銅からなる熱伝導
層(54)と放熱板(55)とを半田層によって固着し
ていた。
(Example) Conventional Technology Conventionally, power integrated circuits equipped with power semiconductor elements have often used a so-called heat sink (copper plate) in consideration of heat dissipation generated during operation. In this type of power integrated circuit, an alumina ceramic plate with a circuit pattern formed on one side and a thermally conductive layer made of copper on the other side is soldered to the heat sink (hereinafter referred to as a heat sink). There is a type that integrates both. As shown in Fig. 4, this type of power integrated circuit has a circuit pattern (52) made of highly conductive copper formed on the entire surface of an alumina ceramic substrate (51), and a pad portion (52') that is a part of the circuit pattern (52). ) is fixed with a brazing material to the power semiconductor element (53).By the way, the copper circuit pattern (52)
is formed by thermal spraying, plating, metallization, printing, and vapor deposition methods alone or in combination, or fixed by brazing a copper plate to form a popular circuit pattern (52).
is formed. The electrode of the semiconductor element (53) and the pad portion (52') constituting a part of the circuit pattern (52) are connected with a thin conductive metal wire (61), and the other surface of the alumina ceramic substrate (5l) is covered with the electrode. The heat conductive layer (54) made of deposited copper and the heat sink (55) were fixed together by a solder layer.

斯る放熱板(55)上には上述したパワー回路が形成さ
れたアルミナセラミックス基板(51)が複数個固着搭
載され、各アルミナセラミックス基板ク51)上に形成
されたパッド部(52’)を上述した細線で接続し所定
のパワー回路、例えばインバータ回路のパワ一部分を集
積回路化してパワーモジュールICとして使用されてい
る. (八)発明が解決しようとする課題 第4図の如き、パワーモジュールICではインバータ装
置のパワ一部分となる主回路のみが構成きれているため
に大電流化として見ればその効果は犬である。しかしな
がら、第4図のパワーモジュールでは上述した如く、イ
ンバータの主回路のみしか形成されておらずその主回路
を駆動させる駆動回路は別部品での外付となりシステム
として見れば大型となる問題がある。
A plurality of alumina ceramic substrates (51) on which the above-mentioned power circuits are formed are fixedly mounted on the heat sink (55), and pad portions (52') formed on each alumina ceramic substrate (51) are fixedly mounted on the heat sink (55). A predetermined power circuit, for example, a part of the power of an inverter circuit, is connected using the above-mentioned thin wires and integrated into an integrated circuit, which is used as a power module IC. (8) Problems to be Solved by the Invention As shown in FIG. 4, in the power module IC, only the main circuit which is a part of the power of the inverter device is configured, so the effect of increasing the current is small. However, as mentioned above, in the power module shown in Fig. 4, only the main circuit of the inverter is formed, and the drive circuit that drives the main circuit is a separate external component, resulting in a large system. .

また、第4図の如き、構造ではセラミックス基板を使用
するために大竃流用のパターンは形成できるが小信号用
のファインパターンを形成することが困難であるためイ
ンバータのハイパワー用主回路と駆動回路とを同一基板
上に形成することが不可能であった。
In addition, since the structure shown in Figure 4 uses a ceramic substrate, it is possible to form a pattern for a large inverter, but it is difficult to form a fine pattern for a small signal. It was impossible to form both circuits on the same substrate.

(二)課題を解決するための手段 本発明は上述した課題に鑑みて為されたものであり、金
属基板と前記基板上に貼着され且つ前記基板表面を露出
させる複数の孔が設けられた絶縁薄層と前記絶縁薄層上
に形成された所望形状の導寛路と前記孔で露出した前記
基板上に固着された熱抵抗比の小さいセラミックス片と
前記セラミックス片上に固着され前記導電路と接続され
たパワーインバータの主回路となる複数のパワー素子と
前記主回路を駆動させ且つ前記基板上に配置された駆動
回路となる複数の小信号回路素子とを具備し、前記孔周
端辺上に環状の導体層を形成し、前記導体層の近傍に前
記基板表面を露出させるザグリ部を形成し、前記導体層
と前記ザグリ部によって露出された基板とを接続したこ
とを特徴とする。
(2) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a metal substrate and a plurality of holes attached to the substrate and exposing the surface of the substrate. an insulating thin layer, a conductive path of a desired shape formed on the insulating thin layer, a ceramic piece with a low thermal resistance ratio fixed on the substrate exposed through the hole, and a conductive path fixed on the ceramic piece. It comprises a plurality of power elements serving as a main circuit of the connected power inverter and a plurality of small signal circuit elements serving as a drive circuit that drives the main circuit and is disposed on the substrate, and is arranged on the peripheral edge of the hole. The present invention is characterized in that an annular conductor layer is formed in the conductor layer, a counterbore portion exposing the substrate surface is formed near the conductor layer, and the conductor layer and the substrate exposed by the counterbore portion are connected.

(ネ)作用 この様に本発明に依れば、金属基板上に貼着する絶縁樹
脂薄層に基板表面を露出させる孔を設け、その孔で露出
された基板上にセラミックス片を介してインバータの主
回路となるパワー素子を搭載し、他の領域上に主回路を
駆動させる複数の/JX信号用素子を配置することによ
り、パワー素子の熱放散性を極めて向上させることがで
き且つ同一基板上に小信号用素子が固着できる。その結
果、ハイパワー用の主回路と駆動回路とを一体化したイ
ンバータ装置を提供することができる。
(f) Function As described above, according to the present invention, a hole is provided in the thin insulating resin layer adhered to a metal substrate to expose the surface of the substrate, and an inverter is placed on the substrate exposed through the hole through a ceramic piece. By mounting a power element that serves as the main circuit of the device and arranging multiple /JX signal elements that drive the main circuit on other areas, the heat dissipation performance of the power element can be greatly improved. A small signal element can be fixed on top. As a result, it is possible to provide an inverter device that integrates a high-power main circuit and a drive circuit.

また、孔周端辺に設けられた導体層と、その導体層の近
傍に設けられたザグリ部とを接続することにより、主回
路のパワー素子のスイッチング時の自己ノイズを抑制す
ることができる。
Furthermore, by connecting the conductor layer provided around the peripheral edge of the hole and the counterbore portion provided in the vicinity of the conductor layer, self-noise during switching of the power element of the main circuit can be suppressed.

(へ)実施例 以下に第1図および第2図に示した実施例に基ついて本
発明を詳細に説明する。
(f) Examples The present invention will be explained in detail below based on the examples shown in FIGS. 1 and 2.

第1図は本発明のインバータ装置を示す平面図であり、
第2図は第1図のI−I断面図である.第1図および第
2図に示す如く、本発明のインバータ装置は、金属基板
(1)と、その基板一生面上に貼着された複数の孔(2
a)を有した絶縁薄層ク2)と、絶縁薄層(2)上に形
成された所望形状の導電路(3)と、孔(2a)によっ
て露出された基板(1〉上に固着されたセラミックス片
(4)と、セラミックス片(4)を囲み且つ孔(2a)
の周端部の絶縁薄層(2)上に形成された導体層(3゛
)と、その導体層(3′)の近傍に設けられたザグリ部
(9)と、セラミックス片(4)上に固着されたパワー
素子(5)と、導軍路(3)上に固着された複数の小信
号素子(6)とから構成されている。
FIG. 1 is a plan view showing an inverter device of the present invention,
Figure 2 is a sectional view taken along line II in Figure 1. As shown in FIGS. 1 and 2, the inverter device of the present invention includes a metal substrate (1) and a plurality of holes (2) attached on the surface of the substrate.
a), a conductive path (3) of a desired shape formed on the insulating thin layer (2), and a conductive path (3) of a desired shape formed on the insulating thin layer (2), and fixed on the substrate (1) exposed by the hole (2a). a ceramic piece (4), and a hole (2a) surrounding the ceramic piece (4).
A conductor layer (3゛) formed on the insulating thin layer (2) at the peripheral edge of , a counterbore (9) provided near the conductor layer (3'), and a ceramic piece (4) It consists of a power element (5) fixed on the guide path (3) and a plurality of small signal elements (6) fixed on the guide path (3).

金属基板(1)として2〜5■厚の銅基板が用いられる
。その銅基板の表面には銅の酸化および機械的強度を増
すために無電解メッキによってニッケルメッキ膜(1a
)がコーティングされている。
A copper substrate with a thickness of 2 to 5 cm is used as the metal substrate (1). The surface of the copper substrate is coated with a nickel plating film (1a) by electroless plating to increase copper oxidation and mechanical strength.
) is coated.

基板(1)の一生面に貼着される絶縁薄層(2)として
は、例えばエボキシあるいはポリイミド樹詣が用いられ
、その所定位置には複数の孔(2a)が設けられている
。孔(2a)は基板(1)に貼着される前にプレス等の
手段によってあらかじめ形成される.基板ク1)上に絶
縁薄層(2)を貼着すると複数の孔(2a)によって基
板(1)の表面のみが露出されることになる.その孔(
2a)は基板(1)の略中央部に配置する様に設けられ
る。本実施例では三相インバータを用いているために孔
(2a)は6個形成されることになる。
For example, epoxy or polyimide resin is used as the insulating thin layer (2) that is adhered to the entire surface of the substrate (1), and a plurality of holes (2a) are provided at predetermined positions. The holes (2a) are formed in advance by means such as pressing before being attached to the substrate (1). When the thin insulating layer (2) is pasted onto the substrate (1), only the surface of the substrate (1) is exposed through the plurality of holes (2a). The hole (
2a) is provided so as to be placed approximately at the center of the substrate (1). In this embodiment, since a three-phase inverter is used, six holes (2a) are formed.

斯る絶縁薄層(2)上には銅箔より成る所望形状の導電
路(3)が形成される。ところで、銅箔と絶縁薄層(2
)とは、あらかじめ接着剤で一体化されており、絶縁薄
層(2)を基板(1)上に貼着する際に銅箔も同時に貼
着される。導電路(3)は第1図から明らかな如く、パ
ワー用の導電路(3a)と小信号用の導電路(3b)と
が形成される。パワー用の導電路(3a)は孔(2a)
間を延在する様に形成され、その延在された基板(1)
の周端辺にはパワー用リード端子が固着されるパワー用
パツド〈3C)が形成される。一方、小信号用の導電路
(3b)はパワー用の導電路(3a)を挾む様に基板<
1)の両端部の領域に形成され、パワー用パッド(3C
)の対向辺側に導電路〈3b)が延在され小信号用のパ
ッド(3d)が形成される。また、パワー用の導電路(
3a)上には大電流を対応とするために表面がNiメッ
キ処理された銅板(7)を本実施例では固着している。
A conductive path (3) of a desired shape made of copper foil is formed on the insulating thin layer (2). By the way, copper foil and insulating thin layer (2
) are integrated in advance with an adhesive, and when the thin insulating layer (2) is pasted onto the substrate (1), the copper foil is also pasted at the same time. As is clear from FIG. 1, the conductive path (3) includes a power conductive path (3a) and a small signal conductive path (3b). The power conductive path (3a) is the hole (2a)
The extended substrate (1) is formed to extend between
A power pad (3C) to which a power lead terminal is fixed is formed on the peripheral edge of the power pad (3C). On the other hand, the small signal conductive path (3b) is placed between the substrates and the power conductive path (3a).
1) is formed in the regions at both ends of the power pad (3C
), a conductive path (3b) is extended to form a small signal pad (3d). In addition, the conductive path for power (
3a) In this embodiment, a copper plate (7) whose surface is plated with Ni is fixed on top of the plate (7) in order to handle a large current.

更に本実施例で形成される小信号用の導電路(3b)は
30〜100μクラスのファインパターンが形成される
Furthermore, the conductive path (3b) for small signals formed in this embodiment has a fine pattern of 30 to 100 μ class.

ところで、孔(2a)の周端部の絶縁薄層(2)上には
後述するセラミ/クス片(4)を取り囲む様に導体層ク
3′)が形成される。この導体層(3゛)は導電路(3
)と同一材料である銅箔により形成され、しかも同一工
程で形成される。また、この導体層(3゛)は製造工程
において不可欠なものとなり、本発明ではその導体層(
3゛)を積極的に利用したものである。
By the way, a conductor layer 3') is formed on the insulating thin layer (2) at the peripheral end of the hole (2a) so as to surround a ceramic/gloss piece (4) to be described later. This conductor layer (3゛) is a conductive path (3゛).
) is made of the same material, copper foil, and is formed in the same process. In addition, this conductor layer (3゛) becomes essential in the manufacturing process, and in the present invention, the conductor layer (3゛) is essential in the manufacturing process.
3)).

絶縁薄層(2)と導寛路(3〉を形成する銅箔とは上述
した様にあらかじめ一体化されているため、その一体化
されたものに孔(2a)を形成し基板(1)上に貼着し
、銅箔をエッチングする際のレジスト膜を孔(2a)で
露出した基板(1)上のみに付着塗布することは非常に
困難である。そこで孔(2a》で露出した基板(1)上
にレジスト膜を塗布させる場合、孔(2a)の周辺の領
域を才−バラップさせる必要性がある。この結果、導電
路(3)をエッチング形成する際に孔(2a)を取り囲
む導体層(3゛)が形成される。また、導体層(3′)
上には表面保護等の目的のためメッキ処理が行われてい
る。
Since the insulating thin layer (2) and the copper foil forming the guiding path (3) are integrated in advance as described above, the hole (2a) is formed in the integrated material and the substrate (1) is formed. It is very difficult to apply a resist film on only the substrate (1) exposed through the hole (2a) when etching the copper foil. When applying a resist film on (1), it is necessary to overlap the area around the hole (2a).As a result, when forming the conductive path (3) by etching, the area surrounding the hole (2a) A conductor layer (3') is formed.A conductor layer (3') is also formed.
The top is plated to protect the surface.

一方、導体層(3゛)の近傍には基板(1)の表面を露
出させるザグリ部(9)が設けられ、そのザグリ部(9
)によって露出された基板(1)と前述した導体層(3
′)とをアルミニウム線の如き接続手段を用いて竃気的
に接続する。この構造に依れば、導体層(3′)と基板
(1)とがアースされることになり、導体層ク3′)に
よって囲まれた後述するパワー素子(5)から発生する
自己ノイズを吸収することができ、他の回路素子、特に
小信号系の素子による悪影響を著しく抑制することがで
きるものである。
On the other hand, a counterbore (9) is provided near the conductor layer (3) to expose the surface of the substrate (1).
) exposed by the substrate (1) and the aforementioned conductor layer (3
') are electrically connected using a connecting means such as an aluminum wire. According to this structure, the conductor layer (3') and the substrate (1) are grounded, and the self-noise generated from the power element (5), which will be described later, is surrounded by the conductor layer (3'). It is possible to significantly suppress the adverse effects caused by other circuit elements, especially small signal type elements.

上述した孔(2a)によって露出された基板(1)上に
は熱抵抗比の小さいセラミックス片(4)を介してパワ
ー素子(5)が基板(1)上に搭載される。
A power element (5) is mounted on the substrate (1) exposed through the above-mentioned hole (2a) via a ceramic piece (4) having a small thermal resistance ratio.

熱抵抗比の小さいセラミックス片(4)として、例えば
窒化アルミニウム、窒化ホウ素、ベリリア等の材料があ
るが、本実施例でもっとも一般的である窒化アルミニウ
ムを用いるものとする。第3図はそのセラミックス片ク
4〉を示す断面図であり、その上下面には酸化鋼を介し
て銅板が固着された導体層(4a)が形成されている。
As the ceramic piece (4) having a low thermal resistance ratio, there are materials such as aluminum nitride, boron nitride, and beryllia, but in this embodiment, aluminum nitride, which is the most common material, is used. FIG. 3 is a sectional view showing the ceramic piece 4〉, and a conductor layer (4a) to which a copper plate is fixed via oxidized steel is formed on the upper and lower surfaces thereof.

従って基板(1)上には半田によって固着できることが
可能となる。また、セラミックス片(4)上に固着され
るパワー素子<5)も半田によって固着搭載されること
はいうまでもない。また、上述したセラミックス片(4
)の上下面に形成された導体層(4a)の表面には図示
されないがニッケルメッキ膜が形成されている. セラミックス片(4)上に固着したパワー素子(5)ト
ハワー用の導電路(3a)とはアルミニウム線によって
ボンディング接続しインバータの主回路となる様にブリ
ッジ接続を行う。本実施例ではセラミックス片(4)が
孔(2a)によって独立状態であるために、上述した主
回路を構成すべきブリッジ回路を形成するためにセラミ
ックス片<4)とパワー用の導電路(3a)とを接続し
てインハータの主回路を形成することができる。
Therefore, it becomes possible to fix it onto the substrate (1) by soldering. Further, it goes without saying that the power element <5) fixed on the ceramic piece (4) is also fixedly mounted by solder. In addition, the above-mentioned ceramic piece (4
Although not shown, a nickel plating film is formed on the surface of the conductor layer (4a) formed on the upper and lower surfaces of the conductor layer (4a). The power element (5) fixed on the ceramic piece (4) and the power conductive path (3a) are connected by bonding using aluminum wires, and a bridge connection is made to form the main circuit of the inverter. In this embodiment, since the ceramic piece (4) is independent by the hole (2a), the ceramic piece <4) and the power conductive path (3a) are used to form the bridge circuit that constitutes the main circuit described above. ) can be connected to form the main circuit of the inharter.

セラミックス片(4)の上下面には上述した如く、導体
層(4a)が形成されているため、セラミックス片(4
)上に固着されたパワー素子(5〉、例えばパワートラ
ンジスタのコしクタが導体層(4a)と共通となり、導
体層(4a)とパワー用の導電路(3a)とをワイヤ線
等で接続することによりパワーインバータの主回路を構
成することができる。導体層(4a)とパワー用の導電
路(3a)とはアルミニウム線でボンディング接続され
るが、このとき夫々の表面にはニッケルメッキ膜が形成
されているために何んら問題はない。
As described above, the conductor layer (4a) is formed on the upper and lower surfaces of the ceramic piece (4).
) fixed on the power element (5>, for example, the connector of a power transistor becomes common with the conductor layer (4a), and connects the conductor layer (4a) and the power conductive path (3a) with a wire etc. By doing so, the main circuit of the power inverter can be constructed.The conductor layer (4a) and the power conductive path (3a) are connected by bonding with aluminum wire, but at this time, a nickel plating film is coated on the surface of each. There is no problem because it is formed.

一方、絶縁薄層(2〉上に形成された小信号用の導電路
(3b)上にはトランジスタ、チップ抵抗、チップコン
デンサー、ダイ才一ド等の発熱を有さない複数の小信号
用素子(6)が搭載され、インバータの主回路を駆動す
べき駆動回路および保護回路が構成される。
On the other hand, on the small signal conductive path (3b) formed on the insulating thin layer (2), there are a plurality of small signal elements that do not generate heat, such as transistors, chip resistors, chip capacitors, and die capacitors. (6) is installed, and constitutes a drive circuit and a protection circuit that drive the main circuit of the inverter.

斯る本発明に依れば、金属基板上に貼着する絶縁樹脂薄
層に基板表面を露出させる孔を設け、その孔で露出され
た基板上に熱抵抗比の小さいセラミックス片を介してイ
ンバータの主回路となるパワー素子を搭載し、他の領域
上に主回路を駆動させる複数の小信号用素子を配置する
ことにより、パワー素子の熱放散性を極めて向上させる
ことができる。また、同一基板上に小信号用素子が固着
できるので、ハイパワー用の主回路と駆動回路とを一体
化したインバータ装置を提供することができる. また、孔(2a)の周端辺、即ち、パワー素子(5)を
取り囲む様に導体層(3゛)を設け、その導体層(3′
)とザグリ部(9)によって露出された基板(1)とを
接続することにより、パワー素子(5)のスイッチング
の際の自己ノイズを抑制することができる。
According to the present invention, a hole is provided in a thin insulating resin layer adhered to a metal substrate to expose the surface of the substrate, and an inverter is installed on the substrate exposed through the hole via a ceramic piece having a low thermal resistance ratio. By mounting a power element serving as a main circuit and arranging a plurality of small signal elements for driving the main circuit on other areas, the heat dissipation performance of the power element can be greatly improved. Furthermore, since small signal elements can be fixed on the same substrate, it is possible to provide an inverter device that integrates a high power main circuit and a drive circuit. Further, a conductor layer (3') is provided around the peripheral edge of the hole (2a), that is, surrounding the power element (5), and the conductor layer (3') is provided so as to surround the power element (5).
) and the substrate (1) exposed by the counterbore (9), it is possible to suppress self-noise during switching of the power element (5).

(ト)発明の効果 以上に詳述した如く、本発明に依れば、同一基坂上にハ
イパワー用のインバータ主回路と、その回路を駆動させ
る駆動回路とを形成することができることにより、極め
て薄型のハイパワー用のインバータ装置を提供すること
ができる。
(G) Effects of the Invention As detailed above, according to the present invention, it is possible to form a high-power inverter main circuit and a drive circuit for driving the circuit on the same base plate, resulting in extremely A thin high-power inverter device can be provided.

また、本発明で用いるセラミックス片上にはパワー素子
のみが固着されているため、安価でしかも同一基板上に
小信号用のファインパターンを形成することができる。
Further, since only the power element is fixed on the ceramic piece used in the present invention, it is possible to form a fine pattern for small signals on the same substrate at low cost.

更に、本発明ではパワー素子の自己ノイズを抑制するこ
とができるため、その結果、周辺の小信号系の回路素子
が安定して動作し特性の優れたインバータ装置を実現で
きるものである。
Further, according to the present invention, since the self-noise of the power element can be suppressed, as a result, the peripheral small-signal circuit elements can operate stably, and an inverter device with excellent characteristics can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す平面図、第2図は第1図
のI−I断面図、第3図は本実施例で用いるセラミック
ス片を示す断面図、第4図は従来例を示す要部断面図で
ある。 (1)・・・金属基板、 (2)・・・絶縁薄層、 (
2a)・・・孔、 ク3)・・・導電路、 (3′)・
・・導体層、 ク4)・・・セラミックス片、 ク5)
・・・パワー素子、 (6)小信号素子、 (9)・・・ザグリ部。
Fig. 1 is a plan view showing an embodiment of the present invention, Fig. 2 is a sectional view taken along the line II in Fig. 1, Fig. 3 is a sectional view showing a ceramic piece used in this embodiment, and Fig. 4 is a conventional example. FIG. (1)...metal substrate, (2)...insulating thin layer, (
2a)...hole, ku3)...conducting path, (3')...
...Conductor layer, 4)...Ceramic piece, 5)
...power element, (6) small signal element, (9) ... counterbore part.

Claims (6)

【特許請求の範囲】[Claims] (1)金属基板と 前記基板上に貼着され且つ前記基板表面を露出させる複
数の孔が設けられた絶縁薄層と 前記絶縁薄層上に形成された所望形状の導電路と 前記孔で露出した前記基板上に固着された熱抵抗比の小
さいセラミックス片と 前記セラミックス片上に固着され前記導電路と接続され
たパワーインバータの主回路となる複数のパワー素子と 前記主回路を駆動させ且つ前記基板上に配置された駆動
回路となる複数の小信号回路素子とを具備し、 前記孔周端辺上に環状の導体層を形成し、前記導体層の
近傍に前記基板表面を露出させるザグリ部を形成し、前
記導体層と前記ザグリ部によって露出された基板とを接
続したことを特徴とするインバータ装置。
(1) A metal substrate, an insulating thin layer attached to the substrate and provided with a plurality of holes that expose the surface of the substrate, and a conductive path of a desired shape formed on the insulating thin layer and exposed through the holes. a ceramic piece having a low thermal resistance ratio fixed on the substrate, a plurality of power elements fixed on the ceramic piece and connected to the conductive path and forming a main circuit of a power inverter, and driving the main circuit; a plurality of small signal circuit elements disposed above and serving as a drive circuit, a ring-shaped conductor layer is formed on the peripheral edge of the hole, and a counterbore portion exposing the substrate surface near the conductor layer. and connecting the conductive layer and the substrate exposed by the counterbore.
(2)前記金属基板として銅基板を用いたことを特徴と
する請求項1記載のインバータ装置。
(2) The inverter device according to claim 1, wherein a copper substrate is used as the metal substrate.
(3)前記セラミックス片として窒化アルミニウム片、
窒化ホウ素片、炭化ケイ素片あるいはベリリア片を用い
たことを特徴とする請求項1記載のインバータ装置。
(3) an aluminum nitride piece as the ceramic piece;
2. The inverter device according to claim 1, wherein boron nitride pieces, silicon carbide pieces, or beryllia pieces are used.
(4)前記導電路として銅箔を用いたことを特徴とする
請求項1記載のインバータ装置。
(4) The inverter device according to claim 1, wherein copper foil is used as the conductive path.
(5)前記パワー素子はブリッジ接続されていることを
特徴とする請求項1記載のインバータ装置。
(5) The inverter device according to claim 1, wherein the power elements are bridge-connected.
(6)前記セラミックス片の両面には導体層が設けられ
ていることを特徴とする請求項1記載のインバータ装置
(6) The inverter device according to claim 1, wherein conductor layers are provided on both sides of the ceramic piece.
JP2014206A 1990-01-23 1990-01-23 Inverter device Expired - Fee Related JP2735920B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014206A JP2735920B2 (en) 1990-01-23 1990-01-23 Inverter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014206A JP2735920B2 (en) 1990-01-23 1990-01-23 Inverter device

Publications (2)

Publication Number Publication Date
JPH03218060A true JPH03218060A (en) 1991-09-25
JP2735920B2 JP2735920B2 (en) 1998-04-02

Family

ID=11854635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014206A Expired - Fee Related JP2735920B2 (en) 1990-01-23 1990-01-23 Inverter device

Country Status (1)

Country Link
JP (1) JP2735920B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03227045A (en) * 1990-02-01 1991-10-08 Fuji Electric Co Ltd Power module
US5444297A (en) * 1992-06-17 1995-08-22 Mitsubishi Denki Kabushiki Kaisha Noise resistant semiconductor power module
JP2003501812A (en) * 1999-05-31 2003-01-14 ティーワイシーオー エレクトロニクス ロジスティック エイジー Intelligent power module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03227045A (en) * 1990-02-01 1991-10-08 Fuji Electric Co Ltd Power module
US5444297A (en) * 1992-06-17 1995-08-22 Mitsubishi Denki Kabushiki Kaisha Noise resistant semiconductor power module
JP2003501812A (en) * 1999-05-31 2003-01-14 ティーワイシーオー エレクトロニクス ロジスティック エイジー Intelligent power module

Also Published As

Publication number Publication date
JP2735920B2 (en) 1998-04-02

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