JPS6041853B2 - electronic circuit equipment - Google Patents

electronic circuit equipment

Info

Publication number
JPS6041853B2
JPS6041853B2 JP53079896A JP7989678A JPS6041853B2 JP S6041853 B2 JPS6041853 B2 JP S6041853B2 JP 53079896 A JP53079896 A JP 53079896A JP 7989678 A JP7989678 A JP 7989678A JP S6041853 B2 JPS6041853 B2 JP S6041853B2
Authority
JP
Japan
Prior art keywords
electronic component
main surface
electronic circuit
metal layer
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53079896A
Other languages
Japanese (ja)
Other versions
JPS558025A (en
Inventor
強 白ケ澤
正晴 野依
博昭 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53079896A priority Critical patent/JPS6041853B2/en
Publication of JPS558025A publication Critical patent/JPS558025A/en
Publication of JPS6041853B2 publication Critical patent/JPS6041853B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は電子回路装置に関し、とくに放熱効果の大な
るハイパワーの高密度実装薄形電子回路装置を歩留り良
く製造できる構造を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic circuit devices, and in particular provides a structure capable of manufacturing high-power, high-density packaging thin electronic circuit devices with a high heat dissipation effect with good yield.

ポリイミドフィルムとメタルフレームを組合せた多層
配線構造によるＬＳＩ高密度実装技術を本出願人はすで
に提案している。The applicant has already proposed a high-density LSI mounting technology using a multilayer wiring structure combining a polyimide film and a metal frame.

すなわち、これは高密度実装を実現するために、薄型耐
熱性絶縁フィルム上に形成された微細スルーホール（貫
通孔）を介してフィルムの一方の主面に接着されたＬＳ
Ｉ電極パッドとフィルムの他方の主面に形成された配線
を直接接続するワイヤレスボンディング技術を用い、さ
らに多層配線とするためにフィルムの一方の主面に形成
されたメタルフレームを用いたもので、最小線幅、間隔
が５０μ程度とてき、ＬＳＩチップ上でも配線形成を可
能にしたもので、高密度でかつ極めて薄い小型の電子回
路実装体を実現したものである。この従来の装置を第１
図に示す。 第１図においてポリイミドフィルム等の絶
縁樹脂フィルム１の第１主面上に形成された導体配線３
と１の第２の主面に接着層６により電子部品（たとえば
半導体集積回路素子）４が取付けられており、更に４の
表面電極５は１に形成された貫通孔２を介して３と電気
的に接続がなされ高密度１実装薄形電子回路装置が構成
されている。In other words, in order to achieve high-density packaging, the LS is bonded to one main surface of the thin heat-resistant insulating film through fine through holes formed on the film.
It uses wireless bonding technology to directly connect the I electrode pad and the wiring formed on the other main surface of the film, and also uses a metal frame formed on one main surface of the film to create multilayer wiring. The minimum line width and spacing are approximately 50 microns, making it possible to form wiring even on LSI chips, and realizing a compact electronic circuit package with high density and extremely thinness. This conventional device is the first
As shown in the figure. In FIG. 1, conductor wiring 3 formed on the first main surface of an insulating resin film 1 such as a polyimide film
An electronic component (for example, a semiconductor integrated circuit element) 4 is attached to the second main surface of and 1 by an adhesive layer 6, and a surface electrode 5 of 4 is electrically connected to 3 through a through hole 2 formed in 1. A high-density, single-package thin electronic circuit device is constructed by making connections between the two.

本電子回路装置の問題点は、半導体チップ、チップ抵抗
等の電子部品４が熱伝導率の低い絶縁樹脂フィルム１に
固着されているために放熱効果が悪く信頼性の低下をき
たし、特にパワー素子を用いたハイ・パワーの高密度実
装薄形電子回路の実現が困難であつた。 従来、この問
題解決策として第１図に示す如く前記電子部品４のヒー
トシンクとなる金属層７を電子部品基体部か接着層６に
至る領域に蒸着等により形成し、電子部品の放熱効果を
高める試みが行なわれている。The problem with this electronic circuit device is that electronic components 4 such as semiconductor chips and chip resistors are fixed to the insulating resin film 1 with low thermal conductivity, which results in poor heat dissipation and reduced reliability, especially in power elements. It has been difficult to realize high-power, high-density, thin electronic circuits using Conventionally, as a solution to this problem, as shown in FIG. 1, a metal layer 7 serving as a heat sink of the electronic component 4 is formed by vapor deposition or the like on the electronic component base portion or in a region extending to the adhesive layer 6, thereby enhancing the heat dissipation effect of the electronic component. An attempt is being made.

しかるにこの方法には、（１）ヒートシンクとなる金属
層の面積は実装電子回路装置の平面面積に制限され大き
な放熱効果を得ることができない。However, in this method, (1) the area of the metal layer serving as a heat sink is limited to the plane area of the mounted electronic circuit device, and a large heat dissipation effect cannot be obtained.

（２）第２図ａに示す如く、絶縁樹脂フィルム１の裏面
上の絶縁接着層６の表面と電子部品４の基体部の裏面間
の段差が大きい為に、電子部品４の端部８において蒸着
金属層７が段切れを起こし、発熱体となる電子部品４と
ヒートシンクとなる蒸着金属層７を効果的に接続する事
が困難である。(2) As shown in FIG. 2a, since there is a large level difference between the surface of the insulating adhesive layer 6 on the back surface of the insulating resin film 1 and the back surface of the base portion of the electronic component 4, the end portion 8 of the electronic component 4 The vapor-deposited metal layer 7 is broken, making it difficult to effectively connect the electronic component 4 serving as a heating element and the vapor-deposited metal layer 7 serving as a heat sink.

（３）実装する複数の電子部品基体部相互の絶縁の為に
はマスク蒸着、又は全面蒸着後のフォトエッチに依り金
属層７のパターン形式が必要であるが、前述の如く段差
が大である為に精度良くパターンを形成する事が困難で
ある。(3) In order to insulate the multiple electronic component base parts to be mounted from each other, it is necessary to pattern the metal layer 7 by mask vapor deposition or photoetching after full surface vapor deposition, but as mentioned above, the steps are large. Therefore, it is difficult to form a pattern with high precision.

（４）第２図ｂのごとく、絶縁樹脂フィルムにピンホー
ル９が存在する場合は金属導体配線３と蒸着金属層７が
短絡し、所望の電気特性を有する薄形電子回路を得る事
が出来ない。(4) As shown in Fig. 2b, if a pinhole 9 exists in the insulating resin film, the metal conductor wiring 3 and the vapor-deposited metal layer 7 will be short-circuited, making it impossible to obtain a thin electronic circuit with desired electrical characteristics. do not have.

本発明はこのような問題に鑑み、放熱効果が極めてすぐ
れたかつ放熱用金属層を容易にかつ歩留り良く得ること
のてきる電子回路装置を実現したもので、本発明の構成
を第３図に示す実施例を用いて説明する。In view of these problems, the present invention has realized an electronic circuit device that has an extremely excellent heat dissipation effect and allows a heat dissipation metal layer to be obtained easily and with a high yield.The configuration of the present invention is shown in Fig. 3. This will be explained using the example shown below.

第３図において外部リードを兼用するステンレス、ニッ
ケル、コバール等の金属よりなる金属枠。In Fig. 3, a metal frame made of metal such as stainless steel, nickel, or Kovar, which also serves as an external lead.

体（図示せず）によつて支えられた耐熱性絶縁樹脂フィ
ルム、本実施例においてはポリイミドフィルム１の第１
の主面に導体配線３が形成されている。同フィルムの第
２の主面にＦＥＰ等の接着層６に依り電子部品、本例に
おいてはＬＳＩチップ４が接着固定されている。このチ
ップ４はたとえば電力用の素子である。ここで導体配線
３はＣｒｌＣｕ．Ａｌ等の金属よりなる。又電子部品と
してはＬＳＩチップの他にチップ抵抗、チップコンデン
サ及びトランジスタチップ等もしばしば用いられるる。
更に前記？Ｉチップ４の表面電極５と前記導体配線３は
、ポリイミドフィルムの一部にフォトエッチ、プラズマ
エッチ等で形成した貫通孔を介して電気的接続がなされ
ている。なお、この貫通孔２は図のごとくテーパー状を
なし、電気的接続の断線を起りにくくし、信頼性を高め
ている。４″はたとえば他のＬＳＩチップあるいは他の
電子部品である。A heat-resistant insulating resin film supported by a body (not shown), in this example, the first polyimide film 1
A conductor wiring 3 is formed on the main surface of. An electronic component, in this example an LSI chip 4, is adhesively fixed to the second main surface of the film by an adhesive layer 6 such as FEP. This chip 4 is, for example, a power element. Here, the conductor wiring 3 is made of CrlCu. Made of metal such as Al. In addition to LSI chips, chip resistors, chip capacitors, transistor chips, and the like are often used as electronic components.
Further mentioned above? The surface electrode 5 of the I-chip 4 and the conductor wiring 3 are electrically connected through a through hole formed in a portion of the polyimide film by photoetching, plasma etching, or the like. Note that this through hole 2 has a tapered shape as shown in the figure to make electrical connection less likely to break and improve reliability. 4'' is, for example, another LSI chip or other electronic component.

更にポリイミドフィルム１の第２の主面ならびにＬＳＩ
チップ４，４″の側面に絶縁樹脂層１０例えばシリコー
ンゴム又はエポキシ樹脂等を形成する。Furthermore, the second main surface of the polyimide film 1 and the LSI
An insulating resin layer 10 such as silicone rubber or epoxy resin is formed on the side surfaces of the chips 4, 4''.

本実施例に於いては、絶縁樹脂層１０をＬＳＩチップ４
，４″の基体側面部、ＬＳＩチップ４″の基ノ体裏面及
びポリイミドフィルム１の第１の主面の金属導体配線３
に対応する第２主面上の接着層６表面に設けてある。次
に絶縁樹脂層６形成後、ＬＳＩチップ４及び４″のヒー
トシンクとして用いる蒸着金属層７：を、Ａ１、Ｃｕ等
の金属で蒸着形成する。In this embodiment, the insulating resin layer 10 is attached to the LSI chip 4.
, 4'', the back side of the LSI chip 4'', and the metal conductor wiring 3 on the first main surface of the polyimide film 1.
The adhesive layer 6 is provided on the surface of the second main surface corresponding to the surface of the adhesive layer 6. Next, after forming the insulating resin layer 6, a vapor-deposited metal layer 7 to be used as a heat sink for the LSI chips 4 and 4'' is formed by vapor-depositing a metal such as A1 or Cu.

本実施例に於いては７の厚みは２〜５μ瓦程度である。
尚、蒸着金属層７を形成する前にＬＳＩチップ基体の露
出部分にＣｒ等の導電性金属をメッキする事に依り、チ
ップ４の基体部と７の接続をより良好”に行なえる。こ
こでＬＳＩチップ４の基体端部８に注目すると、絶縁樹
脂１０を設けた事に依り、蒸着金属層７の段切れを回避
でき、１−ＳＩチップ４即ち発熱体と蒸着金属層７即ち
ヒートシンクを効果的に接続出来る。In this embodiment, the thickness of 7 is approximately 2 to 5 μm.
Note that by plating the exposed portion of the LSI chip substrate with a conductive metal such as Cr before forming the vapor-deposited metal layer 7, the connection between the substrate portion of the chip 4 and 7 can be made better. Paying attention to the base end portion 8 of the LSI chip 4, by providing the insulating resin 10, it is possible to avoid the breakage of the vapor-deposited metal layer 7, and to effectively connect the 1-SI chip 4, that is, the heating element, and the vapor-deposited metal layer 7, that is, the heat sink. Can be connected to

又、本実施例電子回路装置に於いては、ＬＳＩチップ４
と４″は、使用時の基体電位が異なるものとすると、相
互を絶縁する必要がある。Furthermore, in the electronic circuit device of this embodiment, the LSI chip 4
and 4'' have different substrate potentials during use, it is necessary to insulate them from each other.

そこで第３図のごとくチップ４″の基体部に絶縁樹脂１
０を設けた事に依り、４と４″の基体相互は絶縁されて
いる。又チップ４″の基体部と金属層の間には樹脂１０
が形成されているが、これは薄くできるため、４″の発
熱による熱も樹脂１０を介して充分外部に伝導される。
本実施例によれば、基体相互の絶縁の為のマスク蒸着又
は全面蒸着後のフォトエッチングの工程は不要となり、
容易に電子部品相互の絶縁が可能となる。次に、ポリイ
ミドフィルム１の金属導体配線３の設置位置にピンホー
ル９が存在した場合でも配線３と蒸着金属層７の間には
絶縁樹脂１０が設けてある為、３と７の短絡は回避でき
る。Therefore, as shown in Figure 3, insulating resin 1 is placed on the base of the chip 4''.
0, the bases of chips 4 and 4" are insulated from each other. Also, between the base of chip 4" and the metal layer, there is resin 10.
is formed, but since it can be made thin, the heat generated by the 4'' is sufficiently conducted to the outside via the resin 10.
According to this embodiment, the process of mask vapor deposition or photo-etching after the entire surface vapor deposition for insulating the substrates from each other is unnecessary.
It becomes possible to easily insulate electronic components from each other. Next, even if a pinhole 9 exists at the installation position of the metal conductor wiring 3 in the polyimide film 1, the insulating resin 10 is provided between the wiring 3 and the vapor-deposited metal layer 7, so short circuits between 3 and 7 are avoided. can.

このピンホール９は、ポリイミドフィルム１自体に存在
する場合と、貫通孔２形成時のフォトエッチ又はプラズ
マエッチに依つて発生する場合があり、高率でピンホー
ル９は存在するものであるが、本実施例に依れば、極め
て容易にピンホール９に依る短絡を回避でき、高歩留で
放熱効果の大きい薄形電子回路を得る事ができる。以上
のように本発明によれば、ヒートシンクとなる金属層は
装着される電子部品の大きさに制限されず大きな放熱効
果を得ることができるとともに、電子部品基体端部に於
ける放熱用金属層の段切れを防止できる。These pinholes 9 may exist in the polyimide film 1 itself, or may be generated due to photo-etching or plasma etching during the formation of the through-holes 2. Although pinholes 9 are present at a high rate, According to this embodiment, short circuits due to pinholes 9 can be avoided very easily, and a thin electronic circuit with high heat dissipation effect can be obtained with high yield. As described above, according to the present invention, the metal layer serving as a heat sink can obtain a large heat dissipation effect without being limited by the size of the electronic component to which it is attached, and the metal layer for heat dissipation at the end of the electronic component base It is possible to prevent the breakage of the steps.

さらに本発明によれば、複数の電子部品基体部相互の絶
縁が極めて容易にかつ確実に行なえるとともに、絶縁樹
脂フィルムにピンホールが存在しても電気的故障になり
得ない。このように本発明は高密度薄形電子部品実装体
の応用範囲の拡大、製造歩留の向上に大きく寄与するも
のである。Further, according to the present invention, it is possible to insulate a plurality of electronic component base portions from each other very easily and reliably, and even if a pinhole exists in an insulating resin film, it will not cause an electrical failure. As described above, the present invention greatly contributes to expanding the range of applications of high-density thin electronic component mounting bodies and improving manufacturing yields.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のフィルム実装の電子回路装置の構造断面
図、第２図Ａ，ｂはそれぞれ従来のフィルム実装電子回
路装置の要部構造断面図、第３図は本発明の一実施例に
かかるフィルム実装電子回路装置の構造断面図である。FIG. 1 is a structural sectional view of a conventional film-mounted electronic circuit device, FIG. FIG. 2 is a structural cross-sectional view of such a film-mounted electronic circuit device.

Claims (1)

【特許請求の範囲】 １ 一方の主面に配線用金属層が選択的に形成された耐
熱性絶縁基板の他方の主面に、接着層を介して電子部品
の電極を有する一方の主面が固着され、前記電子部品の
電極と前記配線用金属層とが前記絶縁基板に形成された
貫通孔を介して電気的に接続され、前記電子部品の側面
に絶縁層が形成されるとともに、前記耐熱性絶縁基板の
他方の主面に前記接着層を介して絶縁層が形成され、こ
の絶縁層および前記電子部品の他方の主面に連続した金
属層を設けたことを特徴とする電子回路装置。 ２ 電子部品が半導体集積回路基体よりなることを特徴
とする特許請求の範囲第１項に記載の電子回路装置。 ３ 貫通孔がテーパ状をなすことを特徴とする特許請求
の範囲第１項に記載の電子回路装置。 ４ 電子部品の他方の主面と金属間に絶縁層が介在され
てなることを特徴とする特許請求の範囲第１項に記載の
電子回路装置。[Claims] 1. A heat-resistant insulating substrate on which a metal layer for wiring is selectively formed on one main surface, and one main surface having an electrode for an electronic component on the other main surface with an adhesive layer interposed therebetween. The electrodes of the electronic component and the wiring metal layer are electrically connected through the through holes formed in the insulating substrate, an insulating layer is formed on the side surface of the electronic component, and the heat-resistant 1. An electronic circuit device, characterized in that an insulating layer is formed on the other main surface of the insulating substrate with the adhesive layer interposed therebetween, and a continuous metal layer is provided on the insulating layer and the other main surface of the electronic component. 2. The electronic circuit device according to claim 1, wherein the electronic component is made of a semiconductor integrated circuit substrate. 3. The electronic circuit device according to claim 1, wherein the through hole has a tapered shape. 4. The electronic circuit device according to claim 1, wherein an insulating layer is interposed between the other main surface of the electronic component and the metal.
JP53079896A 1978-06-30 1978-06-30 electronic circuit equipment Expired JPS6041853B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53079896A JPS6041853B2 (en) 1978-06-30 1978-06-30 electronic circuit equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53079896A JPS6041853B2 (en) 1978-06-30 1978-06-30 electronic circuit equipment

Publications (2)

Publication Number Publication Date
JPS558025A JPS558025A (en) 1980-01-21
JPS6041853B2 true JPS6041853B2 (en) 1985-09-19

Family

ID=13703031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53079896A Expired JPS6041853B2 (en) 1978-06-30 1978-06-30 electronic circuit equipment

Country Status (1)

Country Link
JP (1) JPS6041853B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01294473A (en) * 1988-05-24 1989-11-28 Material Eng Tech Lab Inc Freshness keeping container
JPH043979U (en) * 1990-04-27 1992-01-14

Also Published As

Publication number Publication date
JPS558025A (en) 1980-01-21

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