JPH03217891A - Data-side driving circuit of color matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To simplify circuit design by placing sample-hold circuit which corresponds to M primary color signals in sample holding operation with outputs of respective stages of a shift register. CONSTITUTION:The shift register 101 transfers shift data SD in order with a shift clock SCL and sampled signals SO, S1... are outputted from the Q outputs of the respective stages. Then a sample-hold circuit 105 samples and holds video data R0, G0, and B0 at the same time at, for example, timing S0. Consequently, the operation frequency of the shift register can be lowered to simplify the circuit design and reduce the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Applications] The present invention relates to a data side drive circuit of a color mask IJ type liquid crystal display device.

[Conventional technology] Color matrix type liquid crystal display devices (hereinafter referred to as color liquid crystal panels) are used in ORT (
It is being used as a display device to replace the Oat'nOde Ray Tube. As color liquid crystal panels become larger, applications other than televisions, such as character displays for computers, are also being considered. In a computer, for example, analog R (}B signal C three primary color signals of red, green, and blue),
Connect to such a computer that is equipped with a connector that outputs synchronization signals, dot clock signals (chronograph signals that define the data transfer period of one pixel), etc.
A block diagram of the color liquid crystal panel that performs display is shown in Fig. 2. 201 is a computer, and analog RGB signals, synchronization signals SYN
O, don't clock signal DOL, etc. are output. 2
02 is a controller that generates timing control signals from SYNC and DOL to each panel drive circuit, which will be described later. Reference numeral 203 is a data side drive circuit, which takes in RGB signals from the computer and controls the brightness of each pixel of the color liquid crystal panel 205 using two timing control signals SD and SOL output from the controller 202. Generate a signal. Reference numeral 204 denotes a scanning side driving circuit, which generates a scanning side drive signal to the color liquid crystal panel 205 in response to a timing control signal from the controller 202. 205 is a color liquid crystal panel, and each pixel PO, P1... is PO, RO, GO.
, BO, P1 are R1, G1, B1, and so on.
．． It consists of three primary color pixels of B.

FIG. 3 is a conventional circuit example of the data side drive circuit 203 in FIG. 2. 301 is a shift register, each stage of which is composed of a flip-flop, and the output Q of each stage is connected to the input D of the next stage. However, the shift data signal SD from the controller 202 is connected to the D input of the first stage. The shift register 301 also transfers shift data in synchronization with the shift clock signal SCL. S
RO, SGO, . . . are Q outputs of each stage. '302 is an analog switch, which is gate-controlled by the Q output of each stage of the shift register 301. The input side of the analog switch 302 is connected to any one of R, G, and B primary color signal lines.

The output side of the analog switch 302 should hold the signal level sampled by the analog switch 302.
, a holding circuit 303 consisting of a capacitor is connected. Further, a data line driving circuit 304 is connected to the holding circuit 303, and based on the amount of charge held by the holding circuit 303,
RO, Go, . . . generates data line drive signals for driving each line.

The data sampling operation in the data rotation driving circuit shown in FIG. 3 will be explained with reference to the time chart shown in FIG. The shift clock SQL has a frequency five times that of the dot clock DOL, and the phase relationship is also fixed. This means that P L L (P
This can be achieved if you have a Rase Locked Lolp (Rase Locked Lolp) circuit.

The shift clock SCL sequentially transfers the sheet data SD, and from the Q output of each stage of the shift register 301, SRO and SGO are synchronized with the rise and rise of SQL.
,... occurs. The holding circuit 303 has an SR
O. R, G, B at the falling edge of SGO,...
The level of is sampled and held.

[The problem that the invention seeks to solve] However, the above-mentioned conventional technology had the following problems.

First, as the shift clock SQL for the shift register in the data side drive circuit 203, a signal with a frequency three times that of the dot clock DC- is required. For example, the dot clock signal of some types of computers is 21 MHz, so in this case the shift clock signal SQL is 65 MHz, which requires a high-speed operation circuit, making circuit design difficult and leading to increased power consumption. Also controller 2
A PLL circuit is required within the 02, which causes an increase in cost.

The present invention has been made to solve the problems of the conventional technology, and an object of the present invention is to provide a color matrix type circuit that can suppress the operating frequency, facilitates circuit design, and has low power consumption. An object of the present invention is to provide a liquid crystal display device.

[Means for solving the problem] In order to achieve the above-mentioned object, the present invention provides (1)4)
In a data-side drive circuit of a color matrix liquid crystal display device, in which display data of one pixel is input as data of M primary color signals (M is a positive integer) synchronized with a prescribed clock signal, b) the above. '/M of clock signal
(N is a positive integer) a shift register that performs a shift operation using a shift clock signal of a frequency; and C) a sample hold that includes a plurality of sets of M analog switches to which each of the M primary color signals is input and a plurality of holding circuits. d) a data line driving circuit connected to the sample and hold circuit, and e) the set of M analog switches simultaneously perform sample and hold operations by the output of each stage of the shift register. A data side drive circuit for a color matrix type liquid crystal display device.

present.

[Example 1] Hereinafter, one configuration example of the present invention will be explained based on the drawings.

FIG. 1 is a configuration diagram of a data side drive circuit of a color matrix type liquid crystal display device according to the present invention. 10) is a shift register, and the D input of the first stage receives shift data SD.
is input, and the Q output of each subsequent stage is connected to the D input of the next stage. Zoft register 101 is shift clock S
A shift operation is performed by QL, and the Q output of each stage is the sampling signal S O , . S 1 .... 102 is an analog switch, and the input section has R,
G and B primary color signals are connected, and the output has a holding circuit 1.
03 is connected. A data line driving circuit 104 is further connected to the holding circuit 103 and drives each data line. The sample/hold circuit consists of an analog switch 102 and a holding circuit 103.
As shown, each pixel PO, P in the color liquid crystal panel 205
Common sampling pulses SO, S1, . . . are input for a set of three pulses corresponding to i, .

The sample and hold operation will be explained with reference to FIG. 5. In this case, the dot clock DOL and shift clock SQL are common. In the shift register 101, the shift clock SQL
The shift data SD is sequentially transferred at the Q output of each stage, and sampling signals SO, S1, . . . are output from the Q output of each stage. For example, at the SO timing, 1
05 sample and hold circuit, RO, (}0, E
The video data of O is sampled and held at the same time.

[Effects of the Invention] As described above, according to the present invention, in a color display panel in which display data of one pixel is manually inputted as M primary color signal data in synchronization with a clock signal, samples corresponding to M primary color signals can be generated. - The operating frequency of the shift register can be lowered by causing the hold circuit to sample and hold the output K of each stage of the shift register. This leads to simplified circuit design and reduced power consumption. Further, a PLL circuit is not required in the controller.

In this embodiment, M=3, that is, one pixel is expressed by RGB three primary color signals, but other examples, for example, M=
It is also applicable to the case where one pixel is expressed by the four primary color signals of 4, that is, RGB and Y (if luminance is white). D
Similar processing is also possible for a video signal that has been digital-to-analog converted using a reference clock signal in an A converter.

Furthermore, if the data side drive circuits are arranged above and below the color liquid crystal panel 205 and each pixel is alternately driven by the upper and lower data side drive circuits, the frequency of the shift clock signal can be further reduced to 1/2. can. (N=2)

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data side drive circuit of a color matrix IJ type liquid crystal display device according to the present invention. FIG. 2 is a block diagram of a color matrix IJ type liquid crystal display device. FIG. 3 is a configuration diagram of a data side drive circuit of a conventional color matrix type liquid crystal display device. Figure 4 is a time chart diagram of each part in Figure 3. FIG. 5 is a time chart diagram of each part of FIG. 1. 101...Shift register 102...Analog switch 103...Holding circuit 104...Data line drive circuit 105...Sample/hold circuit and beyond

Claims (1)

[Claims] (1)a) A color matrix liquid crystal display device in which display data for one pixel is input as M (M is a positive integer) primary color signal data synchronized with a current clock signal. In the data side drive circuit, b) a shift register that performs a shift operation using a shift clock signal having a frequency of 1/N (N is a positive integer) of the clock signal; and c) M registers to which each of the M primary color signals is input. 4. A sample and hold circuit including one set of analog switches and a plurality of sets of holding circuits; ) a data line driving circuit connected to the sample and hold circuit, and e) the output of each stage of the shift register causes the M
A data side drive circuit for a color matrix liquid crystal display device, characterized in that a set of individual analog switches simultaneously perform sample and hold operations.