JPH03203775A - Driving circuit for display device - Google Patents

Abstract

PURPOSE:To drive the display device of a large capacity by using a conventional source driver and also to restrain the increase of cost by fetching a parallel signal outputted by a converting means at the prescribed number of times and driving a signal electrode based on the fetched signal. CONSTITUTION:Video signals by the amount of 8 bits are fetched over plural cycles by a serial-parallel conversion circuit 3a and the upper side source driver 2a, and the video signals which correspond to all of the source electrodes for odd numbered picture elements are fetched in a shift register in the upper side source driver 2a so as to be outputted from the shift register in parallel. The video signal outputted from the shift register is converted to a driving signal having a voltage level optimum for driving the source electrode by the upper side source driver 2a, and the driving signal is outputted to the source electrode. And the same processing is performed for the even numbered video signals by a serial-parallel conversion circuit 3b and a lower side source driver 2b. Thus, the display device of the large capacity can be driven by using the source driver made with a conventional medium break-down strength process and the cost can be restrained so that it may not be increased more than a conventional driving circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drive circuit for a display device, and more particularly to a drive circuit for a display device that is compatible with increased capacity and higher definition of display devices.

(Prior Art) FIG. 7 shows a block diagram of a conventional matrix type liquid crystal display device. In the liquid crystal display panel l, a plurality of source electrodes (not shown) are arranged in parallel to each other, and a plurality of gate electrodes (not shown) are arranged to intersect with the source electrodes. An upper source driver 7a and a lower source driver 7b are connected to the source electrodes. Furthermore, a gate driver 8 is connected to the gate electrode. Depending on the display device, gate drivers may be provided on the left and right sides of the liquid crystal display panel 1. RGB digital video signals are serially input to the upper source driver 7a and the lower source driver 7b. Each of the RlG and B video signals takes a value of rOJ or rlJ, and therefore, this display device can display eight colors. The upper source driver 7a has a clock DOT synchronized with the video signal.
A clock 5CLK obtained by dividing LK into 1/2 is supplied.

On the other hand, the lower source driver 7b has a clock 5 which is the clock 5CLK inverted by the inverter 9.
CLK is supplied.

The upper source driver 7a and the lower source driver buffer b shift and take in input video signals in synchronization with clocks 5CLK and 5CLK, respectively.

In order to perform color display using RGB video signals, striped color filters are repeatedly arranged in the order of R filter, G filter, and B filter on the liquid crystal display panel 1, as shown in FIG. Such a color filter arrangement method is called a "vertical stripe arrangement."

When driving the source electrode of the liquid crystal display panel 1 with one source driver placed on one side of the liquid crystal display panel l, the clock DOTCLK synchronized with the input video signal is
It is necessary to use it as it is as a shift clock for capturing the video signal into the source driver. However, in high-resolution display devices, video signals are transmitted at high speeds (for example, 25
．． 175 MHz), it is not possible to sample the video signal using a conventional medium-voltage source driver with a slow shift speed. Therefore, as shown in FIG. 7, two source drivers, an upper source driver 7a and a lower source driver 7b, are provided, and the upper source driver 7
It is considered that odd-numbered video signals are sampled by a, and even-numbered video signals are sampled by the lower source driver 7b. FIG. 9 shows the connection state between the source drivers 7a and 7b and the liquid crystal display panel 1 in the display device of FIG. 7. Moreover, the sampling timing of the video signal in the display device of FIG. 7 is shown in FIG. The upper source driver 7a takes in odd-numbered video signals at the rising edge of the clock 5CLK, and the lower source driver 7b takes in the clock 5 with the opposite phase to the clock 5CLK.
Even-numbered video signals are taken in at the rising edge of CLK.

(Problem to be solved by the invention) In order to drive a display unit such as a liquid crystal display panel, T
Since a voltage higher than the TL level is required, a so-called medium voltage source driver, which is manufactured using a medium voltage process to withstand such a voltage, is used as the source driver. In order to cope with the demand for high-speed sampling of video signals accompanying the increase in capacity of display devices in recent years, a countermeasure has been considered in which a liquid crystal display panel is driven by two source drivers, upper and lower, as described above. However, even with this method, for example (
A sampling rate of 25,175/2) MHz is required. The upper limit of the operating speed of conventional medium voltage drivers is 6 at most.
Since the frequency is about MHz, the above requirements cannot be met. Therefore, it becomes necessary to provide a line buffer or a frame buffer for temporarily storing video signals for one scanning line or one frame, which increases the cost of the drive circuit.

The present invention was made in view of the current situation, and
The purpose is to provide a display device drive circuit that can drive a large-capacity display device using a source driver manufactured using a conventional medium-voltage process, without causing a significant increase in cost. It is in.

(Means for Solving the Problems) A drive circuit for a display device of the present invention includes a drive circuit for driving a display unit in which a plurality of signal electrodes are arranged in parallel with each other.
A drive circuit for a display device, comprising means for converting a serially input digital video signal into a string of parallel signals having a width of multiple bits, and a means for capturing the parallel signal outputted by the converting means a predetermined number of times and converting it into the captured signal. means for driving the signal electrode based on the signal electrode, thereby achieving the above object.

(Example) The invention will now be described with reference to examples.

FIG. 1 shows a block diagram of a matrix type liquid crystal display device using an embodiment of the present invention. This embodiment is a drive circuit that displays eight colors based on TTL level digital RGB video signals. The liquid crystal display panel 1 is provided with color filters in a vertical stripe arrangement, as described in the "Prior Art" section.

As shown in FIG. 1, an upper source driver 2a and a lower source driver 2b are connected to the liquid crystal display panel l. The upper source driver 2a and the lower source driver 2b include serial/parallel conversion circuits 3a and 3b.
are connected to each other. In FIG. 1, illustrations of gate drivers, control circuits, etc. are omitted.

RGB video signals are serially input to serial/parallel conversion circuits 3a and 3b. Upper source driver 2
The serial/parallel conversion circuit 3a connected to the video signal a takes in odd-numbered video signals in accordance with a clock 5CLK obtained by dividing the clock DOTCLK synchronized with the video signal into 1/2. On the other hand, the serial/parallel conversion circuit 3b connected to the lower source driver 2b uses the clock 5
Clock 5C obtained by inverting CLK by inverter 4
According to LK, even-numbered video signals are taken in. The serial/parallel conversion circuits 3a and 3b also include S, which will be described later.
1, s2, and s33 are input. Further, a signal UCLK and a signal LCLK, which will be described later, are input to the serial/parallel conversion circuits 3a and 3b, respectively.

The serial/parallel conversion circuits 3a and 3b convert serially input video signals into a string of parallel signals having an 8-bit width. Therefore, the upper source driver 2a and the lower source driver 2b each receive and take 8-pit video signals from the serial/parallel conversion circuits 3a and 3b, respectively. The source drivers 2a and 2b are supplied with a shift clock XCK that provides timing for latching the video signal from the serial/parallel conversion circuit 3a or 3b.

The serial/parallel conversion circuit 3a will be explained. The serial/parallel conversion circuit 3a includes a converter 30a (see FIG. 2) for converting each of serially input R, G, and B signals into 8-bit parallel signals, and a converter 30a (see FIG. 2) that converts the output video signal of the converter 30a. Output unit 3 that rearranges the bits and sends them to the upper source driver 2a in three parts of 8 bits each.
1a (see Figure 3). The serial/parallel conversion circuit 3b has the same configuration as the serial/parallel conversion circuit 3a, except that the clock 5CLK and LCLK signals are used instead of the clock 5CLK and UCLK signals, respectively. FIG. 5 shows the timing related to the operation of the serial/parallel conversion circuit 3a.

The converter 30a shown in FIG. 2 includes shift registers 32 to 34 corresponding to the R signal, G signal, and B signal, respectively. D flip-flops 35-37 are connected to the shift registers 32-34, respectively. The shift register 32 shifts the odd-numbered signals among the serially inputted R signals according to the clock 5CLK, and outputs the R signals converted into 8-pit parallel signals to the output terminal Qo.
~ Output to Qs. After the 8-pit video signal is stored in the shift register 32, the UCLK signal is input to the D flip 70 tube 35 as shown in FIG. 5, and at the rising edge of the UCLK signal, the output video signal from the shift register 32 is The signal is transferred to the D flip-flop 35 and output from the D flip-flop 35 as a video signal URO-UR7.

Shift register 33 and D flip-flop 36 corresponding to the G signal, and shift register 34 corresponding to the 8th number
and D flip-flop 37 operate similarly. The D flip-flop 36 corresponding to the G signal outputs 8-bit video signals UGO-UG7, and the D flip-flop 37 corresponding to the B signal outputs 8-bit video signals UBO-UB7.

The output section 31a of the serial/parallel conversion circuit 3a is
As shown in the figure. The output section 31a includes eight selection circuits 39. The output signals of the converting section 30a in FIG. 2 are rearranged as shown in FIG. 3 and input to the output section 31a.

Each selection circuit 39 has three ANDs, as shown in FIG.
41 to 43 and an OR gate 44.

The output section 31a has a 5l-S signal having a waveform shown in FIG.
3 signals are input. The video signals are output from the D flip-flops 35 to 37 of the conversion section 30a, and while the shift registers 32 to 34 of the conversion section are taking in the next 8-bit video signal, the Sl to S3 signals sequentially become H level. ,
The video signal from the conversion section 30a is divided into three times and sent to the output section 3.
1a to the upper source driver 2a. While the Sl signal is at H level, the following video signals are output from the output section 31a.

UROlUGOlUBO, URI, UGI, UBl, U
While the R2, UC2°S2 signals are at H level, the following video signals are output from the output section 31a.

UB2, UR3, UC2, UB3, UR4, UC2, U
B4, UR5° Further, while the S3 signal is at H level, the following video signals are output from the output section 31a.

UC2, UB5, UR6, UC2, UB6, URI, U
C2, UB7° FIG. 6 shows the main parts of the upper source driver 2a.

The upper source driver 2a includes eight shift registers 20-27 corresponding to the video signals UDO-UD7 outputted from the output section 31a in FIG. 3, respectively. Each of the shift registers 20 to 27 has a shift clock XC.
At the falling edge of K, the video signal from the output section 31a is taken in and shifted.

The serial/parallel conversion circuit 3a and the source driver 2a described above take in video signals for 8 pins over multiple cycles, and the source driver 2a
The video signals corresponding to the source electrodes for all odd-numbered pixels are taken into the shift registers 20 to 27 in a,
They are output in parallel from shift registers 20-27. The source driver 2a converts the video signals output from the shift registers 20 to 27 into a drive signal of a voltage level suitable for driving the source electrode, and outputs the drive signal to the source electrode. The serial/parallel conversion circuit 3b and the source driver 2b perform similar processing on even-numbered video signals.

In this embodiment, serial/parallel conversion circuits 3a and 3
b, the frequency of the shift clock XCK input to the source drivers 2a and 2b is equal to the clock DO
When the frequency of TCLK is 25.175MHz, 11
5/5,035 MHz. Therefore, even when the source drivers 2a and 2b are manufactured using the conventional medium breakdown voltage process, a sufficient operating speed can be obtained.

(Effects of the Invention) According to the present invention, a high-speed video signal can be processed using a source driver manufactured using a conventional medium-voltage process, and a large-capacity display device can be manufactured without the need for line buffers or frame buffers. A driving circuit for a display device is provided. The required serial/parallel conversion means can be constructed using at most several-bit shift registers, flip-flops, etc., and there is almost no increase in cost compared to conventional drive circuits.

4. No, no! H Fig. 1 is a block diagram showing the main parts of a matrix type liquid crystal display device using an embodiment of the present invention, and Fig. 2 is a block diagram showing the conversion section in the serial/parallel conversion circuit in the embodiment. , FIGS. 3 and 4 are block diagrams showing the output section of the serial/parallel conversion circuit in this embodiment,
Fig. 5 is a timing diagram for explaining the operation of the embodiment, Fig. 6 is a block diagram showing the main parts of the source driver in the embodiment, and Fig. 7 is an example of a conventional drive circuit. A block diagram of a matrix type liquid crystal display device, FIG. 8 is a diagram schematically showing the vertical stripe arrangement of color filters in the liquid crystal display panel, and FIG. 9 is a diagram showing the liquid crystal display panel in the display device of FIG. FIG. 10 is a timing diagram showing the sampling timing of the video signal in the display device of FIG. 7, which shows the connection state with the source driver.

l...Liquid crystal display panel, 2a...upper source driver, 2b...lower source driver, 3a, 3b...
Serial/parallel conversion circuit, 20-27...shift register, 30a...conversion section, 32-34...shift register, 35-37...D flip-flop, 3
1a... Output section, 39... Selection circuit.

that's all

Claims (1)

[Scope of Claims] 1. A drive circuit for a display device for driving a display unit in which a plurality of signal electrodes are disposed in parallel with each other, the drive circuit converting serially input digital video signals into multi-bit widths. A drive circuit for a display device, comprising means for converting into a string of parallel signals, and means for capturing the parallel signals outputted by the converting means a predetermined number of times and driving the signal electrodes based on the captured signals.