JPH02143781A - Matrix display panel driving device - Google Patents

Abstract

PURPOSE:To display a video image of the NTSC system on a matrix display panel with an aspect ratio different from the aspect ratio of the video signal of the NTSC system by giving a signal based on the video signal to an X driver circuit when the NTSC system video signal is introduced and giving a prescribed DC voltage to a Y driver circuit. CONSTITUTION:When the video signal of the NTSC system is introduced, a signal based on the video signal of the NTSC system is given to a 1st X driver means (X driver circuit) 32 and a prescribed DC voltage is given to a 2nd X driver means (Y driver circuit) 33. Thus, the NTSC system video image is displayed in the middle of a matrix display panel driven by the X driver circuit 32 and a prescribed raster video image is displayed around the matrix display panel driven by the Y driver circuit 33. Thus, the video signal of the NTSC system is displayed by using the display panel with the aspect ratio the high definition television system with simple circuit constitution.

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to a matrix display panel driving device, and in particular,
The present invention relates to a matrix display panel driving device suitable for displaying high-definition television broadcasts. (Prior Art) Recently, high-definition television receivers for high-definition television broadcasting have been developed, and liquid crystal panels are sometimes used as display devices. A liquid crystal panel for displaying high-definition television broadcasts has a horizontal resolution of 640 to 1
200 pixels on the right and 900 to 1000 pixels on the right in the vertical direction are adopted. FIG. 2 is a block diagram showing a conventional 71-lix display panel driving device employing such a 960×960 pixel liquid crystal panel. The composite video signal introduced into the input terminal 1 is sent to the video processing circuit 2.
is input. The video processing circuit 2 includes a video signal processing circuit (not shown), a signal processing circuit and a synchronization separation circuit (14). In addition to outputting the composite same brightness signal S'/NC to the roller circuit 3, it also outputs the 3-axis color signals (R (red), G
(green), B (blue) signal) is output to the polarity switching circuit 4. The controller circuit 3 separates horizontal and vertical dome signals from the composite dome signal 5Y14C, outputs a selection signal PSW that controls the polarity switching circuit 4, and outputs a clock CL and start pulse STH that controls the X driver circuit 5. and outputs Y driver circuit 6L (controlling clock YCL
Output K. Note that the luminance signal, color difference signal, and synchronization signal may be introduced separately to the input terminal 1.
In this case, the video processing circuit 2 is constituted by a matrix circuit and outputs R, G, and B signals to the polarity switching circuit 4. In order to prevent deterioration of the liquid crystal, the polarity switching circuit 4 inverts and outputs the R, G, and B signals at a predetermined period. The X driver circuit 5 receives R and G signals from the polarity switching circuit 4. The B signal and the inverted R, G, and B signals R, G, and B signals are input, and the color is applied to the data line group of the liquid crystal panel 7 under the control of the clock C1- from the controller circuit 3 and the start pulse STH. Output a signal. In addition, the Y driver circuit 6 receives the clock YCLK@23 from the controller circuit 3, and uses the clock YCLK@23 of the liquid crystal panel 7.
A scanning signal is supplied to the line group G. The liquid crystal panel 7 has 7 pixels.
Each pixel is arranged in a matrix, and each pixel is driven based on signals supplied to the data line group and the gate line group G to perform display. FIG. 3 is a diagram specifically showing the polarity switching circuit 4. R, G, which are input to input terminals 3, 9, and 10, respectively.
The B signal is largely supplied to one input terminal of the switch 81.32 and S3, and is also supplied to the polarity inversion circuit 11. The polarity inversion circuit 11 has R and G. The polarity of the B signal is inverted, and the R, G, and B signals are output to the other input terminal of the switch Sl, 32.83. The switches S1 to $3 are controlled and switched by the selection signal PSW, and output the R, G, B signals or the R2O, B signals to the X driver circuit 5 via the buffer amplifiers B1 to B3. In this way, the X driver circuit 5 receives the control signal PS.
R, G, and B signals whose polarities change at a cycle of - are supplied (hereinafter referred to as AC drive). FIG. 4 is a block diagram specifically showing the configuration of the X driver circuit 5. As shown in FIG. The number of pixels in the horizontal direction of the liquid crystal panel 7 is 960.
As the X driver circuit 5, four sets for driving 240 pixels are used. Shift register 12 consists of 240 bits. The shift register 12 is supplied with a start pulse STH indicating the start of a horizontal display period from the controller circuit 3, and then when a clock CL is introduced, the first bit turns on and outputs an on pulse. Thereafter, every time the clock CL is sequentially introduced, each bit is sequentially turned on and an on-pulse is output. When the on pulse is 240 pips 1-shift+-, shift 1-register 12
1-V two-out 5TII OUT is output to the next stage shift register (not shown). The shift register at the next stage introduces this 2l: pleaan f1-STH011T as a star l-pulse 5TII, and each bit turns on sequentially with the clock pulses introduced sequentially. The controller circuit 3 outputs 96 signals per horizontal effective scanning period.
0 clocks CL are output, and 960 on-pulses are sequentially output from each bit of the shift register during one horizontal effective scanning period. The level converter 13 is composed of 240 stages, amplifies the on-pulse of the shift register 120, and outputs it to the υ Zamblebold circuit 14.
Ru. The variable hole 1 circuit 14, which is composed of 240 stages, performs lean-blending and holds the introduced R, G, and B signals at the timing of the on-pulse from the level converter 13. As a result, 960 R, G, and B signals are sampled and held in the ripple hold circuit 14 during one horizontal effective scanning period. At this point, the sample hold circuit 14 connects to the liquid crystal panel 7.
It functions as a line memory by holding R, G, and B (ffiQ) corresponding to one line of pixels. The color switching circuit 15 uses the horizontal periodic switching timing signal C314 to select R, G, or G based on the color arrangement of the pixels of the liquid crystal panel 7.
Switching B signal g. The output from the sample and hold circuit 14 is supplied to a buffer driver 16, and the buffer driver 16 receives an output instruction signal fi from the controller circuit 3.
At the timing of OE, the output of the sample and hold circuit 14 is amplified and output to the data line group of the liquid crystal panel 7. FIG. 5 is a circuit diagram specifically showing the configuration of the sample hold circuit 14 and the buffer driver 16. Each analog switch 1 of analog switch Jj7.17
7a, 17b, . . . are analog switches 17a, 17b, .
17b, . . . are turned on in sequence. Analog switch 17a. 17b, . . . turn on, R from the color switching circuit 15. The G and B signals are supplied in large quantities to each of the hold capacitors 18a, 18b, . The signal is supplied to one input end of the amplifiers 19a, 19b, . 3 state batshu? Amplifier 19a, 1
9b. ... is given an output instruction signal j30E (pulse width of about 10 μsec) from the controller circuit 3 and turned on at the same time. Hold capacitors 18a, 18b
. ... holds the R, G, [3 signals until the output instruction signal f)0[ is outputted and the R, G, [3 signals are output from the 3rd day buffer amplifier 19. The output terminals of the 3-state buffer amplifiers 19a, 19b, . . . are connected to the other input terminal, and are also connected to each data line DI, D2, . . . of the data line YD of the liquid crystal panel 7. These data lines DI, D2, . . . are supplied with color signals in the order of R signal, G signal, B signal, . . . or B signal, No. 048, R signal, . . . by the color switching circuit 15. are supplied respectively. Note that the analog switch 17a,
17b. The time required for . Also, bold condensation Fj18a, 18b. ... has a capacitance of several pF. FIG. 6 is a circuit diagram specifically showing the configuration of the color switching circuit 17. The input terminals 20, 21, and 22 have polarity switching circuits 4 to R2.
O, B signals are input. Input terminals 20, 21 and 22 are connected to one input terminal of switches 84, 85 and 86, respectively, and are also connected to the other input terminals of switches $5.36 and G4. Switches 84°G5 and G6 are supplied with a switching timing signal C3W and are switched in a horizontal cycle. Therefore, from switch 84°3s, Se is 1
The R, G, and B signals or the B, R, and G signals are switched and output in large numbers every horizontal period. As a result, as described above, the data lines 01 and D2 of the liquid crystal panel 7
, . . ., the color signals are in the order of R, G, B or B, R for each horizontal period. The signals are switched and supplied in the order of G. Figure 7

[FIG. 2] A schematic circuit diagram specifically showing a liquid crystal panel 7. [FIG. The liquid crystal panel 7 is 960x96 arranged in a matrix.
It is composed of 0 pixels and has an aspect ratio of 16:9. Each pixel is provided with a thin film transistor (TPT) 23, and the gate of each TFT 23 is connected to gate lines Gl and G2.
,..., respectively, and the drain is connected to the data line DI.
, D2, . . . and their sources are connected to the transparent electrodes 24, respectively. Transparent electrode 24 and common electrode 2
5, a liquid crystal layer 26 of twisted nematic or the like is formed. The TPT 23 is turned on by a scanning signal applied from the Y driver circuit 6 to the gate line group G, and applies R, G, and B signals from the data line group to the transparent electrode 24. As a result, each liquid crystal layer 26 can be fully driven. Each pixel has R and G. A color filter B is formed to enable color display. The Y driver circuit 6 connects the gate line G1 of the liquid crystal panel 7,
A scanning signal is sequentially supplied to G2, . For example, if a scanning signal is supplied to the gate line G1 during one horizontal effective scanning period,
The TFT 23 on the first line of the liquid crystal panel 7 turns on,
Buffer driver 1G at the timing of output instruction signal O[
From R, G, B. . . . signals are sent to each data line D1. D2, . . . are applied to drive the liquid crystal layer 26. During the next one horizontal effective scanning period, a scanning signal is supplied to the gate line G2 and the second
1FT23 of the line is turned on. In this case, the color switching circuit 15 selects data lines r)1. D2゜... is supplied with B, R, G,... signals. [Item type 2G is driven. In this way, the liquid crystal panel 7 having the color arrangement shown in FIG. 7 is driven. As shown in Figure 7, the color array is shifted by 1°5 pixels per line (hereinafter referred to as
The delta array) is often used because of its high resolution. By the way, NTSC television broadcasting is currently being carried out, and it is desirable to be able to display both high-definition television broadcasting and NTSC television broadcasting. The aspect ratio of high-definition television broadcasting is 16:9, and the aspect ratio of NTSC is 4:3.
(12 to 9). Therefore, high quality Te1nobiji'26
The aspect ratio of the video signal of the formula is 16 to 12 compared to the aspect ratio of the video signal of the NTSC system, which is 1 point in the 2Jj direction. Therefore, the horizontal time axis of the video signal is shortened to approximately 12/16 by using line editing, etc., and 2/16 of the front and back of the blanking period are made into one black novel, and the vertical y) For the direction, 2 signals in the same horizontal scanning period
By scanning the lines, it is possible to display NTSC system 7-revisit and 1-channel broadcasts. However, when the circuit for compressing the time axis is constructed from a digital circuit such as a line meter, there is a problem that the circuit becomes extremely complicated and large in size. (Problem to be Solved by the Invention 1)) As described above, in the conventional 71-RIS display panel drive device described above, high-definition television broadcasting and NTSC
In order to achieve U-compatibility with pre-registered broadcasting, the circuit would become extremely complex and large. The present invention has been made in view of the above problems, and has a simple circuit configuration that allows the aspect ratio to be increased to 16, for example.
1] To provide a 71-ix display panel driving device capable of displaying an NTSC video signal using a 9-pixel display panel. "Structure of the Invention" (Means for Solving Problem A) The present invention consists of a 7-vehicle 1-ratio which is longer in the horizontal direction than the aspect ratio of an NTSC video signal and arranged in a matrix. Each pixel is supplied to a data line (51
) and a scanning line 45 which is supplied to the scanning line; a scanning driver means 46 which supplies the pre-scanning line scanning signal Aii; a first line that supplies a signal to the data line
In the case where a second X driver means for supplying a signal to a data line corresponding to a peripheral portion of the matrix display panel, and a video signal corresponding to the aspect ratio of the matrix display panel are introduced. Applying a signal based on the video signal to the first and second X driver means,
When an NTSC type 5 video signal is introduced, a switching stage for applying a signal added to the video signal to the first X driver means and applying a predetermined DC voltage to the second X driver stage; It is equipped with the following. (Function) In the present invention, when an image display panel with the same aspect ratio as the aspect ratio of the 71... Gives a signal based on the video signal.
All pixels of the 1-Risk display panel are driven (images are displayed).On the other hand, when NTSC system video (No.A) is introduced, the first A predetermined DC voltage is applied to the second X driver means.
NTSC video is displayed in the center of the 71-RiX display panel driven by the first X driver means,
A predetermined rask image is displayed on the periphery of the matrix display panel driven by one stage of the second X driver. In this way, images with different aspect ratios can be displayed. (Example) Hereinafter, the present invention will be described in detail based on the drawings. FIG. 1 shows a matrix display panel drive according to the present invention! FIG. 1 is a block diagram showing an example of an lJ device. In FIG. 1, the same components as in FIG. 2 are given the same reference numerals. The R, G, and B signals are supplied to the X driver circuit 32 from a polarity switching circuit (not shown) via the input terminal 30, and the X driver circuit 32 and Y driver circuit 33 are controlled by a controller circuit (not shown), which is the same as in the conventional case. and
The fact that the liquid crystal panel 7 is composed of 960×960 pixels and has an aspect ratio of 16:9 is also the same as in the prior art. The shift register and level converter circuits 34 and 36 of the X driver circuit 32 are composed of 120 bits, and the shift register and level converter circuit 35 is composed of 720 bits. The clock signal from the controller circuit is supplied to all the shift register and level converter circuits 34 to 36 via the input terminal 27, and the start pulse STH from the controller circuit is supplied to the shift register and level converter circuit 34. It is supplied to terminal a of switch 87°S8. switch S7
, the terminals of S8 carry out from the shift register and level converter circuits 34 and 35, respectively.
UT is supplied. Shift register and level converter circuit 35°3 from common terminal C of switch S7.88
A start pulse ST■ is supplied to 6. Shift register and level converter circuits 34 to 36
In both cases, the first bit turns on and outputs an on-pulse at the first clock C after introducing the start pulse STH, and then each time the clock CLK is introduced, the output shifts and each bit turns on in sequence. becomes. The shift register and level converter circuit 34 outputs a carry-out STHOUT when shifted by 120 bits, and the shift register and level converter circuit 35 outputs a carry-out 5 TII OUT when shifted by 720 bits. Note that the controller circuit outputs 960 clocks CL during one horizontal display period when displaying a high-definition television broadcast, and outputs 720 clocks C during one horizontal display period when displaying an NTSC television broadcast. It has become. Shift register and level converter circuits 34 to 36
The on-pulses from are output to three sample-hold and buffer driver circuits 37, respectively. Sample hold and buffer driver circuit 37°39
is composed of 120 stages, and the sample hold/balance driver circuit 38 is composed of 720 stages. A DC voltage is supplied to the input terminal 29, and this DC voltage is applied to the terminals a of the switches 89 and 810. Additionally, R introduced into the input terminal 30 from a polarity switching circuit (not shown)
, G, B signals are supplied to the sample hold and buffer driver circuit 38, and the switches 89, 310
is supplied to the terminal. The DC voltages or R, G, B signals appearing at the common terminals c of the switches 39, 310 are supplied to sample bold and buffer driver circuits 37, 39, respectively. The sample hold and buffer driver circuit 38 samples and holds the R, G, and B signals at the timing of the on-pulse from the shift register and level converter circuit 35. Further, the sample bold and buffer driver circuits 37 and 39 convert DC voltage or R, G at the timing of on-pulses from the shift register and level converter circuits 34 and 36. Sample and hold the B signal. An output instruction signal 0 [ is introduced from the input terminal 31 to the sample bold and buffer driver circuits 37 to 39, and the held signal is output to the data line group of the liquid crystal panel 7 at the timing of the output instruction signal @OE. . The Y driver circuit 33 sequentially outputs scanning signals in a horizontal period during high-definition television broadcast display, and scans all lines of the liquid crystal panel 7 in one vertical scanning period. In addition, when displaying NTSC broadcast, the Y driver circuit 33
Scanning signals are output to two gate line groups G of the liquid crystal panel in the same horizontal scanning period. That is, two lines are scanned in a horizontal period, and all lines are scanned in one direct scanning period. Signals are supplied from the sample hold and buffer 7 driver circuits 37 and 39 to data line groups of 120 pixels on each horizontal side of the liquid crystal panel 7, and lean pull hold signals are supplied to the data line group of 720 pixels in the center. Signals are supplied from the buffer driver circuit 38 and the buffer driver circuit 38. In addition, when the quality television transmission display is set to 7, all switches S7 to 810 are set to terminal [), and the NTS
In the C broadcast display mode, all of the switches S7 to 810 select terminal a. Further, the DC type FF introduced into the input terminal 29 is synchronized with the R, G, and B signals introduced into the input terminal 30. It is necessary to switch the C polarity, and a polarity switching path (not shown) outputs a control signal for switching the polarity of the free current voltage.Next, the operation of the embodiment device configured in this way will be explained. Now select the terminals S7 through 310 to enter the high-definition television broadcast display mode.In this case, the carry signal from the shift register and level converter circuit 34. It is introduced as a start pulse STH into the level converter circuit 35°3G. R, G, and B signals are also supplied to the ripple hold and buffer driver circuits 37 to 39. A start pulse STH is introduced at the start of the display period, and each time the clock C1- is introduced, the shift register and level inverter circuit 34
On-pulses are output sequentially from the first set of outputs. When the on-pulse is shifted by 120 bits, the carry error from the shift register and level converter circuit 34 is
-8THOUT causes the digital register and level inverter circuit 35 to start operating, and the on-pulse shifts sequentially each time the clock CI- is introduced. Thereafter, similarly, on-pulses are sequentially outputted from all bits of the shift 1-1 register and the 1-current converter circuits 34 to 3G at 43 times during one horizontal scanning period. Sample hold and buffer driver circuits 37 to 3
9 sequentially leanbrings and holds the R2G and B signals at the timing of these on-pulses, and outputs the output instruction signal 0.
At the timing [, 1- is simultaneously output to the data line group of the liquid crystal panel 7. The Y driver sequentially outputs scanning signals to the gate line group G in a horizontal period to turn on the TFT 24. In this way, all lines are scanned in one direct scanning period, and one screen of high-definition preview broadcasting is displayed. On the other hand, when displaying an NTSC system J-Revisicon broadcast, the switch S7 to 810 selects the terminal a to display the NTSC broadcast display. In this case,
Shift register and level converter circuits 34 to 36
In both cases, the start pulse 5TI from the input terminal 28
I is supplied. Therefore, when the start pulse STH is introduced from the input terminal 28 and the clock C1- is further introduced, the shift register and level converter circuit 34
Each of the first bits h of No.36 turns on at the same time, and the on-pulse shifts every time the clock CLK is introduced thereafter. circuit 37
．． A DC voltage is supplied to the input terminal 39 from the input terminal 29 . Ripple hold and buffer 7 driver circuit 37.39 is shift 1-register and level: J shift 3 circuit 34.3
The DC voltage is numbered and held at the timing of the on-pulse from 6. Further, the ripple hold and buffer driver circuit 38 samples and holds the R, G, and B signals at the timing of the A pulse from the shift register and level inverter circuit 35. 1], the sample hold and balance driver circuit 3
8 holds 720 color signals. Input terminal 317
When the output instruction signal 0[ from JII is introduced, the signals from the sample hold and balance driver circuits 37 to 39 are simultaneously output to the data line group of the liquid crystal panel 7. The Y driver circuit 33 scans two lines of the liquid crystal panel 7 with one horizontal scanning signal, and scans all lines during the double scanning period. A signal at a constant level is supplied to data line groups of 120 pixels on both sides of the liquid crystal panel 7 in the horizontal direction, and a predetermined rask image is displayed on this portion. 7 in the horizontal center of the liquid crystal panel 7.
The 20-pixel data line group has R, G, and B of NTSC broadcasting.
A signal will be supplied. In this way, the liquid crystal panel 7
NTSC broadcasting is displayed on the 720x960 pixels in the center, and a predetermined rask video is displayed on the 120x960 pixels on both sides. Note that only the shift register and level converter circuit 35 and the sample hold and buffer driver circuit 38 are operated, and the shift register and level converter circuit 3
A method of stopping the operations of 4.36 and sample/hold and buffer driver circuits 37 and 39 is also conceivable. However, in this case, the left and right portions of the liquid crystal panel 7 deteriorate. Particularly, when a low voltage is applied to a normally-on mode liquid crystal that changes its translucency, the left and right portions become white. For this reason, in J3 of this embodiment, a DC voltage of a predetermined level is supplied to the pixels on both the left and right sides of the liquid crystal panel 7 to display a predetermined rask image. Further, by switching the level of the DC voltage introduced to the input terminal 29 based on the color arrangement of the liquid crystal panel 7, a desired color can be displayed on both left and right portions of the liquid crystal panel 7. Note that the present invention is not limited to the above embodiments,
For example, plasma, EL (electroluminescence), LED (light emitting diode), etc. may be used instead of the liquid crystal panel, and NTSC broadcasting may be displayed in a portion other than the center of the liquid crystal panel 7. . [Effects of the Invention] As explained above, according to the present invention, with an extremely simple circuit configuration, a matrix display panel having an aspect ratio different from that of an NTSC video signal can display NTSC video signals.
You can display the video of the method.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of a matrix display panel driving device according to the present invention, Fig. 2 is a block diagram showing a conventional matrix display panel driving device, and Fig. 3 is a block diagram showing an embodiment of a matrix display panel driving device according to the present invention. 1 block diagram specifically showing the configuration of the polarity switching circuit 4, FIG.
A fifth block diagram specifically showing the configuration of the driver circuit 5.
The diagram shows sample hold circuit 14 and buffer 7 driver 1
6 is a circuit diagram specifically showing the configuration of color switching circuit 1.
5 specifically shows the configuration of 1 circuit diagram, and FIG. 7 shows the liquid crystal panel 7.
FIG. 2 is a schematic circuit diagram specifically showing the FIG. 7...Liquid crystal panel, 27 to 31...Input terminal, 3
2...X driver circuit, 33...Y driver circuit,
34 to 36...Shift register and level converter circuit, 37 to 39...Sample hold and buffer driver circuit, S7 to S10...Switch.

Claims (1)

[Claims] Each pixel is arranged in a matrix and has an aspect ratio that is longer in the horizontal direction than the aspect ratio of an NTSC video signal, and the pixels are supplied to the data line and the scanning line. a matrix display panel driven by a scan signal; scan driver means for supplying a scan signal to the scan line; first X driver means for supplying a signal to a data line corresponding to a central portion of the matrix display panel; a second X driver means for supplying a signal to a data line corresponding to a peripheral portion of the matrix display panel; A signal based on the video signal is supplied to the X driver means of the X driver means, and when an NTSC video signal is introduced, a signal based on the video signal is supplied to the first X driver means and the second X driver means is supplied with a signal based on the video signal. 1. A matrix display panel driving device comprising: switching means for applying a predetermined DC voltage.