JP2913612B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to a liquid crystal display device capable of displaying both types of video signals having different numbers of horizontal scanning lines, for example, both video signals of the HDTV system and the NTSC system.

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram showing a configuration example of a conventional TFT active matrix type liquid crystal display device. In the TFT active matrix type liquid crystal display device, a plurality of data signal lines 32 and a plurality of scanning signal lines 33 are orthogonally arranged on a liquid crystal display panel 31 as a display means, and as shown in FIG. A pixel electrode 35 is formed at each intersection of the lines 32 and 33 via a TFT (thin film transistor) 34. Further, the pixel electrode 35
Is formed, a display voltage is applied to a liquid crystal layer disposed in a gap between the pixel electrode 35 and a not-shown counter electrode, and display is controlled by controlling the brightness of each pixel. Done. The operation principle will be described below.

In a TFT active matrix type liquid crystal display device, a data signal having display light / dark information is applied to each data signal line 32, and a plurality of scanning signal lines 3 are simultaneously supplied.
3, a TFT 34 is connected to one specific scanning signal line 33.
A selection signal for turning on is applied. At this time, the data signal having the brightness information is transmitted to the pixel group of one horizontal row (one horizontal display line) connected to the selected scanning signal line 33 via the TFT 34, and the display of one horizontal row is performed. Done. Such an operation is synchronized with the video signal (data signal) to set the scanning signal line 33 at the uppermost position (upper side in FIG. 11).
, One screen at a time is selected one by one from the scanning signal lines 33 to display one screen.

In order to perform these operations, a data signal line driving circuit 36 and a scanning signal line driving circuit 37 are provided, and the data signal line driving circuit 36 and the scanning signal line driving circuit 37 are provided.
Are controlled by a control circuit 38 that operates based on a synchronization signal supplied from a video signal source 41, and a video signal is supplied from the video signal source 41 to the data signal line driving circuit 36.

The scanning signal line driving circuit 37 generally includes a shift register circuit, a level shifter for converting a voltage necessary for operating the TFT 34, and an output buffer. On the other hand, the data signal line driving circuit 36 performs a sampling operation to distribute the video signal input as an analog signal to the plurality of data signal lines 32.

More specifically, the data signal line drive circuit 36 mainly includes a shift register circuit 39 and a sampling circuit 40 as shown in FIG. The shift register circuit 39 sequentially shifts the start signal given from the control circuit 38 by a clock signal, and outputs sampling pulses Sa1, Sa2,... To the sampling circuit 40. The sampling circuit 40 samples the video signal supplied from the video signal source 41 at a different timing for each of the data signal lines S1, S2,... By using the sampling pulses Sa1, Sa2,. A capacitor 42 for holding the voltage applied to the data signal line 32 until the next sampling is connected to the output terminal side of the sampling circuit 40.

The data signal line drive circuit 36 has an analog memory which latches and stores the same number of data as the number of data signal lines obtained by sampling at the same time after all sampling.
In a driver monolithic type active matrix liquid crystal display device using T or the like, in which a drive circuit is formed on a substrate together with a pixel TFT, it is common not to use an analog memory in order to simplify the circuit.

FIG. 13 is a timing chart showing the operation of the liquid crystal display device shown in FIG. The data signal line driving circuit 36 and the scanning signal line driving circuit 37
The operation timing of each signal output from is set as described below.

The data signal line driving circuit 36 repeats a series of operations in synchronization with the horizontal scanning cycle of the video signal. That is, in one horizontal period (for example, about 63.6 μsec in the NTSC system) of the video signal shown in FIG. 13 (1), as shown in FIG. In the period indicated by reference numeral Wa in FIG.
The timings of the start signal and the clock signal of the shift register circuit 39 are set so that the sampling pulses Sa1 to SaN correspond to the range of c). In the data signal lines S1 to SN, as shown in FIG. 13C, the data is updated at the sampling timing of the sampling circuit 40 corresponding to each data signal line.

On the other hand, the scanning signal line driving circuit 37 also operates in synchronization with the horizontal scanning period. That is, as shown in FIG. 13D, a selection signal having a width of one horizontal period is applied to each scanning signal line 33, and the application start and end times tG are set to one horizontal period. The time is set from the time tE at which the sampling of the minute is completed to the time tS at which the next sampling is started.

At this time, a data signal is written from the data signal line 32 to the pixel electrode 35 through the TFT 34 connected to the scanning signal line 33 to which the selection signal is applied. The reference numeral 35 is electrically disconnected from the data signal line 32, and the voltage applied to the pixel electrode 35 is maintained as it is by the capacitance of the capacitor or the liquid crystal. In the example of FIG. 13, a voltage indicated by a circle is written to each of the pixels connected to the x-th scanning signal line Gx, and a voltage indicated by a cross is written to each of the pixels connected to the x + 1-th scanning signal line Gx + 1. Written.

At this time, in the TFT 34 of each pixel,
It is necessary to finish charging the pixel electrode 35 between the time when the data signal on the data signal line 32 is updated and the time when the selection signal given from the scanning signal line 33 ends. Therefore, the change time tG of the selection signal must be some time after the time tE, and is usually set to a timing relatively close to the time tS. In the case of the NTSC system, the time from time tE to time tS is about 11 μsec. Therefore, if the polysilicon TFT is used for the switching element, the pixel electrode 35 can be sufficiently charged.

[0013]

In recent years, it has been observed that HDTV (high definition), which is a new television system, has advanced to a practical use level and will soon be used for home use. At that time, the current N
It is disadvantageous in terms of space to install two TSC television receivers and two HDTV television receivers side by side.
A television receiver capable of displaying both NTSC and HDTV on a stand is desired.

By the way, in the receiver for both HDTV and NTSC, there is a problem that the screen aspect ratio differs between NTSC and HDTV. NTSC
Is 3: 4, whereas HDTV is 9:16 (= 3:
5.33), which is considerably wider than NTSC. When two methods having different aspect ratios are to be displayed on one display device, the following four display methods can be considered.

FIG. 14 is a diagram for explaining the four display methods. FIGS. 14 (1) and 14 (2) show display methods when the aspect ratio of the display device is set to 9:16 in accordance with HDTV, and FIGS. 14 (3) and 14 (4).
Shows a display method when the aspect ratio of the display device is 3: 4 in accordance with NTSC.

FIG. 14A shows an aspect ratio of the display device set to HD.
When displaying 9:16 in accordance with TV and displaying NTSC, all video signals are displayed so that video signals are not lost.
A display method is shown in which a part of the display device is set as an area in which no image is displayed (an area indicated by hatching).

FIG. 14 (2) shows the aspect ratio of the display device set to HD.
When displaying 9:16 in accordance with TV and displaying NTSC, a display method is shown in which video is displayed using the entire display device and a part of a video to be originally displayed (a region shown by a broken line in the figure) is cut. ing.

FIG. 14C shows the aspect ratio of the display device as NT.
3: 4 according to SC, and when displaying HDTV, all video signals are displayed so that video signals are not lost.
A display method is shown in which a part of the display device is set as an area where image display is not performed (an area indicated by hatching in the figure).

FIG. 14D shows the aspect ratio of the display device as NT.
In the case of 3: 4 in accordance with SC, when displaying HDTV, a display method is shown in which video is displayed using the entire display device and a part of a video to be originally displayed (a region shown by a broken line in the figure) is cut. ing.

Of the above four display methods, FIG.
In the display method in which a part of the video signal is cut as shown in (2) and FIG. 14 (4), the value may be significantly reduced depending on the video signal, which is not desirable. On the other hand, as shown in FIG. 14 (3), in a display method in which the aspect ratio of the display device itself is adjusted to NTSC, an HDTV
Since the image is displayed in an area considerably smaller than the size of the display device at the time of the display, the feature of the HDTV, in which the image quality is emphasized as the size of the large screen is not so much exhibited, is not effective. For this reason, the display method shown in FIG. 14A is most rational for the receiver for both HDTV and NTSC.

Here, H of the display method shown in FIG.
When the DTV / NTSC dual-purpose receiver is realized in the liquid crystal display device shown in FIG. 11 described above, the aspect ratio of the display device itself is set in accordance with HDTV.
There is no particular problem with the display of V. On the other hand, when performing the NTSC display on this liquid crystal display device, the following problem occurs.

FIG. 15 is a timing chart for explaining the problem. When performing NTSC display on a liquid crystal display device having an HDTV aspect ratio, an image is displayed in an area 3/4 near the center with respect to the horizontal length.
As shown in (3), the sampling pulses Sai + 1 to Saj are supplied to the sampling circuits of the data signal line driving circuit 36 corresponding to the number of data signal lines in the central part ／ of the plurality of data signal lines 32 provided. And FIG.
It is necessary to perform sampling of the effective period Wa of the video signal shown in (1).

However, in the liquid crystal display device shown in FIG. 11 described above, sampling is continuously performed on the sampling circuits corresponding to all the data signal lines 32. 3
2 are supplied with sampling pulses Sa1 to Sai; Saj + 1 to SaN, so that sampling is performed outside the valid period (blanking period) as shown in FIGS. 15 (2) and 15 (4). Will be done.

That is, the period required for all sampling is longer than that required for a conventional liquid crystal display device exclusively for NTSC. Therefore, the period from the completion of sampling for one horizontal period to the start of the next sampling is relatively short, and as a result, the end time of the application of the selection signal to the scanning signal line 33 from the last sampling time tE. The period up to tG is also greatly reduced. For this reason, at the right end of the screen, the pixel electrode is not sufficiently charged through the TFT 34, and a sufficient display voltage cannot be applied to the liquid crystal.

An object of the present invention is to provide a liquid crystal display panel having the same aspect ratio as that of a predetermined specific video signal, and to display a good image when displaying an image signal having a different aspect ratio. It is to provide a liquid crystal display device which can perform the above.

[0026]

According to the present invention, a plurality of data signal lines and a plurality of scanning signal lines are arranged orthogonally, and switching is controlled on / off by a scanning signal line at an intersection of each signal line. A pixel electrode connected to the data signal line via the element, a liquid crystal display panel including a counter electrode facing the plurality of pixel electrodes, a data signal line driving circuit for applying a display signal to the plurality of data signal lines, A scanning signal line driving circuit that applies a selection signal for turning on a switching element line-sequentially to the plurality of scanning signal lines; and a control circuit that controls the data signal line driving circuit and the scanning signal line driving circuit. Wherein the data signal line drive circuit comprises:
A left end portion, a center portion, and a right end portion which are divided along the arrangement direction of the data signal lines include three data signal line groups,
The control circuit includes a corresponding left end drive circuit, a center drive circuit, and a right end drive circuit, and the control circuit is configured to display a video signal having the same aspect ratio as the liquid crystal display panel. The liquid crystal display panel is operated in the order of the drive circuit for the section, the drive circuit for the center section, and the drive circuit for the right end, having an aspect ratio different from that of the liquid crystal display panel. When a video signal during the scanning period is displayed, only the pixel corresponding to the data signal line connected to the center driving circuit is displayed. When such a video signal is displayed, the driving for the center is performed. A liquid crystal display device characterized in that the driving circuit for the left end and the driving circuit for the right end are operated simultaneously before or after the operation of the circuit.

According to the present invention, the left end drive circuit and the right end drive circuit may include a predetermined reference signal different from the video signal on the data signal line when displaying the video signal having the different aspect ratio. Is applied.

The present invention further provides a driving circuit for the left end,
The ratio of the number of data signal lines connected to each of the center drive circuit and the right end drive circuit is approximately 1: 6:
It is characterized in that it is selected as 1.

[0029]

According to the present invention, a plurality of data signal lines constituting the liquid crystal display panel are divided into three signal line groups, that is, a left end portion, a center portion, and a right end portion. Drive circuit, the center drive circuit, and the right end drive circuit are connected and driven individually. When displaying a video signal having the same aspect ratio as the liquid crystal display panel, for example, an HDTV signal, the video signal is output every horizontal period in the order of the left end drive circuit, the center drive circuit, and the right end drive circuit. Sampling is performed and a data signal is applied to a plurality of data signal lines to drive display of each pixel electrode of the liquid crystal display panel.

When displaying a video signal having an aspect ratio different from the aspect ratio of the liquid crystal display panel, for example, an NTSC signal, a group of data signal lines at the center of the plurality of data signal lines is used for displaying the NTSC signal. In the case of displaying the NTSC signal, the central driving circuit that supplies the data signal only to the data signal line group in the central portion in the case of displaying the NTSC signal, Perform sampling.

On the other hand, in the display area corresponding to the left end and the right end of the liquid crystal display panel, an image irrelevant to the applied NTSC signal, such as black on one screen, white on one screen, or gray on one screen, is displayed. Therefore, at the stage of supplying the data signal to the left end and right end data signal lines, it is not always necessary to perform sampling. Therefore, the drive circuit for the left end and the drive circuit for the right end include the drive circuit for the center. It operates independently of the circuit.

If the operation time of the left-end driving circuit and the right-end driving circuit is shorter than the time required for sampling when the video signal is sampled, the video signal is supplied to the data signal line accordingly. There is a margin in the time until the application of the selection signal is completed in the scanning signal line,
A sufficient display voltage can be applied to the liquid crystal of the liquid crystal display panel.

For example, after sampling the video signal of the center drive circuit, the left end drive circuit and the right end drive circuit simultaneously perform a sampling operation, so that all the data signal lines are successively and sequentially. Compared to the case where sampling is performed and the data signal is applied, the operation time can be reduced by the time required for sampling the data signal line connected to the left end driving circuit or the right end driving circuit, and the final sampling is performed accordingly. A long period from the time to the end time of the application of the selection signal on the scanning signal line can be secured long. In this case, the left and right ends of the screen are displayed as a video signal during a blanking period, that is, black display. The same effect can be obtained even if the above-described simultaneous sampling operation of the left end drive circuit and the right end drive circuit is performed prior to the operation of the center drive circuit.

According to the present invention, a video signal having an aspect ratio different from the aspect ratio of the display panel, for example, N
At the time of displaying the TSC signal, the driving circuit for the left end and the driving circuit for the right end do not perform the sampling operation, and a predetermined reference signal different from the video signal is simultaneously applied to the connected data signal lines simultaneously. You.

For example, if each circuit is configured so that the same signal voltage is applied to each data signal line of the left end drive circuit and the right end drive circuit through a switching element controlled by a common switching signal, The period required to supply data signals to all data signal lines is
Other than the valid period of the video signal, only the period for operating the switching element is sufficient, and the period from when the signal is finally given on all the data signal lines until the application of the selection signal is completed is shorter than the above case. It can be secured longer. In this case, the so-called solid display of the brightness corresponding to the voltage value of the given reference signal is provided at the left and right ends of the screen.

Further, according to the present invention, the ratio of the number of data signal lines connected to each of the left end drive circuit, the center drive circuit, and the right end drive circuit is generally selected to be 1: 6: 1. It is. That is, in the liquid crystal display device of the present invention, in order to display both the HDTV signal and the NTSC signal, the aspect ratio of the liquid crystal display panel is 9:16 in accordance with the HDTV signal. When an NTSC signal having an aspect ratio of 3: 4 is displayed on this liquid crystal display panel with its upper and lower ends aligned with the frame of the liquid crystal display panel, the displayed image is approximately 3/4 with respect to the horizontal direction of the liquid crystal display panel.
It is displayed using an area with a ratio of 4.

Therefore, if the non-display area is equally distributed to both the left and right ends in a balanced manner, the occupied widths of the non-display area, the display area, and the non-display area in order from the left end of the screen are approximately 1: 6: The ratio is 1. For this reason, as described above, the division of the data signal lines of the liquid crystal display device of the present invention is also performed by setting the number of the respective data signal lines to approximately the left end portion: the center portion: the right end portion to be 1: 6: 1. By distinguishing the circuits for image display or non-display, respectively, it is possible to effectively display both the HDTV signal and the NTSC signal.

[0038]

FIG. 1 is a circuit diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention. The liquid crystal display device of this embodiment is a TFT active matrix type liquid crystal display device, and its liquid crystal display panel 1 has a plurality of data signal lines 2.
And a plurality of scanning signal lines 3 are arranged orthogonally, and a TFT (thin film transistor) is provided at each intersection of the two signal lines 2 and 3.
4, a pixel electrode 5 is formed. One counter electrode is formed over substantially the entire display surface of the liquid crystal display panel 1 so as to face the pixel electrode 5. A liquid crystal layer is interposed between the pixel electrode 5 and a counter electrode (not shown), and display is performed by applying a display voltage to the liquid crystal layer interposed between the electrodes to control the brightness of each pixel. The operation principle will be described below.

In the TFT active matrix type liquid crystal display device, a data signal having display light / dark information is applied to each data signal line 2 and at the same time, a specific one of the plurality of scanning signal lines 3 is applied to one of the plurality of scanning signal lines 3. , A selection signal for turning on the TFT 4 is applied. At this time, the brightness information is transmitted to the pixel group forming one horizontal line connected to the selected scanning signal line 3 via the TFT 4, and the display for one horizontal line is performed. In this manner, the scanning signal line 3 is synchronized with the video signal (data signal) and the liquid crystal display panel 1
, For example, one by one from the scanning signal line 3 at the top, one screen at a time is displayed.

In order to perform these operations, the data signal line drive circuits 6L and 6L for the left end, the center and the right end are required.
C, 6R (indicated by reference numeral 6 when collectively referred to) and a scanning signal line driving circuit 7 are connected, and both the data signal line driving circuit 6 and the scanning signal line driving circuit 7 are connected to the video signal source 11.
Control circuit 8 that operates based on a synchronization signal given from
The video signal is supplied from the video signal source 11 to the data signal line drive circuit 6.

The control circuit 8 includes signal lines L1, L2, L
3, a start signal to be described later is supplied to each of the driving circuits 6L, 6C, 6R, and a common clock signal is supplied to the driving circuits 6L, 6C, 6R via a signal line L4.

The scanning signal line driving circuit 7 is generally composed of a shift register, a level shifter for converting a voltage necessary for operating the TFT 4, and an output buffer. On the other hand, the data signal line drive circuit 6 performs a sampling operation to allocate a video signal input as an analog signal to the plurality of data signal lines 2.

FIG. 2 is a circuit diagram showing a configuration of the data signal line drive circuit 6. The data signal line drive circuit 6 is mainly composed of a shift register 9 and a sampling circuit 10, as shown in FIG. The shift register 9 sequentially shifts a start signal given from the control circuit 8 by a clock signal, and performs sampling pulses Sa1, Sa2,.
Is output. The sampling circuit 10 samples and outputs a video signal at a different timing for each data signal line according to the sampling pulses Sa1, Sa2,. A capacitor 12 for holding the video signal (display voltage) supplied to the pixel electrode 5 until the next sampling is connected to the output terminal side of the sampling circuit 10.

In the liquid crystal display device of this embodiment, the aspect ratio (aspect ratio) of the liquid crystal display panel 1 is set to 9:16 in accordance with the HDTV signal. In the present liquid crystal display device, the data signal line 2 is connected to 1/8, 6/8, 1
/ 8 divided into three data signal line groups, and for each data signal line group, a left end data signal line drive circuit 6L, a central data signal line drive circuit 6C, and a right end data signal line. A drive circuit 6R is provided.

For example, if the number of all data signal lines 2 is 120
Assuming that the number is 0, the left side 1 of the liquid crystal display panel 1 in FIG.
The 50 data signal lines are driven by the left end data signal line drive circuit 6L, the center 900 are driven by the center data signal line drive circuit 6C, and the right 150 data signal lines are driven by the right end data signal line drive circuit. Each is driven by the circuit 6R. These data signal line drive circuits 6L, 6
Each of C and 6R has the configuration shown in FIG. 2, and there is no difference other than the number of connected data signal lines.

Each data signal line drive circuit 6L, 6C, 6R
It is assumed that the first sampling pulse is generated after a lapse of a predetermined clock cycle from the input of the start signal from the control circuit 8. The clock signals input to each of the data signal line driving circuits 6L, 6C, 6R are all common, but the start signal gives an independent signal.

The data signal line drive circuit 6 includes an analog memory which latches and stores the same number of data as the number of data signal lines obtained by sampling at the same time after all sampling.
In a driver monolithic active matrix type liquid crystal display device in which a driving circuit using a TFT or the like is formed on a substrate together with a pixel TFT, it is common to not use the analog memory in order to simplify the circuit.

Hereinafter, the case where the HDTV signal is displayed and the case where N
The case where the TSC signal is displayed will be described.

FIG. 3 is a timing chart showing the operation when displaying an HDTV signal. When an HDTV signal is displayed in the liquid crystal display device of the present embodiment, a video signal of a valid period is displayed in the entire display area of the liquid crystal display panel 1, so that it is input to each of the three driving circuits. Three start signals are given at timings as shown in FIGS. 3 (2) to 3 (4). This timing is determined by each of the drive circuits 6L and 6L.
With respect to the operation of the sampling circuits in C and 6R, timing such that the last stage of the drive circuit 6L and the forefront of the drive circuit 6C are continuous, and the last stage of the drive circuit 6C and the forefront of the drive circuit 6R are continuous. It is. That is, the operations of the three drive circuits 6L, 6C, 6R are, as a whole, equal to the operations performed by one drive circuit having a single shift register, that is, as shown in FIG.
As shown in the timing chart, the timing of the start signal is determined. Thus, the display of the HDTV signal is performed normally.

When NTSC Signal is Displayed FIGS. 4 and 5 are timing charts showing the operation when displaying an NTSC signal. In the case of displaying an NTSC signal in the liquid crystal display device according to the present embodiment, in this case, a video signal is displayed in an area corresponding to 900 data signal lines in a central portion of the liquid crystal display panel 1. Therefore, the timings of the three start signals to be input to the drive circuits 6L, 6C, and 6R are set as shown in FIG. 4 so that only the central data signal line drive circuit 6C performs sampling of the video signal during the valid period. Also defines the clock frequency.

Each start signal of the drive circuits 6L and 6R is
After the end of the sampling operation in the drive circuit 6C, it is given simultaneously. As a result, sampling is performed in the driving circuits 6L and 6R during the blanking period, and regions corresponding to the 150 data signal lines on both the left and right ends of the liquid crystal display panel 1 are displayed in black. The sampling operation of the drive circuits 6L and 6R may be performed prior to the sampling operation of the drive circuit 6C.

As described above, the sampling in the left end data signal line drive circuits 6L and 6R in the right end data signal line drive circuits 6R and 6R is performed simultaneously in parallel.
Compared with the case where R is sampled at another time, the time for applying a voltage to 1200 data signal lines 12 by sampling is shorter, and the time for charging the pixel electrode is correspondingly longer. Thereby, the display quality of the liquid crystal display panel 1 is improved.

Referring to FIG. 5 in more detail,
In the valid period W of the video signal shown in FIG.
As shown in (3), the central data signal line drive circuit 6C
Performs sampling of the video signal based on the sampling pulses Sai + 1 to Saj. As a result, FIG.
As shown in (5), a display voltage corresponding to the video signal at the timing of each sampling signal is applied to the data signal lines Si + 1 to Sj.

Further, as shown in FIGS. 5 (2) and 5 (4), the data signal line driving circuit 6 for the left end and the right end is provided.
L and 6R are sampling pulses Sa1 to Sai; Sa
The sampling in the blanking period is executed based on j + 1 to SaN. As a result, as shown in FIG. 5 (5), a display voltage corresponding to a signal different from the video signal is applied to the data signal lines S1 to Si; Sj + 1 to SN.

Further, the scanning signal line driving circuit 7 operates in synchronization with the horizontal scanning period. That is, as shown in FIG. 5 (6), the selection signals..., Gx, Gx + 1,.
Is applied. The application start and application end time tG of the selection signal is from a time tE at which sampling for one horizontal scanning period is completed to a time t at which the next sampling is started.
It is set before S.

As described above, as compared with the case where sampling is continuously performed on all data signal lines, the data signal lines S1
.About.Si, the sampling time is shortened by the time required for sampling, and accordingly, the period from the final sampling time tE to the application signal end time tG on the scanning signal line can be secured longer. In this case, the left and right ends of the screen of the liquid crystal display panel 1 display a video signal during a blanking period, that is, black display. The sampling by the left end and right end data signal line drive circuits 6L and 6R may be performed prior to the sampling operation by the central data signal line drive circuit 6C.

FIG. 6 is a block diagram showing the configuration of the second embodiment of the present invention. This embodiment is similar to the embodiment shown in FIG. 1, and the same components are denoted by the same reference numerals. The feature of the present embodiment is that, in addition to the function of sampling the video signal supplied from the video signal source 11, the function of sampling the predetermined reference signal supplied from the control circuit 8 is added, and the sampling output of the video signal and the sampling of the reference signal are performed. That is, the left end and right end data signal line drive circuits 16L and 16R that output any one of the outputs are used.

The control circuit 8 sends a reference signal to the drive circuits 16L and 16R via a signal line L5, an H / N signal to be described later via a signal line L6, and a signal line L7.
, A switching signal Psw to be described later is given.

FIG. 7 shows a data signal line driving circuit 1 for the left end.
FIG. 6 is a circuit diagram showing a configuration of 6L. The same applies to the configuration of the right end data signal line drive circuit 16R. The left end data signal line drive circuit 16L includes a shift register 17,
The circuit includes a sampling circuit 18, a switching element 19, a changeover switch 20, and a capacitor 21.

The shift register 17 sequentially shifts a start signal supplied from the control circuit 8 by a clock signal supplied from the control circuit 8 and outputs sampling pulses Sa1, Sa2,. The sampling circuit 18 samples the video signal supplied from the video signal source 11 at the input timing of the sampling pulse, that is, samples the video signal at a different timing for each data signal line, and outputs the sampling result to one of the switches 20. Give to terminal. The switching element 19 converts the reference signal supplied from the control circuit 8 into a common switching signal Psw supplied from the control circuit 8.
Selectively applied to the other terminal of the changeover switch 20.

The changeover switch 20 connects one of the output of the sampling circuit 18 and the output of the switching element 19 to a data signal line connected thereto, based on the H / N signal which is a changeover signal given from the control circuit 8. S1,
Are output to S2,. That is, when the video signal is an HDTV signal, the output of the sampling circuit 18 is applied to the data signal line, and when the video signal is an NTSC signal, the output of the switching element 19 is applied to the data signal line. The capacitor 21 controls the display voltage applied to the data signal line,
Hold until the next sampling timing.

Hereinafter, the case of displaying the HDTV signal and the case of N
The case where the TSC signal is displayed will be described.

FIG. 8 is a timing chart showing an operation for displaying an HDTV signal. When displaying the HDTV signal in the liquid crystal display device of the present embodiment, H / H signals are generated in the left and right end data signal line drive circuits 16L and 16R.
The changeover switch 20 outputs the sampling result of the sampling circuit 18 to the data signal line 2 in response to the N signal.
The other operations are exactly the same as the case of displaying the HDTV signal in the liquid crystal display device of the above-described embodiment.

That is, since the video signal of the valid period is displayed in the entire display area, each data signal line driving circuit 16
For the L, 6C and 16R, the start signal is changed as shown in FIG.
8 at a timing as shown in FIG. This timing relates to the operation of the sampling circuits in each of the drive circuits 16L, 6C, and 16R, in which the last stage of the left end data signal line drive circuit 16L and the forefront stage of the center data signal line drive circuit 6C are continuous. And the last stage of the data signal line driving circuit 6C for the center part and the data signal line driving circuit 1 for the right end part
The timing is such that the first stage of 6R is continuous.

That is, the three drive circuits 16L, 6C,
16R, as a whole, as if it were the same as the operation performed in one drive circuit having a single shift register, that is, as shown in the timing chart of FIG. Is determined. Thus, the display of the HDTV signal is performed normally.

When NTSC Signal is Displayed FIGS. 9 and 10 are timing charts showing the operation when displaying an NTSC signal. When displaying an NTSC signal in the liquid crystal display device of the present embodiment, in this case, an image is displayed in a display area corresponding to 900 data signal lines at the center of the liquid crystal display panel 1. Therefore, as shown in FIG. 9 (2), the timing of the start signal given to the central part data signal line drive circuit 6C is set at the beginning of the effective period of the video signal, and the central part data signal line drive circuit 6C The frequency of the clock signal is set so that the sampling of the video signal during the valid period is performed.

The data signal line driving circuits 16L and 16R for the left end and the right end are controlled so that the control signal given from the control circuit 8 is output to the data signal line 2 by the H / N.
The switching signal 20 is switched and set by a signal, and sampling is not performed. That is, at a certain point in one horizontal scanning period, the common switching signal Psw is supplied to the switching element 19 to be turned on at the same time, and all data connected to the left end and right end data signal line drive circuits 16L and 16R are connected. A reference signal is applied to the signal line 2 at the same time.

In the example shown in FIG. 9 (3), immediately after the sampling in the data signal line driving circuit 6C for the central part is completed, the common switching signal is transmitted to the data signal line driving circuits 16L and 16R for the left and right ends. Psw is given. The time for turning on the switching element 19 by the common switching signal Psw may be an extremely short time. Therefore, the time required to apply a signal to the 1200 data signal lines 2 is slightly longer than the effective time. A long period is fine.
As a result, a sufficient time for charging the pixel electrode can be secured.

More specifically, referring to FIG. 10, the sampling in the data signal line driving circuit 6C for the central portion within the valid period W of the video signal shown in FIG. The reference signal is transmitted by the data signal line drive circuits 16L and 16R. That is, as shown in FIG. 10 (2), the central part data signal line drive circuit 6C samples the video signal by the sampling pulses Sai + 1 to Saj.
As a result, as shown in FIG. 10D, a display voltage as a sampling result is applied to the data signal lines Si + 1 to Sj.

The central data signal line drive circuit 6C
After the end of the sampling operation, the common switching signal Psw shown in FIG. 10 (3) is supplied to the left end and right end data signal line drive circuits 6L and 6R. As a result, FIG.
As shown in (4), the data signal lines S1 to Si, Sj +
A reference signal is simultaneously applied to 1 to SN as a display voltage.

On the other hand, each scanning signal line 3
0 (5), selection signals..., Gx, Gx + 1,... Each having a width of one horizontal scanning period are applied.
The application start and end times tG are set from time tE when the sampling and reference signal transfer periods for one horizontal scanning period are completed to time tS when the next sampling is started.

In the liquid crystal display device of this embodiment, the data signal line driving circuits 16L and 16R
Only the time required to operate the switching element 19 in the above is sufficient, and the period from the final application of the signal on all the data signal lines to the end of the application of the selection signal is longer than in the above-described embodiment. Can be secured. In this display method, the left and right ends of the liquid crystal display panel 1 are in a so-called solid display with a brightness corresponding to the voltage value of the reference signal.

As described above, according to each of the above embodiments, the HDTV signal and the NTS signal having different aspect ratios (aspect ratios) are provided.
Both video signals of the C signal can be displayed well.

[0074]

As described above, according to the present invention, the drive circuit for the left end and the drive circuit for the right end are operated independently of the drive circuit for the center, so that the aspect ratio of the liquid crystal display panel is reduced. When displaying video signals having different aspect ratios, if the operation time of the left end drive circuit and the right end drive circuit is shorter than the time required for sampling when the video signal is sampled, As a result, there is a margin in the time from the application of the video signal to the data signal line to the end of the application of the selection signal in the scanning signal line, and a sufficient display voltage can be applied to the liquid crystal of the liquid crystal display panel.

According to the present invention, when displaying an image signal having an aspect ratio different from the aspect ratio of the display panel described above, the left end drive circuit and the right end drive circuit do not perform a sampling operation. A predetermined reference signal different from the video signal is simultaneously applied to the connected data signal lines in a lump. As a result, the period from when the signal is finally applied to all the data signal lines to when the selection signal is completely applied can be secured longer than in the case described above. In this case, the so-called solid display of the brightness corresponding to the voltage value of the given reference signal is provided at the left and right ends of the screen.

Further, according to the present invention, in order to display both the HDTV signal and the NTSC signal, the aspect ratio of the liquid crystal display panel is set to 9:16 in accordance with the HDTV signal.
Is used. When an NTSC signal having an aspect ratio of 3: 4 is displayed on the liquid crystal display panel so that the upper and lower ends thereof are approximately aligned with the frame of the liquid crystal display panel, the display image is approximately ／ of the horizontal direction of the liquid crystal display panel. Is displayed using an area with the ratio of Is approximately a 1: 6: 1 ratio. For this reason,
Regarding the division of the data signal lines, the number of the lines is generally set to the left end part: the center part: the right end part = 1: 6: 1, and the driving circuits for each data signal line group are used for image display.
Or by distinguishing them for non-display,
It is possible to display both the TV signal and the NTSC signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a data signal line driving circuit 6 used in the first embodiment.

FIG. 3 is a timing chart when displaying an HDTV signal in the liquid crystal display device of the first embodiment.

FIG. 4 is a timing chart when displaying an NTSC signal in the liquid crystal display device of the first embodiment.

FIG. 5 is a timing chart when displaying an NTSC signal in the liquid crystal display device of the first embodiment.

FIG. 6 is a block diagram illustrating a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a data signal line drive circuit 16L used in the second embodiment.

FIG. 8 is a timing chart when an HDTV signal is displayed on the liquid crystal display device of the second embodiment.

FIG. 9 is a timing chart when displaying an NTSC signal in the liquid crystal display device of the second embodiment.

FIG. 10 illustrates a liquid crystal display device according to a second embodiment in which NTSC is used.
6 is a timing chart when a signal is displayed.

FIG. 11 is a block diagram illustrating a configuration of a conventional liquid crystal display device.

FIG. 12 is a circuit diagram showing a configuration of a data signal line driving circuit used in a conventional liquid crystal display device.

FIG. 13 is a timing chart when a conventional liquid crystal display device displays an NTSC signal.

FIG. 14 is a diagram for explaining a display method when displaying video signals having different aspect ratios on one display device.

FIG. 15 is a timing chart when an NTSC signal is displayed on a display device compatible with HDTV.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Data signal line 3 Scan signal line 4 TFT 5 Pixel electrode 6L, 16L Left end data signal line drive circuit 6C Central part data signal line drive circuit 6R, 16R Right end data signal line drive circuit 7 Scan Signal line drive circuit 8 Control circuit 9, 17 Shift register 10, 18 Sampling circuit 11 Video signal source 19 Switching element 20 Switching switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 3 / 20,3 / 36 H04N 5/38-5/46 H04N 5/66-5/74 H04N 7 / 00-7/088

Claims (3)

(57) [Claims] 1. A plurality of data signal lines and a plurality of scanning signal lines are arranged orthogonally, and pixel electrodes are connected to a pixel electrode via switching elements whose ON / OFF are controlled by the scanning signal lines at intersections of the signal lines. A liquid crystal display panel connected to a signal line and having a counter electrode facing the plurality of pixel electrodes; a data signal line drive circuit for applying a display signal to the plurality of data signal lines; and a line connected to the plurality of scanning signal lines A scanning signal line driving circuit for sequentially applying a selection signal for turning on a switching element; and a control circuit for controlling the data signal line driving circuit and the scanning signal line driving circuit, wherein the data signal line driving circuit A left end driver circuit corresponding to three data signal line groups of a left end, a center, and a right end divided along the arrangement direction of the data signal lines; Driving circuit, and consists of a right end portion driving circuit, the control circuit, when performing display of the video signal having the same aspect ratio and the liquid crystal display panel, the left end drive circuit,
Operate the drive circuit for the center and the drive circuit for the right end in this order,
The video signal having a different aspect ratio from that of the liquid crystal display panel and displaying the video signal of the first and last horizontal scanning periods of the video signal on the upper and lower display lines of the liquid crystal display panel is connected to the data signal connected to the center driving circuit. When displaying such a video signal in which only the display of the pixel corresponding to the line is performed, the drive circuit for the left end and the drive circuit for the right end are simultaneously operated before or after the operation of the center drive circuit. A liquid crystal display device comprising: 2. The driving circuit for a left end and the driving circuit for a right end apply a predetermined reference signal different from a video signal to a data signal line when displaying a video signal having a different aspect ratio. The liquid crystal display device according to claim 1, wherein: 3. A ratio of the number of data signal lines connected to each of the left end drive circuit, the center drive circuit, and the right end drive circuit is selected to be approximately 1: 6: 1. The liquid crystal display device according to claim 1 or 2, wherein: