JPH03212861A - Digital servo device - Google Patents

Abstract

PURPOSE:To prevent phase deviation output going to disturbance by presetting and latching deviation zero at the falling position of a head switching signal in an unlocked state. CONSTITUTION:A reference value is preset at a speed comparison counter 12 from a speed preset data generation circuit 11 with rotating speed information(FG signal), and a count value at that time is latched at a position delayed by one cycle from a preset position, then, it is set as rotating speed deviation output. The reference value is preset at a phase comparison counter 16 from a phase preset data generation circuit 15 when the count value of the phase comparison counter 16 shows NF, and the count value is latched with a phase latch circuit 17, then, it is set as the phase deviation output. The value of deviation zero is preset at the phase comparison counter 16 at the falling position of the head switching signal when rotating speed is set at the unlocked state, and the deviation zero of the phase comparison counter 16 is latched with the phase latch circuit 17. Thereby, it is possible to prevent servo disturbed with the phase deviation output even immediately after a state is changed from the unlocked state to a locked state.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital servo device for controlling rotational speed and rotational phase.

Conventional technology FIG. 3 shows a conventional digital servo device.

Based on the rotational speed information (hereinafter referred to as FG multiplication signal), the speed preset data generation circuit 1 presets the reference value Nps into the speed comparison counter 2.

A speed comparison counter 2 performs counting, and a speed latch circuit 3 latches the counted value at a position one cycle behind the preset position. The latched count value becomes the rotation speed deviation output. When the count value of the phase comparison counter 6 is NF, the reference value Npp is output from the phase preset data generation circuit 7.
Reset the phase comparison counter 6 and perform counting. At the falling position of the head switching signal, the count value of the phase comparison counter 6 is latched by the phase latch circuit 8 to provide a phase deviation output. When the NL-NH detection circuit 4 detects that the speed deviation output is outside the predetermined value (outside the control range), the phase deviation output is set to zero to perform only rotational speed control without controlling the rotational phase. This is because the rotational phase deviation output when the rotational speed is outside the control range is not a normal control output, so the phase deviation output itself becomes a disturbance element.

This is to set the phase deviation output to zero to prevent disturbance due to the phase deviation output.

Problems to be Solved by the Invention In the case of such a conventional configuration, as shown in the timing chart of Fig. 4, the speed deviation output (Fig. 4 a) changes from a value other than a predetermined value (hereinafter referred to as unlocked state) to within a predetermined value. (hereinafter referred to as the locked state), the phase deviation output is set to zero during the unlocked state and the phase 01 m is not performed, so the phase deviation output immediately after entering the locked state is not a normal control output, so the phase deviation output is output. There was a problem in that it itself became a disturbance element. SUMMARY OF THE INVENTION An object of the present invention is to provide a digital servo device that can solve the problems of the conventional example.

Means for Solving the Problem In order to solve this problem, the digital servo device of the present invention presets the deviation zero to the phase comparison counter when the speed deviation output is in the unlocked state, and presets the phase comparison counter to the phase latch circuit. This is an attempt to solve the above-mentioned problem by a configuration that latches the zero deviation of .

Effect: With this configuration, the phase deviation output is zero even immediately after changing from the unlocked state to the locked state, so the phase deviation output does not become a disturbance element and the phase comparison counter counts with the deviation being zero. Therefore, the operation is the same as phase control when outputting zero deviation, so the control is not disturbed.

Embodiment FIG. 1 is a functional block diagram of a digital servo device according to an embodiment of the present invention. In FIG. 1, 11 is a speed preset data generation circuit for generating a reference value of rotation speed, 12 is a speed comparison counter for counting rotation speed, 13 is a speed latch circuit for latching a counted value, and 14 is a speed comparison counter for counting rotation speed. is NL-, which determines the deviation value of the speed deviation output.
NH detection circuit; 15, a phase preset data generation circuit for generating a reference value of the rotational phase; 16, a phase comparison counter for counting the rotational phase; 17, a phase latch circuit for latching the counted value; 18, a phase comparison counter for counting the rotational phase; NF detection circuit for detecting count value NF of phase comparison counter, 1
9 is an AND circuit for passing the head switching signal when the speed deviation output is other than a predetermined value (unlocked state); 2o is the output of the AND circuit 19 or the NP detection circuit 1
It is constituted by an OR circuit for passing the outputs of 8.

The operation of the digital servo device of this embodiment configured as described above will be explained below. First, the speed preset data generation circuit 11 generates the reference value N by the FG signal.
Reset FS to speed comparison counter 12. A speed comparison counter 12 performs counting, and a speed latch circuit 13 latches the counted value at a position one cycle behind the preset position. The latched count value becomes the rotation speed deviation output. The count value of the phase comparison counter 16 is NF
When the phase preset data generation circuit 15 outputs the reference value N
PP is reset to phase comparison counter 16 and counting is performed. At the falling position of the head switching signal, the count value of the phase comparison counter 16 is latched by the phase latch circuit 17 to obtain a phase deviation. As shown in the timing chart of Fig. 12, when the rotational speed is in the unlocked state, a zero deviation value is preset in the phase comparison counter 16 at the falling position of the head switching signal (Fig. 2b). The zero deviation of the phase comparison counter 16 is latched into the phase latch circuit 17.

As described above, according to this embodiment, by presetting and latching the deviation to zero at the falling position of the head switching signal in the unlocked state, the phase comparison counter 16 can detect the deviation even immediately after changing from the unlocked state to the locked state. Since the count is performed in a zero state and the phase latch circuit 17 outputs a deviation output of zero, the state is the same as that under normal control, so that the phase deviation output can be prevented from becoming a disturbance.

Effects of the Invention The present invention presets the zero deviation in the phase comparison counter at the fall position of the head switching signal when in the unlocked state, and latches the zero deviation of the phase comparison counter into the phase latch circuit, thereby locking from the unlocked state. Since it is possible to prevent the phase deviation output from disturbing the servo even immediately after the state changes, a circuit with excellent servo characteristics can be realized.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of a digital servo device according to an embodiment of the present invention, FIG. 2 is an operation timing chart of the embodiment of FIG. 1, and FIG. 3 is a functional block diagram of a conventional digital servo device. 4 is an operation timing chart of FIG. 3. 1.11... Speed preset data generation circuit,
2.12... Speed comparison counter 3,13.
...Speed latch circuit, 4,14...NL
-NH detection circuit, 5.21...Digital speed discriminator, 6,16...Phase comparison counter 7
．． 15...Phase preset data generation circuit, 8
, 17... Phase-shifting triple circuit, 9.18...
...NF detection circuit, 10.22...Digital phase discriminator, 19...AND circuit, 20...
...OR circuit.

Claims (1)

[Claims] a digital speed discriminator that performs input signal frequency control;
When the deviation output of the digital speed discriminator is other than a predetermined value, a controlled signal is used to preset a zero deviation to a phase comparison counter that counts the phase deviation of the digital phase discriminator, and a phase latch circuit latches the zero deviation of the phase comparison counter. A digital servo device equipped with a digital phase discriminator that performs phase control to output a phase deviation.