JPH01286524A - Pll protection circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of the circuit by detecting the malfunction of a phase locked loop(PLL) and holding an applied voltage to a VCO. CONSTITUTION:A pulse given only at a slope of a trapezoidal wave is given to a D input of a D flip-flop 12. When the PLL is locked, since a sample pulse exists at the slope of the trapezoidal wave, an output of the D-FF 12 goes to a low level. If the PLL is unlocked or the sample pulse comes to an abnormal location, the output of the D-FF 12 changes from a low to a high level to hold the applied voltage of the VCO 6 for a prescribed time through a monostable multivibrator circuit 10. Thus, the abnormal operation of the PLL circuit is prevented in advance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a PLL that protects a phase-locked loop (PLL).
The present invention relates to a protection circuit (2), particularly to a PLL protection circuit for clock generation when digital signal processing is performed on a VTR laser disc reproduction signal.

[Conventional technology]

An example of a conventional PLL protection circuit is shown in FIG.

This PLL protection circuit includes a trapezoidal wave generating circuit 1, a switch 3 connected to this circuit, a capacitor C1 that holds the switch output, an amplifier 4, a loop filter 5, a switch 11, a capacitor c2, vCo6, and a sampling pulse. It is composed of a sampling pulse generator 2, a comparator 7.8 connected to a capacitor c1, an OR circuit 9 connected to these comparators 7.8, and a monostable multivibrator (hereinafter referred to as monomulti) circuit 10.

In this circuit, the oscillation output of vCo6 is frequency-divided by a set frequency division value and inputted to the trapezoidal wave generation circuit 1 from the input terminal 22, while the reference signal from the input terminal 21 is generated by the sample pulse generator 2 with a pulse width converted into a constant sampling pulse. During this sampling, switch 3 is closed and capacitor C1 is charged. The output voltage is amplifier 4,
It is applied to vCo6 through loop filter 5. At this time, switch 11 is closed. A reference voltage VH is applied to the negative phase terminal of the comparator 7, and the positive phase terminal is connected to the capacitor C1. On the other hand, a reference voltage VL smaller than the voltage vH is applied to the positive phase terminal of the comparator 8, and the negative phase input terminal is connected to the capacitor C1.

In this case, OR circuit 9 rises from low (L) to high (H) only when the voltage of capacitor C1 becomes greater than voltage VH or smaller than voltage Vc. A pulse output for a certain period of time from the rise of this OR circuit 9 is taken out from the monomulti circuit 10, and by opening the switch 11, the error voltage of the PLL is held in the capacitor C2, and the PLL system is temporarily disconnected. Since there is a delay time for the abnormal voltage detected in to pass through the amplifier 4 and the loop filter 5, the switch 11 opens before the abnormal voltage is transmitted to the loop filter 5, and the system is not disturbed.
Further, when the mono multi-circuit 10 operates once, there is a fixed time interval before the next operation, so that no hold is applied at all times.

[Problem to be solved by the invention]

The conventional PLL protection circuit described above is not suitable for LSI integration because it is configured using an analog circuit, and also has the disadvantage that the circuit may malfunction due to noise on the hold capacitor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL protection circuit that eliminates such drawbacks and prevents malfunctions of the circuit using a simple circuit.

[Means to solve the problem]

The configuration of the present invention includes a voltage controlled oscillator that oscillates using a control voltage, and a VCo which frequency-divides the output of this voltage controlled oscillator.
A trapezoidal wave generator that inputs a frequency divided signal (or reference signal) and outputs a trapezoidal wave, and the reference signal (or ■Co signal)
a first holding circuit that samples the slope part of the trapezoidal wave with the sampling pulse, holds the voltage, and outputs it as an error voltage; In a PLL protection circuit including an input loop filter and a second holding circuit that outputs the output of the loop filter as the control voltage and holds this output in the event of an abnormality, the pulse generated at the slope of the trapezoidal wave and the It is characterized in that the phase state with the sampling pulse is detected, and if the sampling is performed in a section other than the tilting time, it is determined that there is an abnormality and the control voltage is held.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The PLL protection circuit of this embodiment includes a trapezoidal wave generating circuit 1, a switch 3 connected to the trapezoidal wave generating circuit 1, and a capacitor C1 that holds the switch output. Amplifier 4 and loop filter 5
, switch 11, capacitor C2, vCo6,
It is composed of a sampling pulse generator 2 and a D-type flip-flop (D-FF) 12 which uses the output of the sampling pulse generator 2 as a clock. A reference signal is input from the input terminal 21 to the input of the sampling generator 2, and vCo is input from the input terminal 22 to the input of the trapezoidal wave generation circuit 1.
A frequency-divided signal is input.

As shown in FIG. 2, a pulse that is output only when the trapezoidal wave slopes is input to the D input of the D-type flip-flop 12. When the PLL is locked, the sample pulse is on the slope of the trapezoidal wave, so the output of the D-FF 12 is at a low level. In addition, when the PLL is disconnected or the sample pulse comes to an abnormal position, the output of the D-FF 12 changes from low level to high level, passes through the monomulti circuit 10, and holds the voltage applied to the VCO 6 for a certain period of time. This prevents abnormal operation of the PLL circuit.

FIG. 3 is a block diagram of a second embodiment of the present invention. In the first embodiment, the sample pulse was generated by the reference signal from the input terminal 21, but in this embodiment, the V
A sample pulse is generated using the CO frequency-divided signal, and a trapezoidal wave is created using the reference signal. It will be clear that this case also operates in the same way as the first embodiment.

〔Effect of the invention〕

As explained above, the present invention detects abnormal operation of the PLL and holds the voltage applied to the VCO, which prevents disturbance of the PLL system due to noise, etc., and is configured with a simple digital circuit. Therefore, there is an effect that no adjustment is required and it is easy to implement into an LSI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of FIG. 1, and FIG. 3 is a block diagram of the second embodiment of the present invention.
FIG. 4 is a block diagram of an example of a conventional PLLgAN circuit. DESCRIPTION OF SYMBOLS 1... Trapezoidal wave generation circuit, 2... Sample pulse generator, 3, 11... Switch, 4... Amplifier, 5...
・Loop filter, 6... vCo, 7.8... Comparator, 9... OR circuit, 10... Switch, 1
2...D-flip-flop, C1, C2... capacitor.

Claims (1)

[Claims] A voltage controlled oscillator that oscillates using a control voltage, a trapezoidal wave generator that outputs a trapezoidal wave by inputting a VCO frequency divided signal (or reference signal) obtained by dividing the output of this voltage controlled oscillator, and the reference signal (or a first holding circuit that samples the slope part of the trapezoidal wave with the sampling pulse, holds the voltage, and outputs it as an error voltage; In a PLL protection circuit that includes a loop filter that inputs an error voltage and a second holding circuit that outputs the output of this loop filter as the control voltage and holds this output in the event of an abnormality, the error occurs when the trapezoidal wave slopes. A PLL protection circuit characterized in that it detects a phase state of a pulse and the sampling pulse, and when the sampling is performed in a section other than the slope, it is determined to be abnormal and the control voltage is held.