JP2006148623A - Method and device for reproducing horizontal synchronization - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a horizontal synchronization reproducing method and device capable of obtaining a stable clock by reducing the influence of noise included in a video signal. <P>SOLUTION: A first sample and hold circuit 15 and a second sample and hold circuit 16 cascaded by first and second pulse generation circuits 12 and 13 for generating first and second sampling pulses, respectively by an output of a synchronization separation circuit 11 to which an analog video input is inputted are provided. The second sample and hold circuit 16 resamples an output of the first sample and hold circuit 15 to thereby reduce the influence of noise of an analog video input. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a horizontal synchronized reproduction method and apparatus, and more particularly to an improved horizontal synchronized reproduction method and apparatus used in a converter for converting an analog video signal into a digital video signal.

  In the equipment of a television (TV) broadcasting station, in order to facilitate connection between video devices, a digital video signal is converted into a serial signal, and the devices are connected by a single coaxial line (standard name: SMPTE259M). / 292M). Therefore, when an analog video signal is input, conversion processing from an analog to a serial digital signal is required.

  This conversion process requires a horizontal synchronous reproduction circuit and a parallel / serial conversion circuit. In the parallel-serial conversion, for example, a 143 Mbps serial signal is generated from a 10-bit parallel signal obtained by sampling at 14.3 MHz. At this time, it is necessary to generate a 143 MHz phase-synchronized clock that is ten times greater than the input 14.3 MHz clock. The jitter of the 143 MHz clock needs to be 20% (1.4 ns) or less of the clock period in the SMPTE259M standard.

  This 10 times clock is generally generated using a PLL (Phase-Locked Loop) circuit. A general horizontal synchronous reproduction circuit using a PLL circuit is disclosed in several technical documents (for example, refer to Patent Document 1).

JP-A-11-41487 (FIG. 1, paragraph numbers [0010] to [0011])

  FIG. 3 is a block diagram showing an example of a horizontal synchronous reproduction circuit using a conventional PLL circuit. The PLL circuit is an H-PLL that applies a PLL with a horizontal synchronization signal. The horizontal synchronous reproduction circuit 30 includes a synchronous separation circuit 31, an integration circuit 32, a pulse generation circuit 33, a trapezoidal wave generation circuit 34, a sample hold circuit 35, a loop filter 37, a VCO 38, and a synchronous reproduction circuit 39. An input terminal IN is connected to the sync separation circuit 31. The output of the VCO 38 is connected to the synchronous reproduction circuit 39 and to the first output terminal OUT1. The output of the synchronous reproduction circuit 39 is input to the trapezoidal wave generation circuit 34 and is connected to the second output terminal OUT2.

  From the analog video signal input to the input terminal IN, a synchronization signal is extracted by the synchronization separation circuit 31. A clock is generated from the extracted synchronization signal using an H-PLL. Therefore, when a high quality analog video signal is input, the jitter of the generated clock is reduced. However, when the video signal is affected by noise, such as a video signal transmitted over a long distance, there is a problem that the quality of the extracted synchronization signal is poor and the resulting jitter of the clock increases. Arise. As a countermeasure against this noise, conventionally, the output of the sync separation circuit 31 is input to the integration circuit 32 to reduce pulse-like fine noise mixed in the sync separation output. For this purpose, in the case of the NTSC signal, it is necessary to smooth the waveform in a period of 1 μs, for example.

  However, there has been a problem that jitter is increased in the pulse generation circuit 33 by smoothing the waveform as described above. In this conventional horizontal reproduction circuit 30, when the integration circuit 32 is inserted for noise reduction, the phase of the output signal of the pulse generation circuit 33 becomes unstable and the jitter of the finally generated clock is reduced. It was difficult. In addition, the processing by such an analog circuit is easily affected by temperature drift, the phase becomes unstable, and causes deterioration of jitter. The output of the pulse generation circuit 33 is sampled and held by the sample and hold circuit 35, smoothed by the loop filter 37, and the frequency of a VCO (voltage controlled oscillator) 38 is changed by the output voltage. This is input to the synchronous reproduction circuit 39, the control signal of the synchronous reproduction circuit 39 is input to the trapezoidal wave generation circuit 34, and the output is input to the sample hold circuit 35. This closed loop constitutes one phase comparison unit. From the synchronous reproduction circuit 39, a clock is output to the first output terminal OUT1, and a horizontal synchronization pulse is output to the second output terminal OUT2.

  The present invention has been made in view of the above-described problems of the prior art, and a main object of the present invention is to provide a horizontal synchronous reproduction method and apparatus that overcomes or reduces such problems.

  In order to solve the above-described problems, the horizontal synchronized reproduction method and apparatus of the present invention employs the following characteristic configuration.

(1) In a horizontal synchronization reproduction method for generating a clock signal having a frequency corresponding to a plurality of times of a horizontal synchronization signal separated from an analog video input by a horizontal synchronization separation circuit using a PLL (Phase Locked Loop) circuit,
A horizontal synchronized reproduction method in which the trapezoidal wave of the PLL circuit is sampled and held by a first sampling pulse, and the sampled and held signal is resampled by a second sampling pulse and input to the loop filter of the PLL circuit. .

  (2) The horizontal synchronized reproduction method according to (1), wherein the second sampling pulse is delayed by a predetermined time with respect to the first sampling pulse, and a stable portion of the sampled and held signal is resampled.

  (3) The horizontal synchronous reproduction method according to (1) or (2) above, wherein the first sampling pulse is obtained by slicing the analog video input at a predetermined slice level.

(4) including a horizontal sync separation circuit to which an analog video input is input, a sampling circuit for sampling with a sampling pulse generated by the output of the horizontal sync separation circuit, and a PLL (Phase Locked Loop) circuit operating with the output of the sampling circuit In a horizontal synchronization reproduction device that generates a clock signal having a frequency that is a multiple of the horizontal synchronization signal,
A horizontal synchronized reproduction apparatus comprising a second sampling circuit for resampling the output of the sampling circuit to obtain a stable output signal.

  (5) The horizontal synchronous reproduction device according to (4), wherein the resampling is performed by a second sampling pulse delayed by a predetermined time from the sampling pulse of the sampling circuit.

  (6) The horizontal synchronous reproduction device according to (5), wherein the second sampling pulse is a pulse in which noise is reduced by an integration circuit.

  (7) The horizontal synchronous reproduction device according to (5), wherein the second sampling pulse is generated using an up / down counter.

  (8) A synchronization separation circuit to which an analog video input is input, a first and a second pulse generation circuit for outputting first and second sampling pulses respectively by an output of the synchronization separation circuit, and the first and second pulse generation circuits that are connected in cascade. First and second sample and hold circuits sampled by the second sampling pulse, and a loop filter, VCO, and synchronous recovery circuit cascaded between the output of the second sample and hold circuit and the input of the first sample and hold circuit And a PLL circuit including a trapezoidal wave generating circuit, and obtaining an output signal synchronized with the horizontal synchronizing signal of the analog video input from the synchronous reproducing circuit.

  According to the horizontal synchronized reproduction method and apparatus of the present invention, the following remarkable effects in practical use can be obtained. That is, two sample hold circuits are provided in the phase comparison circuit, the output of one sample hold circuit is resampled by the other sample hold circuit, and the sampling timing is controlled to avoid the influence of noise in the video signal. Improved horizontal synchronization (ie, greatly reduced noise effects) is possible.

  Hereinafter, the configuration and operation of a preferred embodiment of the horizontal synchronized playback method and apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

  First, FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a horizontal synchronized playback apparatus according to the present invention. The horizontal synchronization reproduction apparatus 10 includes a synchronization separation circuit 11, a first pulse generation circuit 12, a second pulse generation circuit 13, a trapezoidal wave generation circuit 14, a first sample hold circuit 15, a second sample hold circuit 16, and a loop filter 17. , A VCO 18 and a synchronous reproduction circuit 19.

  Here, an analog video signal is input from the input terminal IN to the synchronization separation circuit 11, and its output is input to the first pulse generator 12 and the second pulse generator 13. The outputs of the first pulse generation circuit 12 and the second pulse generation circuit 13 are input to the first sample hold circuit 15 and the second sample hold circuit 16, respectively. The output of the trapezoidal wave generation circuit 14 is input to the first sample hold circuit 15, and the output is input to the second sample hold circuit 16. The output of the second sample and hold circuit 16 is input to the VCO 18 via the loop filter 17. The output of the VCO 18 is input to the synchronous reproduction circuit 19 and is connected to the first output terminal OUT1. The output of the synchronous reproduction circuit 19 is input to the trapezoidal wave generation circuit 14 and is connected to the second output terminal OUT2.

  In addition, the first pulse generation circuit 12, the second pulse generation circuit 13, the trapezoidal wave generation circuit 14, the first sample hold circuit 15, the second sample hold circuit 16, the loop filter 17, the VCO 18, and the synchronous reproduction circuit 19 have one A phase comparison unit is configured.

  Next, an overview of the overall operation of the horizontal synchronized playback apparatus 10 shown in FIG. 1 will be described. The analog video signal input to the input terminal IN is sent to the sync separation circuit 11. The output of the synchronous separation circuit 11 is sent to the first pulse generation circuit 12 and the second pulse generation circuit 13. Here, the output of the first pulse generation circuit 12 is sent to the first sample hold circuit 15, and the output of the second pulse generation circuit 13 is sent to the second sample hold circuit 16. The second pulse generation circuit 13 includes an integration circuit and a pulse generation circuit for reducing noise generated in the video.

  The first pulse generation circuit 12, the second pulse generation circuit 13, the trapezoidal wave generation circuit 14, the first sample hold circuit 15, the second sample hold circuit 16, the loop filter 17, the VCO 18 and the synchronous reproduction circuit 19 form a closed loop. Yes. A clock is output from the synchronous reproduction circuit 19 to the first output terminal OUT1, and a horizontal synchronization pulse is output to the second output terminal OUT2. Here, the trapezoidal wave generation circuit 14 may generate a trapezoidal wave using a D / A converter.

  Next, the operation of the horizontal synchronized playback apparatus 10 shown in FIG. 1 will be described in detail with reference to the operation waveform diagram of FIG. In FIG. 2, (a) is an analog video signal input from the input terminal IN. (B) is an output signal from the synchronization separation circuit 11. (C) is a signal generated inside the second pulse generation circuit 13. (D) is a first sampling pulse generated from the first pulse generation circuit 12. (E) is a second sampling pulse output from the second pulse generation circuit 13. (F) is a trapezoidal signal output from the trapezoidal wave generation circuit 14. (G) is an output signal from the first sample and hold circuit 15. (H) is an output signal from the second sample and hold circuit 16. (I) and (j) are clocks output from the first output terminal OUT1. The former is a clock output from the conventional horizontal synchronized reproduction circuit 30, and the latter is output from the horizontal synchronized reproduction apparatus 10 of the present invention. Clock.

  First, the sync signal portion of the analog video input (see FIG. 2A) input to the input terminal IN is sliced at a predetermined slice level as shown in the figure to obtain a sync separation output (see FIG. 2B). . Here, when the analog video input includes a large noise N as shown in FIG. 2A, this noise N is also sliced, and a pulse other than the horizontal synchronizing signal is generated in the sync separation output (b). .

  Here, the first sampling pulse (d) is an output signal of the first pulse generation circuit 12, and the second sampling pulse (e) is an output signal of the second pulse generation circuit 13. Since the second pulse generation circuit 13 has an integration circuit for reducing noise generated in the video input signal, the second pulse generation circuit 13 generates a signal as shown in FIG. Next, the trapezoidal wave (f) is sampled by the first sampling pulse (d) corresponding to the fall of the synchronous separation output (b), and the output of the first sample hold circuit 15, that is, the first sampling hold output (g). Is obtained. Further, by resampling the first sampling hold output (g) with the second sampling pulse (e), the second sampling hold circuit 16 outputs the second sampling hold output (h), that is, a stable DC output signal. Thus, it is possible to stably obtain a clock signal from the VCO 18 to the first output terminal OUT1.

  Note that the first pulse generation circuit 12 of FIG. 1 can be realized by, for example, a one-shot multivibrator or a differentiation circuit. The second pulse generation circuit 13 outputs a second sampling pulse (e) in which noise is reduced by an integration circuit. The second pulse generation circuit 13 can be realized by, for example, an up / down counter. The output pulse (e) of the second pulse generation circuit 13 is a pulse having jitter, but since a stable portion of the first sample hold output (g) is resampled, there is no need to worry about the phase. Here, the second pulse generation circuit 13 and the synchronous reproduction circuit 19 can be configured by a known digital circuit.

  As described above, by having the second pulse generation circuit 13 and the second sample hold circuit 16, it is possible to prevent fluctuations caused by the analog circuit as much as possible, and a stable clock even if the analog video input includes noise N. Can be realized.

  The configuration and operation of the preferred embodiment of the horizontal synchronized playback method and apparatus according to the present invention have been described in detail above. However, it should be noted that such examples are merely illustrative of the invention and do not limit the invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention. For example, a digital phase comparison means can be provided to speed up the phase pull-in response. Further, the present invention can be applied not only to the NTSC system but also to the PAL system.

It is a block diagram which shows the structure of the suitable Example of the horizontal synchronized reproducing | regenerating apparatus by this invention. It is an example of the operation | movement waveform diagram which shows operation | movement of each part of the horizontal synchronous reproducing | regenerating apparatus shown in FIG. It is a block diagram of the horizontal synchronous reproduction circuit by a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Horizontal synchronous reproduction apparatus 11 Synchronization separation circuit 12 1st pulse generation circuit 13 2nd pulse generation circuit 14 Trapezoid wave generation circuit 15 1st sample hold circuit 16 2nd sample hold circuit 17 Loop filter 18 VCO
19 Synchronous playback circuit

Claims (8)

In a horizontal synchronization reproduction method for generating a clock signal having a frequency corresponding to a plurality of times of a horizontal synchronization signal separated from an analog video input by a horizontal synchronization separation circuit using a PLL (Phase Locked Loop) circuit,
The trapezoidal wave of the PLL circuit is sampled and held with a first sampling pulse, and the sampled and held signal is resampled with a second sampling pulse and input to the loop filter of the PLL circuit. Horizontal synchronized playback method.   2. The horizontal synchronous reproduction method according to claim 1, wherein the second sampling pulse is delayed by a predetermined time with respect to the first sampling pulse, and a stable portion of the sampled and held signal is resampled. .   The horizontal synchronized reproduction method according to claim 1 or 2, wherein the first sampling pulse is obtained by slicing the analog video input at a predetermined slice level. A horizontal sync separation circuit to which an analog video input is input, a sampling circuit for sampling with a sampling pulse generated by an output of the horizontal sync separation circuit, and a PLL (Phase Locked Loop) circuit that operates with the output of the sampling circuit, In a horizontal synchronous reproduction device that generates a clock signal having a frequency that is a multiple of the synchronization signal,
A horizontal synchronized reproduction apparatus comprising a second sampling circuit for resampling the output of the sampling circuit to obtain a stable output signal.   5. The horizontal synchronous reproduction apparatus according to claim 4, wherein the resampling is performed by a second sampling pulse delayed by a predetermined time from a sampling pulse of the sampling circuit.   6. The horizontal synchronized reproduction apparatus according to claim 5, wherein the second sampling pulse is a pulse in which noise is reduced by an integration circuit.   6. The apparatus according to claim 5, wherein the second sampling pulse is generated using an up / down counter.   A synchronization separation circuit to which an analog video input is input, first and second pulse generation circuits that output first and second sampling pulses by the output of the synchronization separation circuit, respectively, and the first and second cascaded connections, respectively. First and second sample and hold circuits sampled by a sampling pulse, and a loop filter, a VCO, a synchronous reproduction circuit, and a trapezoidal wave cascaded between the output of the second sample and hold circuit and the input of the first sample and hold circuit And a PLL circuit including a generation circuit, wherein an output signal synchronized with the horizontal synchronizing signal of the analog video input is obtained from the synchronous reproducing circuit.

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