JPH06245219A - Burst signal processing circuit - Google Patents

Abstract

PURPOSE:To attain a stable burst clock operation by continuously implementing phase comparison with a burst gate pulse having a 2H period as a result of 1/2 frequency division for a vertical blanking period where no burst signal is in existence. CONSTITUTION:A bust gate pulse circuit 7 using a horizontal synchronizing separator circuit 5 and a 1/2 frequency divider circuit 6 generates a burnt gate pulse, a vertical synchronizing separator circuit 3 and a vertical blanking circuit 4 generate a vertical blanking pulse, a BPF 8 and a comparator 9 generate a burst square wave and it is fed to a latch circuit 10 generating a latch pulse, an output being the burst gate pulse or the latch pulse selected by a switching circuit 11, the switching output signal and a 1/1820 frequency division signal of a PLL circuit are given to a phase comparator circuit 12, in which they are compared for the phase and its output is given via an LPF 14 to a VCO 15, from which a reference clock is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst signal processing circuit in the field of color signal processing of reproduced video signals, and more particularly to a reference clock for reproducing a video signal having an intermittent period of a color burst signal such as a vertical blanking period. The present invention relates to a burst signal processing circuit suitable for generation.

[0002]

2. Description of the Related Art Conventionally, a burst signal processing circuit for generating a reproduction reference clock for performing color signal processing at the time of reproducing a video signal has been provided with the block diagram shown in FIG. In FIG. 7, reference numeral 1 denotes a composite video signal input terminal, and the composite video signal applied to this input terminal 1 is a sync separation circuit 2 and a bandpass filter 8 (hereinafter referred to as BPF 8) for extracting a color burst signal.
Is supplied to.

Reference numeral 5 is a horizontal sync separation circuit for separating a horizontal sync signal from the composite sync signal separated by the sync separation circuit 2. This horizontal sync signal is a burst gate pulse circuit.
Supplied to 70. On the other hand, the color burst signal extracted by the BPF 8 is supplied to the comparator 9, and the center level of the color burst signal is compared with the direct current zero level (0V _DC ) to generate a color burst square wave.

A burst 71 is supplied with the color burst gate pulse output from the burst gate pulse circuit 7 and the color burst square wave, and extracts a burst signal in which the phase of the color burst square wave matches the color burst gate pulse. It is a signal extraction circuit.

Reference numeral 12 is a phase comparison circuit which constitutes a PLL circuit, and a comparison error output signal of the phase comparison circuit 12 passes through a noise removal loop filter of a low pass filter 14 (hereinafter referred to as LPF14) and a voltage controlled oscillation 15 (hereinafter referred to as VCO15)
The output of the VCO 15 is fed back to the phase comparison circuit 12 via the 1/4 frequency divider circuit 72. on the other hand,
The output signal of VCO15 is supplied to output terminal 17
A reference clock for color signal reproduction is output.

Further, the vertical blanking period in which the color burst signal of the composite video signal is intermittent is
The phase comparison circuit 12 of the LL circuit maintains the hold state by the EN (Enable) pulse input for sample hold supplied to the phase comparison circuit 12. That is, EN pulse is at high level (color burst gate pulse of color burst signal
In the high level period), the phase comparison circuit 12 is set to the active state and performs the phase comparison processing of the burst signal,
When the EN pulse is at the low level, the phase comparison circuit 12 enters the hold state and holds the droop characteristic of the output of the phase comparison circuit 12 in a stable state.

In the burst signal processing circuit thus constructed, the output of the VCO 15 of the PLL circuit is phased by the phase comparison circuit 12 by the color burst square wave synchronized with the color burst gate pulse obtained from the horizontal synchronizing signal of the composite video signal. The reference clock synchronized with the burst signal of the composite video signal can be obtained by comparison processing, and the reproduction of the color signal at the time of video reproduction can be reproduced by the reference clock.

As another conventional burst signal processing circuit, for example, Japanese Patent Laid-Open No. 61-212188 is disclosed. This publication is configured such that a burst signal is digitally converted to generate a burst continuous wave using a circulating memory circuit and is supplied to a high speed PLL circuit (utilization circuit) to obtain a reference clock of a reproduced video signal. .

[0009]

The conventional burst signal processing circuit (FIG. 7) described above has a vertical blanking period in which the color burst signal of the composite video signal does not exist as a continuous wave. In the vertical blanking period, the phase comparison circuit 12 must be kept in the hold state and the droop characteristic of the output of the phase comparison circuit 12 must be kept in a stable state.

However, during the intermittent period of the burst signal in the vertical blanking period, due to the voltage change of the DC voltage component held in the color burst gate pulse period,
There is a drawback in that the phase comparison circuit 12 cannot maintain a stable locked state.

That is, when the phase comparison circuit 12 of the PLL circuit holds the phase comparison in an unstable state, the oscillation frequency of the VCO 15 becomes unstable and the output reference clock frequency also becomes unstable. There was a drawback that it would end up.

Further, since the phase comparison circuit 12 of the PLL circuit is set to the hold state, there is a drawback that the response of the phase comparison operation of the phase comparison circuit 12 becomes slow.

Further, in the above-mentioned "Japanese Patent Laid-Open No. 61-212188", a burst signal is digitally converted by an A / D conversion circuit, and an intermittent period of the burst signal is compensated by a circulating memory circuit to generate a burst continuous wave. , The D / A converter circuit has a large-scale circuit configuration that converts it to an analog signal.

That is, an A / D for performing the above digital conversion processing
Also, a PLL circuit for generating the clock signal of the D / A conversion circuit and the circulating memory circuit is required, and the burst signal processing depends on the accuracy of the clock signal of the PLL circuit.

As described above, there is a drawback that a PLL circuit for generating a clock signal such as an A / D and D / A conversion circuit and a high-speed PLL circuit for generating a reference clock signal of a reproduced video signal are required. It was

The present invention has been made in view of the above points, and its object is to solve the drawbacks of the conventional example and to provide a burst gate pulse of 2H period divided by 1/2 in the vertical blanking period. An object of the present invention is to provide a burst signal processing circuit which performs a stable burst lock operation by continuously performing the phase comparison operation of the phase comparison circuit 12.

[0017]

SUMMARY OF THE INVENTION A burst signal processing circuit of the present invention is a horizontal signal processing circuit for extracting a horizontal synchronizing signal from a composite video signal to generate a color burst gate pulse at the same timing as a color burst signal,
A vertical signal processing circuit that extracts a vertical synchronization signal from a composite video signal to generate a vertical blanking pulse,
A latch circuit for latching the color burst gate pulse with the color burst square wave, and a latch signal for the latch circuit, the color burst signal processing circuit for extracting the color burst signal from the composite video signal to generate a color burst square wave And a switching circuit for switching the color burst gate pulse with the vertical blanking pulse and a switching circuit for supplying the switching output signal to a PLL circuit to generate a reference clock.

Further, the horizontal signal processing circuit separates the horizontal synchronizing signal and divides it by 1/2, and a 1/2 dividing circuit, and the color synchronizing gate pulse is generated by the 1/2 dividing horizontal synchronizing signal. The color burst gate pulse circuit may be provided.

Further, the output signal of the voltage controlled oscillator of the PLL circuit may be a 4f _sc reference clock.

[0020]

According to the present invention, the color burst signal is extracted from the composite video signal to generate the color burst square wave, and the burst gate pulse selected from the horizontal synchronizing signal is latched by the color burst square wave, and the latch pulse is generated. The burst gate pulse and the burst gate pulse are selected by the switching circuit and supplied to the phase comparison circuit of the PLL circuit.

The switching selection of the switching circuit is controlled by the vertical blanking pulse generated by the vertical synchronizing signal of the vertical processing circuit. That is, during the video signal period in which the color burst signal of the composite video signal is present, the latch pulse synchronized with the color burst signal is switching-selected and supplied to the phase comparison circuit, and the latch pulse and the V
The phase is compared with the 1 / N divided signal from CO.

In the vertical blanking period in which the color burst signal of the composite video signal is not present, the burst gate pulse is selected by the switching circuit and supplied to the phase comparator circuit, and the burst gate pulse is divided into 1/2 and the burst gate pulse has a period of 2H. And the 1 / N frequency-divided signal from the VCO of the PLL circuit are continuously phase-compared and the output error signal is passed through the LPF to the VCO.
Can be controlled.

The division ratio of the 1 / N divider circuit of the PLL circuit is
The frequency is set to 1/1820 and the VCO output reference clock frequency of the line PLL circuit is f = 4f _SC (f _SC is the burst signal frequency) before output. In this way, even in the vertical blanking period of the composite video signal, the phase comparison can be performed by the burst gate pulse of 2H period divided by 1/2, so that the phase comparison operation of the phase comparison circuit is stable and the continuous input is performed. It is possible to perform a phase comparison operation with a quick response by a signal.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a burst signal processing circuit according to the present invention will be described with reference to FIGS. The same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted. Figure 1
2 is a block diagram, FIG. 2 and FIGS. 4 to 6 are waveform diagrams showing timings of operation waveforms of respective parts, and FIG. 3 is a circuit diagram showing one embodiment of a comparator.

In FIG. 1, 3 and 4 are vertical signal processing circuits, and 3 is a vertical sync separation circuit. The vertical sync separation circuit 3 separates the vertical sync signal from the composite sync signal extracted by the sync separation circuit 2, and the vertical sync signal is supplied to the vertical blanking circuit 4 to generate a vertical blanking pulse.

Reference numerals 5, 6 and 7 are horizontal signal processing circuits, and 5 is a horizontal sync separation circuit. The horizontal sync separation circuit 5 separates the horizontal sync signal from the composite sync signal extracted by the sync separation circuit 2, and the 1/2 frequency divider circuit 6 generates a pulse of 1 / 2H period. Reference numeral 7 is a burst gate pulse circuit, and this burst gate pulse circuit 7 generates a gate pulse at the same timing as the color burst signal by the frequency dividing pulse of 2H period obtained by dividing the 1/2 frequency dividing circuit 6 by 1/2. .

Reference numerals 8, 9 and 10 denote color burst signal processing circuits, which are used to convert a color signal (f = 3.58 MHz) from an input composite video signal by a BPF 8 having a filter center frequency f _C = 3.58 MHz.
z) Only the component is extracted, the center level of the color signal and the DC zero voltage (0V _DC ) level are compared by the comparator 9 and converted into a color signal square wave, and the latch circuit
Supply to 10.

Reference numeral 11 denotes a switching circuit which is switched and controlled by the output signal of the vertical blanking circuit 4, and this switching circuit 11 is the burst gate pulse circuit 7 described above.
And the output of the latch circuit 10 are switched.

Reference numerals 12 to 16 are PLL circuits, and 12 is a phase comparison circuit for phase-comparing the output of the switching circuit 11 and the signal obtained by dividing the output of the VCO 15. Reference numeral 13 is an EN (Enable) pulse input terminal for sample and hold of the phase comparison circuit 12, and the output of the phase comparison circuit 12 controls the voltage of the VCO 15 via the LPF 14. Reference numeral 16 is a frequency divider circuit for dividing the VCO 15 output by 1/1820, and the output of the 1/1820 frequency divider circuit 16 is supplied to the phase comparison circuit 12. Reference numeral 17 is the output terminal of the PLL circuit to which the output signal of VCO15 is supplied.

The burst signal processing circuit thus constructed takes out the color burst signal from the input composite video signal, outputs the reference clock of the color signal synchronized with the color burst signal at the same timing, and reproduces the video signal processing circuit. It can be operated as a reference clock for color signal reproduction.

The operation of the burst signal processing circuit which is generated from the composite video signal input with the reference clock for color signal reproduction will be described with reference to the waveform diagrams and circuit diagrams of FIGS.

The composite video signal applied to the input terminal 1 is shown, for example, by the waveform (A) in FIG. 2, and in the figure, 20 is a video signal portion, which is a Y level in a state where there is no actual video signal. 21 is a horizontal synchronizing signal, and 22 is a color burst signal. This composite video signal is supplied to the sync separation circuit 2 to extract the composite sync signal and is supplied to the vertical and horizontal sync separation circuits 3 and 5.

Only the horizontal sync signal 21 is separated by the horizontal sync separation circuit 5 of the horizontal signal processing circuits 5, 6, 7 and the waveform (B) in FIG.
The horizontal synchronizing signal 21 shown in can be taken out. The horizontal synchronizing signal 21 is supplied to the 1/2 frequency dividing circuit 6 and is halved by 2H which is triggered at the rising edge of the horizontal synchronizing signal 21.
A 1/2 frequency-divided output pulse 23 (waveform (C) in FIG. 2) is generated.

The 1/2 frequency-divided output pulse 23 is supplied to the burst gate pulse circuit 7, and the 1/2 frequency-divided output pulse 23 synchronized with the horizontal synchronizing signal 21 is converted into a color burst signal 22 having a predetermined time. 2 divided by 1/2 at the same timing
Burst gate pulse 24 of H period, that is, waveform of FIG.
Generate (D).

On the other hand, the input composite video signal 20 is
Supplied to BPF8. The center frequency of the BPF 8 is set to the frequency of the color burst signal 22: f = 3.58 MHz, and only the color burst signal 22 is extracted and sent to the comparator 9.

This comparator 9 is a square wave conversion comparator, and is composed of an operational amplifier 31 having a supply voltage of 5V _DC as shown in the circuit diagram of FIG.
The color burst signal 22 is added to the input terminal 30 of and the output terminal 32 is obtained by comparing the center level of the color burst signal 22 and the zero level of DC voltage = 0V _DC
Can generate a color burst square wave 25 of waveform (F) in FIG.

By supplying the color burst square wave 25 and the burst gate pulse 24 to the latch circuit 10, the burst gate pulse 24 is generated at the rising portion of the color burst square wave 25 as shown in the waveform diagram of FIG. ,
For example, a latch circuit formed by a flip-flop circuit or the like
The latch pulse 40 shown in the waveform diagram (G) of FIG. 4 can be obtained by latching at 10. The falling timing of the latch pulse 40 has a pulse waveform in phase with the rising timing of the color burst square wave 25.

The latch pulse 40 is the horizontal synchronizing signal 2
The color burst signal is output once to H and latches the color burst signal, but generally, since the color burst signal itself is phase-inverted every 1H, as described above, by latching at 2H once, In-phase color burst signals can always be obtained.

The latch pulse 40 is a switching circuit.
On the other hand, the burst gate pulse 24 of the burst gate pulse circuit 7 is supplied to the switching circuit 11, and the latch pulse 40 and the burst gate pulse 24 supplied to the switching circuit 11 are selected to Step
Supply to the PLL circuit.

The switching selection of the switching circuit 11 is switched by the vertical blanking signal from the vertical blanking circuit 4. As the vertical blanking signal, the vertical synchronizing signal separated by the vertical synchronizing separating circuit 3 from the composite video signal 20 is supplied to the vertical blanking circuit 4, and there is no color burst signal before and after the vertical synchronizing signal which is determined in advance. Can be extracted to generate a vertical blanking pulse.

That is, during the video signal period in which the color burst signal 22 of the composite video signal 20 is present, it is latched by the color burst square wave 25, and the latch pulse 40 phase-synchronized with the color burst signal 22 is selected by the switching circuit 11. And is supplied to the phase comparison circuit 12 of the PLL circuit. On the other hand, during the vertical blanking period in which the color burst signal 22 does not exist, the burst gate pulse 24 of the burst gate pulse circuit 7 is selected by the switching circuit 11 in the 2H cycle divided by 1/2 and the phase comparison of the PLL circuit is performed. It is supplied to the circuit 12 for phase comparison.

As is well known, the PLL circuit is a phase comparison circuit 12
The error output of the phase comparison of VCO15 controls VCO15 via LPF14, and the output of this VCO15 is fed back to the phase comparison circuit 12 via the frequency division circuit 16 with the division ratio N = 1820,
Output clock signal from CO15.

The phase comparison timing of the phase comparison circuit 12 in the video signal period in which the color burst signal 22 exists is shown in FIG.
Shown in. In FIG. 5, the latch pulse 40 of the waveform (G) synchronized with the rising phase of the color burst square wave 25 of the color burst signal 22 of the composite video signal of the waveform (A) described above is supplied to the phase comparison circuit 12, while Divided signal obtained by dividing the output clock signal of VCO15 by the 1/1820 divider circuit 16.
50 (waveform (H) in FIG. 5) is supplied to the phase comparison circuit 12. That is, the phase comparison timing of the phase comparison circuit 12 is, as shown in the figure, the trailing edge of the latch pulse 40 and the 1/1820 frequency division signal.
Phase comparison is performed at the trailing edge of 50.

As described above, the error data phase-compared by the phase comparison circuit 12 controls the oscillation frequency of VCO15 via LPF14, and VCO15 controls f = 4F _SC (F _SC is the frequency of the burst signal).
The reference clock of can be output from the output terminal 17.

FIG. 6 shows the phase comparison timing of the phase comparison circuit 12 in the vertical blanking period in which the color burst signal 22 does not exist. In FIG. 6, 60 is a vertical synchronizing signal of the composite video signal of waveform (I), and 61 is a vertical blanking period. That is, the vertical blanking period
61 does not have the color burst signal 22 but the horizontal sync signal 21 and TV
It is a portion having a test signal for use in the display (not shown).

The burst gate pulse 24 switched by the switching circuit 11 is supplied to the phase comparison circuit 12 of the PLL circuit in the vertical blanking period 61, and the 1/1820 divided signal 50 from the VCO 15 is supplied in the same manner as described above. Phase compared VCO
Controls 15 and outputs f = 4F _SC reference clock from output pin 17 from VCO15.

The lock state by the phase comparison of the phase comparison circuit 12 with the burst gate pulse 24 has a larger error voltage than the burst lock at the phase comparison of the latch pulse 40 synchronized with the color burst signal 22. A stable locked state can be obtained by sufficiently attenuating the high frequency error component in the LPF 14 in the subsequent stage of the phase comparison circuit 12.

As described above, in the vertical blanking period 61 in which the color burst signal 22 of the composite video signal is not present, the phase is compared by the burst gate pulse 24 and the burst lock is performed as described above, so that the conventional PLL circuit is used. It is possible to prevent the burst lock state of the device from going into the free-run state, and use the sample and hold circuit.
It is not necessary to hold the loop gain of the PLL circuit, and the response of the phase comparison operation of the PLL circuit can be stabilized.

[0049]

As described above, the burst signal processing circuit according to the present invention allows the burst gate pulse 24 generated from the horizontal synchronizing signal to output from the VCO 15 even in the intermittent vertical blanking period of the color burst signal of the composite video signal. Since the 1/1820 divided signal 50 and the phase comparison operation of the phase comparison circuit 12 can be continuously performed, there is an effect that the burst lock operation of the PLL circuit can be stably performed.

That is, unlike the conventional example, it is not necessary to hold the loop gain in the hold state for a long period during the vertical blanking period, and the sample hold circuit is eliminated in the PLL circuit loop, so that the response of the phase comparison operation is stable. It also has the effect of being faster.

Moreover, it has excellent features such as a simple structure and easy implementation because it can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a burst signal processing circuit according to the present invention.

FIG. 2 is a waveform diagram showing operation waveforms of a horizontal processing circuit and a color burst signal processing circuit of the present invention.

FIG. 3 is a circuit diagram showing an embodiment of a comparator circuit of the present invention.

FIG. 4 is a waveform diagram showing operation waveforms of the latch circuit of the present invention.

FIG. 5 is a waveform diagram showing the phase comparison operation of the phase comparison circuit in the video signal period having the color burst signal of the present invention.

FIG. 6 is a waveform diagram showing the phase comparison operation of the phase comparison circuit in the vertical blanking period without a color burst signal of the present invention.

FIG. 7 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Composite video signal input terminal 2 Sync separator circuit 3 Vertical sync separator circuit 4 Vertical blanking circuit 5 Horizontal sync separator circuit 6 1/2 divider circuit 7 Burst gate pulse circuit 8 Band pass filter (BPF) 9 Comparator 10 Latch circuit 11 Switching circuit 12 Phase comparison circuit 13 EN pulse input pin for sample hold 14 Low pass filter (LPF) 15 Voltage controlled oscillator (VCO) 16 1/1820 Frequency divider 17 Output pin

Claims (3)

[Claims] 1. A horizontal signal processing circuit for extracting a horizontal sync signal from a composite video signal to generate a color burst gate pulse at the same timing as a color burst signal, and a vertical blanking circuit for extracting a vertical sync signal from the composite video signal. A vertical signal processing circuit for generating a pulse and a color burst signal processing circuit for extracting a color burst signal from a composite video signal to generate a color burst square wave are provided, and the color burst gate pulse is latched by the color burst square wave. A latch circuit, a switching circuit for switching the latch signal of the latch circuit and the color burst gate pulse with the vertical blanking pulse, and a configuration in which the switching output signal is supplied to a PLL circuit to generate a reference clock. Burst signal processing circuit according to claim. 2. A ½ divider circuit for separating the horizontal synchronizing signal from the horizontal signal processing circuit and dividing the horizontal synchronizing signal by ½;
2. The burst signal processing circuit according to claim 1, further comprising a color burst gate pulse circuit for generating the color burst gate pulse according to the divided horizontal synchronizing signal. 3. The burst signal processing circuit according to claim 1, wherein the output signal of the voltage controlled oscillator of the PLL circuit is a 4f _sc reference clock.