JPH03211734A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03211734A JPH03211734A JP667190A JP667190A JPH03211734A JP H03211734 A JPH03211734 A JP H03211734A JP 667190 A JP667190 A JP 667190A JP 667190 A JP667190 A JP 667190A JP H03211734 A JPH03211734 A JP H03211734A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- aluminum
- wiring layer
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 23
- 150000002500 ions Chemical class 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体技術に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor technology.
特に、電極層と配線層の接続方法に関するものである。In particular, it relates to a method of connecting electrode layers and wiring layers.
［従来の技術］ 従来の半導体装置を、−例に取り概略を示そう。[Conventional technology] Let us give an overview of a conventional semiconductor device as an example.
半導体基板上に、Ｎ型多結晶シリコン層が電極層として
パターニングされている。Ｎ型多結晶シリコン中には通
常Ｉ Ｘ １０２°［個／ｃｍ−３１以上の燭、または
砒素が含まれている。 このＮ型多結晶シリコン層と、
配線層であるアルミニウム層は絶縁層を挟んで配置され
ており、Ｎ型多結晶シリコン層とアルミニウム層との接
続は接続孔を介して接続される。An N-type polycrystalline silicon layer is patterned as an electrode layer on a semiconductor substrate. N-type polycrystalline silicon usually contains I x 102[deg./cm-31 or more] or arsenic. This N-type polycrystalline silicon layer,
The aluminum layer, which is a wiring layer, is arranged with an insulating layer in between, and the N-type polycrystalline silicon layer and the aluminum layer are connected through a connection hole.
以上従来の半導体装置の概略をしめした。The outline of the conventional semiconductor device has been shown above.
［発明が解決しようとする課題］
従来の半導体装置では、この配線材である、アルミニウ
ム層中には通常耐エレクトロマイグレーション性を高め
るためや、アルミニウムの堆積時に形成されるグレイン
を小さくするために、不純物イオンを導入させている。[Problems to be Solved by the Invention] In conventional semiconductor devices, in order to improve electromigration resistance or to reduce the size of grains formed during aluminum deposition, the aluminum layer, which is the wiring material, usually contains Impurity ions are introduced.
この不純物イオン種としては、ホウ素、燐、ヒ素、アン
チモン、アルゴン、などがある。Examples of the impurity ion species include boron, phosphorus, arsenic, antimony, and argon.
Ｎ型多結晶シリコン層と配線金属、例えばアルミニウム
とのあいだを電気的に接続させる場合。When electrically connecting an N-type polycrystalline silicon layer and a wiring metal, such as aluminum.
接続するアルミニウム層中の不純物にはおもに次の３タ
イプがある。There are mainly three types of impurities in the connecting aluminum layer:
タイプ■１．配線層形成過程で不純物何も導入されなか
った。Type ■1. No impurities were introduced during the wiring layer formation process.
タイプＩ１．．配線層形成過程にＮ型不純物が導入され
た。Type I1. ．． N-type impurities were introduced during the wiring layer formation process.
タイプＩＩ１． 、配線層形成過程にＰ形不純物が導
入された。Type II1. , P-type impurities were introduced in the wiring layer formation process.
一般に、アルミニウムを堆積させた後、堆積時のダメー
ジを補償するために、水素雰囲気中で５００°Ｃ程度の
アニール処理をおこなっている。 配線層がアルミニウ
ム層でなく他の金属層の場合は、表面の安定化のために
、６００°Ｃから１０００°Ｃ程度の水素雰囲気中での
アニール処理を行う。Generally, after depositing aluminum, annealing treatment is performed at about 500° C. in a hydrogen atmosphere to compensate for damage during deposition. If the wiring layer is not an aluminum layer but another metal layer, annealing treatment is performed in a hydrogen atmosphere at about 600° C. to 1000° C. to stabilize the surface.
このアニール処理によって、配線層中の不純物は電極層
中に拡散する。By this annealing treatment, impurities in the wiring layer are diffused into the electrode layer.
従って従来例のような、Ｎ形番結晶シリコン中の配線材
料との接触部分でのＮ型不純物の正味の濃度は、タイプ
ＩＩ ＞タイプＩ〉タイプＩＩＩの順に小さくなってい
る。Therefore, as in the conventional example, the net concentration of N-type impurities at the contact portion with the wiring material in N-type crystalline silicon decreases in the order of type II>type I>type III.
従来技術によれば多結晶シリコンと配線層との接続は上
記の３タイプに関わりなく行なっていた。According to the prior art, the connection between polycrystalline silicon and the wiring layer was performed regardless of the above three types.
図３はアルミニウム配線層とＮ型多結晶シリコン層が接
触している部分のＮ型多結晶シリコン中に含まれている
正味のＮ型不純物に対する、アルミニウム層中に含まれ
るＰ型不純物の割合と接触抵抗の関係を示す図である。Figure 3 shows the ratio of P-type impurities contained in the aluminum layer to the net N-type impurities contained in the N-type polycrystalline silicon in the area where the aluminum wiring layer and the N-type polycrystalline silicon layer are in contact. It is a figure showing the relationship of contact resistance.
特に、第３図に示したように、タイプＩＩＩの様な場合
、シリコン中の正味のＮ型不純物中と配線層中の正味の
Ｐ型不純物との割合が３０パーセントを越えると、接触
抵抗は急激に増加してしまう。この増大した抵抗は、素
子の寄生抵抗となってトランジスタ回路の遅延時間を増
大させるばかりか、回路によって接触抵抗が異なるため
に、回路の安定動作領域が狭められてしまうという欠点
を有していた。In particular, as shown in Figure 3, in the case of type III, if the ratio of the net N-type impurity in the silicon to the net P-type impurity in the wiring layer exceeds 30%, the contact resistance will increase. It will increase rapidly. This increased resistance not only becomes a parasitic resistance of the element and increases the delay time of the transistor circuit, but also has the disadvantage that the stable operation area of the circuit is narrowed because the contact resistance differs depending on the circuit. .
そこで、本発明はこのような課題を解決しようとするも
ので、その目的とするところは、電極層と配線層との接
触抵抗を低く、しかも安定に保つことである。The present invention aims to solve these problems, and its purpose is to keep the contact resistance between the electrode layer and the wiring layer low and stable.
［課題を解決するための手段］
本発明の半導体装置は、半導体装置に於いて、第１導電
型の半導体を主成分として含んでいる電極層が形成され
て成り、該電極層と金属を主成分として含む第１配線層
との間を接続をさせる構造において、該第１配線層が電
極層と接触している領域の配線層中の正味の不純物にお
いて、該第１電極層中の第１導電型と異なる導電型の正
味の不純物濃度は該第１電極層中の第１導電型の正味の
不純物濃度の３０パーセント以内であることを特徴とす
る。[Means for Solving the Problems] A semiconductor device of the present invention is a semiconductor device in which an electrode layer containing a first conductivity type semiconductor as a main component is formed, the electrode layer and a metal as a main component. In a structure in which a connection is made between a first wiring layer included as a component, in a net impurity in the wiring layer in a region where the first wiring layer is in contact with an electrode layer, the first wiring layer in the first electrode layer is The net impurity concentration of a conductivity type different from the conductivity type is within 30% of the net impurity concentration of the first conductivity type in the first electrode layer.
［実施例］ 以下、本発明の半導体装置を詳細に説明する。[Example] Hereinafter, the semiconductor device of the present invention will be explained in detail.
第１図は、本発明による半導体の一実施例である。FIG. 1 shows an embodiment of a semiconductor according to the present invention.
半導体基板上に、Ｎ型多結晶８９３２層１０１が電極層
としてバターニングされている。Ｎ型多結晶シリコン中
には通常ｌＸ１０２０［個／ｃｍ−３］以上の燗、また
は砒素が含まれている。 このＮ型多結晶シリコン層と
、配線層であるアルミニウム層１０３は絶縁膜を挟んで
配置されており、Ｎ型多結晶シリコン層とアルミニウム
層との接続は接続孔１０２を介して接続される。 こ
の配線層である、アルミニウム層中には通常耐エレクト
ロマイグレーション性を高めるためや、アルミニウムの
スパッタ時に形成されるグレインを小さくするために、
不純物イオンを導入させる。この不純物イオン種として
は、ホウ素、燐、ヒ素、アンチモン、アルゴン、などが
ある。本実施例では、Ｎ型多結晶シリコン層と配線層で
ある、アルミニウム層との接続であるから、アルミニウ
ム層中に不純物イオンを導入させる場合は、少なくとも
、Ｎ型多結晶シリコン層と、アルミニウム層とが接触し
ている領域上のアルミニウム層中のＰ型不純物濃度は、
多結晶シリコン中に含まれているＮ型不純物濃度の３０
パーセント以下になるようなＰ型不純物濃度で導入した
。An N-type polycrystalline 8932 layer 101 is patterned on a semiconductor substrate as an electrode layer. N-type polycrystalline silicon usually contains 1×1020 [pieces/cm −3 ] or more of arsenic or arsenic. The N-type polycrystalline silicon layer and the aluminum layer 103, which is a wiring layer, are arranged with an insulating film in between, and the N-type polycrystalline silicon layer and the aluminum layer are connected through a connection hole 102. In order to improve electromigration resistance and to reduce grains formed during aluminum sputtering, there is usually a layer in the aluminum layer that is this wiring layer.
Introduce impurity ions. Examples of the impurity ion species include boron, phosphorus, arsenic, antimony, and argon. In this embodiment, since the connection is between the N-type polycrystalline silicon layer and the aluminum layer, which is a wiring layer, when introducing impurity ions into the aluminum layer, at least the N-type polycrystalline silicon layer and the aluminum layer are connected. The P-type impurity concentration in the aluminum layer on the region in contact with is
The concentration of N-type impurities contained in polycrystalline silicon is 30
The P-type impurity concentration was introduced at a concentration of less than %.
本実施例ではは、電極層としてＮ型多結晶シリコン層を
例にとったが、Ｐ型多結晶シリコン層、シリコン中のＮ
型拡散層、シリコン中のＰ型板散層と配線層との接触に
ついても同様である。また配線層についてもアルミニウ
ム層を例に取って説明したが、銅、金、白金、チタン、
タングステンなどの金属、あるいは金属を主成分として
している合金でもよい。In this example, an N-type polycrystalline silicon layer is used as an electrode layer, but a P-type polycrystalline silicon layer,
The same applies to the contact between the type diffusion layer, the P type diffusion layer in silicon, and the wiring layer. The wiring layer was also explained using an aluminum layer as an example, but copper, gold, platinum, titanium,
It may be a metal such as tungsten or an alloy containing metal as a main component.
［発明の効果］
以上本発明によれば、電極層と、配線層との接続抵抗を
低くしかも変動値も少なく形成することができたために
、半導体装置全体での最大動作周波数が５パーセント増
大したばかりではなく、回路の動作マージンも５パーセ
ント広げることができた。[Effects of the Invention] According to the present invention, the connection resistance between the electrode layer and the wiring layer can be made low and the fluctuation value can be reduced, so that the maximum operating frequency of the entire semiconductor device is increased by 5%. Not only that, but we were also able to widen the circuit's operating margin by 5%.
第１図（ａ）は、本発明の半導体装置の一実施例を示す
平面図であり、第１図（ｂ）は、第１図（ａ）のＡ−８
間の断面図を示している。
第２図はアルミニウム配線層とＮ型多結晶シリコン層が
接触している部分のＮ型多結晶シリコン中に含まれてい
る正味のＮ型不純物に対する、アルミニウム層中に含ま
れる正味のＰ型不純物の割合と接触抵抗の関係を示す図
である。
］０１
０２
０３
０４
０５
・Ｎ型多結晶シリコン層
・多結晶シリコンと配線層との接続孔
・配線層
・Ｐ型不純物を含む配線層
・多結晶シリコンと配線層との接続領
域
以上FIG. 1(a) is a plan view showing one embodiment of the semiconductor device of the present invention, and FIG. 1(b) is a plan view showing A-8 in FIG. 1(a).
A cross-sectional view is shown between the two. Figure 2 shows the net P-type impurity contained in the aluminum layer relative to the net N-type impurity contained in the N-type polycrystalline silicon in the area where the aluminum wiring layer and the N-type polycrystalline silicon layer are in contact. It is a figure showing the relationship between the ratio and contact resistance. ]01 02 03 04 05 ・N-type polycrystalline silicon layer ・Connection hole between polycrystalline silicon and wiring layer ・Wiring layer ・Wiring layer containing P-type impurities ・Connection area between polycrystalline silicon and wiring layer and above
Claims (1)
て含んでいる電極層が形成されて成り、該電極層と金属
を主成分として含む第１配線層との間を接続をさせる構
造において、該第１配線層が電極層と接触している領域
の配線層中の正味の不純物において、該第１電極層中の
第１導電型と異なる導電型の正味の不純物濃度は該第１
電極層中の第１導電型の正味の不純物濃度の３０パーセ
ント以内であることを特徴とする半導体装置。In a semiconductor device, an electrode layer containing a semiconductor of a first conductivity type as a main component is formed, and a structure is provided in which a connection is made between the electrode layer and a first wiring layer containing a metal as a main component. , in the net impurity concentration in the wiring layer in the region where the first wiring layer is in contact with the electrode layer, the net impurity concentration of a conductivity type different from the first conductivity type in the first electrode layer is
A semiconductor device characterized in that the net impurity concentration of the first conductivity type in the electrode layer is within 30%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP667190A JPH03211734A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP667190A JPH03211734A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03211734A true JPH03211734A (en) | 1991-09-17 |
Family
ID=11644837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP667190A Pending JPH03211734A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03211734A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268291B1 (en) | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
-
1990
- 1990-01-16 JP JP667190A patent/JPH03211734A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268291B1 (en) | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
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