JPH0237726A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To prevent wiring resistance due to oxidation of a gate electrode in the succeeding process from increasing by covering the entire surface of the gate electrode with a gate protection film with improved conductivity. CONSTITUTION:The entire surface of a gate electrode 14a and a wiring layer 14b consisting of a high melt-point metal layer, a high melt-point metal silicide layer, etc., which are easily oxidized is covered by a protection film 16b of a gate protection film 16a such as polysilicon and a protection film 16b of wiring layer, Thus, no oxidation reaction occurs in the gate electrode 14a itself, thus preventing gate insulation withstand voltage from deteriorating. Also. since the gate protection film 16a not only protects the gate electrode 14a but also is an electrically improved conductor itself so that the gate protection film 16a can be regarded as an electrode which is electrically connected to the gate electrode 14a. It eliminate oxidation of the gate electrode 14a and the wiring layer 14b, thus preventing wiring resistance increasing.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a manufacturing method on a semiconductor substrate, such as a high melting point metal,
Or, it has a gate electrode containing a high melting point metal silicide layer (silicon compound), etc.
(Doped Drain) This relates to a method for manufacturing a wt-based semiconductor element.

(Prior art) MO8 type field effect transistor (hereinafter referred to as MO8・FE'
Semiconductor devices such as semiconductor devices (referred to as 1') are being miniaturized to increase bond collection due to practical advantages, and their gate lengths tend to become shorter and shorter. Along with this, a phenomenon occurs in which carriers with relatively high energy are trapped in the gate insulating film due to the high electric field near the drain, reducing carrier mobility.
The electrical characteristics of the device are significantly deteriorated. Therefore, as a means to alleviate the concentration of the electric field near the drain and improve the drain breakdown voltage, the gate electrode is separated from the drain region to create an offset gate structure, and the offset portion from the train region to just below the gate electrode has an impurity concentration of Attempts have been made to fabricate an LDD structure that forms a diffusion layer with a low diffusion layer.

Conventionally, this type of semi-thick body Takako has been manufactured by, for example,
Electron Devices (IE)
TONS ON ELECTRON DEVIC
ES)-529-[4] (1982-4>(US)
There was one described in P, 590596. The manufacturing method will be explained below with reference to the drawings.

FIGS. 2(a) to 2(d) show the conventional M described in the above-mentioned document.
FIG. 3 is a manufacturing process diagram showing a method for manufacturing an OS-FET. This MOS-FET is manufactured through the following steps.

First, as shown in FIG. 2(a), a field insulation v2 is selectively formed on the P-type semiconductor substrate 1 with the orientation (100), and then a gate insulation film 3 is formed in the MOS-FET formation region. , W (tungsten), a high melting point metal, or WSi/polysilicon (polysilicon on the base, W on the top)
A film having a composite structure of Si (called polycide) or the like is formed on the surface of the semiconductor substrate 1. Further, the film is etched to form a gate electrode 4a and a wiring layer 41 on the gate insulating film 3 and field insulating film 2, respectively.
form. Thereafter, ion implantation is performed using the gate electrode 4a as a mask, and N is implanted into the semiconductor substrate 1 to form a first diffusion layer.
- Form JB5.

Next, as shown in Fig. 2(b),
After forming R on the entire surface of the semiconductor substrate 1, R
By using the IE method (reactive ion etching), sidewall films 6a and 6b are selectively formed only on the sidewall portions of the gate electrode 4a and wiring layer 4b.

Furthermore, as shown in FIG. 2(C), high-precision As (arsenic) ions are implanted into the semiconductor substrate 1 using the electrode 4a and the sidewall film 6a as masks, and N is then ion-implanted to form the second diffusion layer. "Layer 7 is formed.

Subsequently, as shown in FIG. 2(d), after an intermediate insulating film 8 is deposited on the entire surface of the semiconductor substrate 1, a contact hole 9 is formed in the intermediate insulating film PA8 by etching. Thereafter, by depositing and patterning a wiring metal 10 such as AI on the intermediate insulating rIAS, a DD type MOS-FE'l' having a high melting point metal gate is obtained.

(Problems to be Solved by the Invention) However, in the production of the above-mentioned MC>S FET by Yang Cheng, C had the following problems.

(a) Day 1 - Metal materials having a high melting point such as W and Mo (molybdenum) are often used for the gate electrode 4a in view of the resistance value reduction and heat resistance m1 of the electrode 4a.

By the way, the materials of the intermediate insulating film 8 covering the gate electrode 4a and the wiring layer 4b are 5i02°PSG (doped silicate glass), 38G (boron-doped silicate glass), and BPSG (adjacent and boron-doped silicate glass). It is of the S i 02 series such as. Therefore, the formation of the sidewall films 6a, 6a, the formation of the second diffusion layer 7,
During the subsequent oxidation heat treatment steps such as formation of the intermediate insulating film 8, the metal is oxidized and the wiring resistance increases, and furthermore, if the oxidation progresses significantly in the thin portions of the wiring layer 4b, there is a risk of disconnection.

(b) Since the sidewall films 6a, 6a do not function as electrodes, hot carriers generated under the sidewall films 6a, 6a are transferred to the sidewall WA6.
They are likely to be captured by the gate insulating film 3 directly below a and 6a. Generally, an MO having 1 N-channel type and 10 DDs is used.
It is known that in S-FIET', electrons are captured as pot carriers and electron traps occur. Therefore, as a phenomenon peculiar to the LDD structure, deterioration of the mutual conductance gII occurs due to an increase in the resistance component of the N-layer 5 at the initial stage of the experiment. This is the slope of the curve that gives the relationship between the drift current and the flowing drift current, and the larger this value is, the better the electrical characteristics of the device are.

In order to reduce this deterioration of mutual conductance gm,
Generally, the concentration of the N- layer 5 is set high. Therefore, in order to reduce electric field strength and substrate current, N-
N5 is optimized in the lowest possible concentration range, and it deviates from the woody advantages of DD Yokomichi.

(C) The material of the sidewall films 6b and 6b is 5jO.
2 series, and has the same basic physical properties as the field insulating film 2. Therefore, during the RIE process for forming the sidewall films 6b, 6b, the field insulating film 2 is reduced due to over-etching, which deteriorates the feed isolation characteristics.

The present invention addresses the problems that the prior art described in 01f had.
The metal used for the gate electrode is oxidized during the oxidation heat treatment process, increasing the wiring resistance; the mutual conductance deteriorates as the resistance component of the first diffusion layer increases during the initial stage of the operation test; and the film of the field insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor device that solves the problem that the feed separation characteristics deteriorate due to the decrease in the feed separation characteristics.

(Means for Solving the Problem) In order to solve the problem, in the invention of claim 1, after forming a gate electrode in a predetermined region on a semiconductor substrate, a first diffusion layer is selectively formed on the semiconductor substrate. and a second step of forming a second diffusion layer having a higher concentration than the first diffusion layer on the semiconductor substrate. The process is structured as follows.

That is, the second step includes a step of selectively depositing a gate protective film on the entire surface of the gate electrode, and a step of diffusing impurities into the gate protective film to form a conductive type gate protective film. The steps of forming the second diffusion layer by ion implantation using the gate protection film and the gate electrode as masks are sequentially performed.

In the invention according to claim 2, in the invention according to claim], a foot insulating film is selectively formed on the semiconductor substrate before forming the gate electrode, and further, the second step is performed only on the conductive material. A process of depositing a gate protective film on the entire surface of the electrode on the gate 1 using a chemical vapor deposition method under conditions for selectively growing a film, and diffusing impurities into the gate protective film to make the gate conductive. A process of forming a gate protective film of a mold type and a process of forming the second diffusion layer by ion implantation using the gate protective film and the gate electrode as masks are performed in order.

(Function) According to the invention of claim 1, since the method for manufacturing a semiconductor device is configured as described below, the gate protective film formed so as to cover the entire surface of the gate electrode can be removed during the subsequent oxidation heat treatment step. It works to prevent the gate electrode from being oxidized and the wiring resistance increasing. In addition, since the gate protective film is formed as a good electrical conductor, it prevents the capture of hot carriers in the gate insulating film directly under the gate electrode, and also promotes the generation of new carriers, significantly deteriorating the mutual conductance. Work to suppress it.

In the invention of claim 2, the selective chemical vapor deposition method that selectively grows a film only on conductive materials does not require an etching process when forming the gate protective film, so the field insulating film is not damaged. Maintain sufficient field separation characteristics without incurring

One foot can solve the above problem.

(Embodiment) FIGS. 1(a) to 1(d) are manufacturing process diagrams showing a method of manufacturing a MOS-FET according to a first embodiment of the present invention. The manufacturing method will be explained below with reference to the drawings.

(i>Process shown in FIG. 1(a)) First, a field insulation V412 with a film thickness of approximately 5000 mm is selectively formed on a semiconductor substrate 11 made of P-type silicon with a plane orientation of -(100), for example, and then a MOS -F
A gate insulating film 13 is formed in the active region for ET formation.

Next, a film with a thickness of 300 mm is formed on the entire surface of the semiconductor substrate 11 by sputter deposition, CVD (chemical vapor deposition), or the like.
After covering with a 0W film, a gate electrode 1421 and a wiring layer 14b are formed using a buttering method.

Thereafter, using the gate electrode 14a as a mask, As ions are implanted into the semiconductor substrate 11 at about 40 KeV and a dose (number of atoms of ions implanted per unit area) of about 1 to 2 x 1013 cm' to form the first diffusion layer. as N11J
9(ii) Step of FIG. 1(b) to form a film 15 with a thickness of 20
After growing polysilicon, etching is performed to form a gate protection film 16a on the entire surface of the gate electrode 14a, and also to protect the entire surface of the wiring layer 14b.
16b.

Next, P is diffused into the gate protective film 16a and the wiring layer protective film 16b at a concentration of about 2×10 20 cm −3 or more by a thermal diffusion method at a temperature of 900° C., for example, to improve the conductivity.

(City) Process of FIG. 1(C) Using the gate electrode Kf414a and the gate protective film 16a as masks, As ions are implanted into the semiconductor substrate 11 at a dose of about 40 Kev and a dose of about ft5 x 1015 cm m-''. N-layer (first diffusion layer) 1 as a diffusion layer of
After forming the N+ layer 15 with a higher impurity concentration than 5, approximately 9
A drive-in process is performed in a nitrogen atmosphere at 00°C. This drive-in process is to diffuse ions in the N+ layer 15 by heat treatment and control the thickness and depth.

(1) Process shown in FIG. 1(d) From this step onwards, the same processing as for a normal MOS-FET is performed.

That is, the entire surface of the semiconductor substrate 11 is covered with, for example, a film) C1,6°0.
After seeding a BPS G film of 08 degrees as the intermediate insulating film 18, contact holes 19 are formed at predetermined locations in the intermediate insulating film 18 using the buttering method.

After that, for example, after depositing AρSi with a film thickness of about 1 μm by sputtering or the like, and forming the wiring layer 20 by etching, the M
An OS-FET is obtained.

The following explanation has been about the N-channel type MO8-FET, but the same applies to the 1] channel type MO3-FET.

The advantages of the first embodiment can be summarized as follows.

(1) Gate electrode consisting of a high melting point metal layer, high melting point metal silicide layer, etc. that is easily oxidized; i+? ) 414a and the wiring layer 14b are covered with the gate protection pattern 16a made of polysilicon or the like and the wiring layer protection J pattern 16b, resulting in the following advantages.

(2) In the oxidizing atmosphere heat treatment step for forming the intermediate insulating film 8, etc., the gate electrode 14a and the wiring layer 14b are not oxidized, so an increase in wiring resistance can be prevented.

■ S is removed by oxidation, expansion iis', cV
When cleaning the i-wafer, the gate electrode ++14a and the wiring 114b do not come into direct contact with chemicals such as HF (hydrofluoric acid). Therefore, the high melting point metal material is not melted, and an increase in wiring resistance can be prevented.

(2) When the gate electrode 1.4a has a polycide structure, a problem unique to this structure is deterioration of the gate dielectric breakdown voltage. Most of the causes of this problem are that when the gate electrode 14a is oxidized during heat treatment in an oxidizing atmosphere, a partial interfacial reaction occurs between the upper and lower layers of polycide, and this reaction causes It is thought that this is due to the stress caused.

In this embodiment, the entire surface of the gate electrode 14a is covered with the gate protective film 16a, and no oxidation reaction occurs in the gate electrode 14a itself, so that deterioration of the gate dielectric breakdown voltage can be prevented.

(2) The gate protection film 16a not only protects the gate electrode 1tLa, but also is itself a good electrical conductor.

Therefore, the gate protective film 16a can be regarded as an electrode electrically connected to the gate electrode 14a, resulting in the following advantages.

(a) Since hot carriers are less likely to be trapped in the gate insulation 1 13 directly under the gate protection PLA 16 a, it is possible to eliminate the deterioration of the mutual conductance gIIl caused by the increase in the resistance component of the N-layer 15 caused by the capture of hot carriers. .

(b) As in (a) above, since there is almost no problem with the capture of boll-carriers, the formation conditions such as the impurity concentration distribution and junction depth in the N-layer 15 should be adjusted to suit the original purpose of the LDD structure. Conditions can be set as follows.

(c) Since the gate protection film 16a also has a function as an electrode, carriers are newly induced in the N- layer 15 directly under the gate protection film 16a during operation of the device. Therefore, the resistance value of the N-I element 15 is effectively reduced, and it is possible to obtain a higher mutual conductance gIIl than in the past.

Next, the manufacturing method of the second embodiment will be explained using FIG. 1.

In this example, (C
), the gate protection pA 16a and the wiring layer protection film 16b are formed by the CVD selective polysilicon growth method.

A feature of this method is that it has a selective covering growth function in which polysilicon is grown only on conductive materials, and polysilicon is not grown on insulating materials such as SiO2. The following table shows the formation conditions that enable this selective polysilicon growth.

1. If polysilicon is grown to a thickness of about 20,000 on the surface of the semiconductor substrate 11 using this method, polysilicon will not grow on the field insulating film 12 and the gate insulating film 13, and the gate electrode The gate insulation film 1 is formed so as to cover the entire surface of the wiring layer 14a and the wiring layer 14b, respectively.
6a and a protective film 16b for the wiring layer are formed.

The second embodiment has the following advantages.

(A> Same advantages as advantages (1) and (2) of the first embodiment.

(B) Gate protective film 16a and wiring layer protective film 16
Since no etching process is required when forming b,
There is no change in the thickness of the field insulating film, and sufficient field isolation characteristics can be maintained.

Next, a third example will be described.

FIG. 3 shows complementary MO8= according to the third embodiment of the present invention.
FET (Complementary MOS-FE)
1 is a diagram illustrating a method of manufacturing a P-channel MO3-FET in a manufacturing method ('T'').Elements common to those in FIG. 1 are denoted by the same reference numerals. do.

First, a field insulating film 12 is formed on a semiconductor substrate 11 made of P-type silicon with a plane orientation of (100), and an N-well layer 21 is selectively formed on the surface of the semiconductor substrate 11. Next, an N-IP 7 for a buried channel is formed in a predetermined region on the surface of the semiconductor substrate 21, and the semiconductor substrate 21 is
After forming the gate insulating film 13 on the gate electrode 1
4a is selectively formed. Furthermore, after depositing, for example, polysilicon on the semiconductor substrate Lh, etching is performed to form a sidewall film 23. Subsequently, impurities are thermally diffused to increase the conductivity of this sidewall film 23, giving it a function as an electrode. After that, ion implantation is performed using the gate 1 pole 14a and the sidewall M23 as a mask, and P-type source/drain regions 15 are implanted.
form.

This embodiment has the following advantages.

Generally, the sidewall film 23 is made of an insulating material, so that the gate electrode 14a and the source/drain region 15 are offset from each other by 4'I! In the case of four structures, the mutual conductance g111 significantly deteriorates.

In this embodiment, new carriers (holes) are induced directly under the sidewall film 23, so even in such an offset structure, it is possible to suppress the deterioration of the mutual conductance gIll to a low level.

Note that the present invention is not limited to the illustrated embodiment, and various modifications can be made to the conditions in each manufacturing process, such as using other materials for the ↑M component. For example, the gate electrode 4a
T i S i /polysilicon, W
It is also possible to use a material containing a high melting point metal such as Si/polysilicon and W/polysilicon or a high melting point metal silicide layer.

(Effects of the Invention) As described above in detail, according to the invention of claim 1, the entire surface of the gate electrode is covered with a highly conductive gate protection film, so that the gate electrode can be removed in the subsequent manufacturing process. It is possible to prevent an increase in wiring resistance due to oxidation of the electrodes, and to significantly suppress deterioration in mutual conductance caused by an increase in the resistance component of the first diffusion layer that occurs at the initial stage of an element operation test.

In the invention of claim 2, since the gate protective film is formed by the C'VD method, which selectively grows a film only on good electrical conductors, there is no need for an etching process when forming the gate protective film, and field insulation is improved. It is possible to retain sufficient field separation properties so that the membrane is not damaged.

Therefore, it is expected that high-quality semiconductor elements with extremely high reliability and excellent electrical characteristics can be manufactured.

[Brief explanation of the drawing]

1(a) to (d) are manufacturing process diagrams showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIGS. 2(a) to 2(d) are
(d) is a manufacturing process diagram showing a conventional method for manufacturing a semiconductor device, and FIG. 3 is a manufacturing process diagram showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. 11... Semiconductor substrate, 12... Field insulating film, 14 total... Goo 1 to electrode, 15...
...First diffusion layer, 16a... Gate protection film, 17... Second diffusion layer. 11: Semiconductor substrate 12: Field isolation 8 equipment 14a: Gate tornado 15; 1st r > expansion ■ 16a: Gate protective film

Claims (1)

[Claims] 1. After forming a gate electrode in a predetermined region on a semiconductor substrate, a first step of selectively forming a first diffusion layer on the semiconductor substrate; a second step of forming a second diffusion layer having a higher concentration than the diffusion layer of the method, wherein the second step includes selectively forming a gate protective film over the entire surface of the gate electrode. a step of depositing an impurity into the gate protective film to form a conductive type gate protective film;
1. A method of manufacturing a semiconductor device, comprising sequentially performing steps of forming a diffusion layer. 2. After selectively forming a field insulating film on the semiconductor substrate and forming a gate electrode in a predetermined region on the semiconductor substrate, a first step of selectively forming a first diffusion layer on the semiconductor substrate. and a second step of forming a second diffusion layer with a higher concentration than the first diffusion layer on the semiconductor substrate, wherein the second step includes forming a second diffusion layer in a conductive material. A process of depositing a gate protective film on the entire surface of the gate electrode using chemical vapor deposition under conditions that selectively grow a film, and a step of diffusing impurities into the gate protective film to form a conductive type. A method for manufacturing a semiconductor device, comprising sequentially performing a step of forming a gate protective film and a step of forming the second diffusion layer by ion implantation using the gate protective film and the gate electrode as masks.