JPH03210687A - Card reader - Google Patents

Abstract

PURPOSE:To correctly detect an information bit string through simple configuration by providing a card reading part provided with a sensor common to the information bit string and a first and a second sensors to be used for latching a bit, and a counter. CONSTITUTION:The card reading part 10 provided with the sensor 11 common to the information bit string and the first and the second sensors 12a, 12b for latching the bit, and an up-down control circuit 30 to which the outputs of a pair of the sensors 12a, 12b for latching the bit are supplied are provided, and the up-down control circuit 30 is provided with a first data latching means 31 which makes the output of the first sensor 12a its clock and makes the output of the second sensor 12b to be obtained at timing different from that of the output of the first sensor its data, and a second data latching means 35 which makes the output of the second sensor 12b its clock and makes the output of the first sensor 12a to be obtained at timing different from that of the second sensor its data. Thus, an information it can be read correctly whether the inserting direction of a card is forward or backward.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a card reading device that can read information without error and can reduce costs.

[Background of the Invention] The following two types of card reading devices are known as card reading devices that read the information bits of a card that has m columns (m and n are integers) of information bit strings each consisting of n bits. It is being

The first case is when the card is completely inserted into the reading device and the contents of the information bits are read simultaneously by m rows and n sensors.

The second case is when the information bits are sequentially read while inserting the card using a sensor consisting of n columns.

[Problem to be solved by the invention] In the first means, m''n sensors are required, so
The number of parts is large, leading to increased costs.

The second method uses n sensors arranged in rows to read m rows of information bits, which has the effect of reducing the number of parts; There is a risk that the information bits may be read incorrectly.

Therefore, this invention takes these points into consideration,
The present invention proposes a card reading device that can read information without error and can reduce costs.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a card for reading cards that is composed of a plurality of information bit strings and latch pits provided at both ends of the information bit strings. The reading device includes a card reading section provided with a common sensor for the information bit string and first and second sensors used as latch pits, and a card reading section that is provided with a sensor common to the information bit string, and a first and second sensor used as a latch pit, and a card reader that latches the latch according to the entry and exit of the card. a counter that performs up/down operations in synchronization with the pits; a latch unit that decodes the output of this counter and latches bit information from a corresponding information bit string; and an up/down unit to which the sensor outputs of the pair of latch pits are supplied. and a control circuit, the up-down control circuit has a first data latch means that uses the first sensor output as a clock and uses the second sensor output obtained at a timing different from the first sensor output as data. and a second data latch means that uses the second sensor output as a clock and uses the first sensor output obtained at a timing different from the second sensor output as data. .

[Operation] Since the co-card reading unit 10 is configured with n sensors arranged in a row, the information bits of the m columns of information bit strings are sequentially read while the card 1 is inserted.

Since the first and second sensor outputs a and b (Fig. 4 A and B) are obtained at different timings, by monitoring which one is output first, it is possible to ensure that the card 1 is inserted and removed. can be determined.

In this example, the card is inserted when the first sensor output a is obtained early. At this time, the up-down control circuit 3o outputs a positive level up-down pulse g (E in FIG. 4). The counter 40 performs an up operation.

As a result, the decoded output shown in FIG. 5 is obtained from the decoder 60, and the information bits of each information bit string (in this example, six columns from 0 to 5) are output from the corresponding latch circuits 21 to 5 in a predetermined order. It is latched at 26.

On the other hand, when the second sensor output is obtained quickly (when the card is removed), the up-down control circuit 30 outputs a negative level up-down pulse g (E in FIG. 4). The counter 40 performs a down operation.

As a result, the reverse decoded output shown in FIG. 5 is obtained from the decoder 60, so the information bits of the respective information bit strings 0 to 5 are latched by the latch circuits 21 to 26 in the reverse order to that described above. Ru.

Therefore, the information bits can be read correctly regardless of whether the card 1 is inserted in the forward or reverse direction.

[Embodiment] Next, an example of a card reading device according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

For convenience of explanation, a card on which information bits are recorded will be explained.

FIG. 2 shows an example of a card 1 on which information bits are recorded, and information bit 2 is recorded in the center thereof. In this example, information bits are recorded by punching, but there are no particular restrictions on the recording method.

In this example, one column is formed of a maximum of n information bit strings (n is an integer) or a maximum of m columns (m is a positive integer).

In the example shown in the figure, when n=”8.m=6, latch bits 4a to 9a, which determine the latch timing for latching the information bits of each information bit string, are provided at both ends of the information bit strings O to 50. , 4b to 9b are formed.

The information bit 2 is bored in a circular shape, whereas the latch bits 4a to 9a and 4b to 9b are all bored in an elliptical shape with the long axis in the insertion direction.

Moreover, the relationship between the information bit string and the latch bit is that, if we take the information bit string O as an example, as shown in FIG. The latch bit 4b can be punched out on the side subsequent to the detection area of the information bit 2 in common.

Then, the section where latch bits 4a and 4b match is exactly the section where information bit 2 exists, and the information bit is latched in this section.

In addition, by making the drilling positions of the latch bits 4a and 4b different in this way, when the card 1 is inserted in the forward direction (in the direction of the arrow in FIG. 2), the latch pit sensor 12b is
Sensor output a can be obtained faster from point a. On the other hand, when the card 1 is pulled out in the opposite direction, the sensor output is obtained faster from the latch bit sensor 12b than from the latch bit sensor 12a.

Therefore, by monitoring the output timings of the sensor outputs a and b, it is possible to reliably detect whether the card 1 is in the inserted state or in the withdrawn state.

As shown in FIG. 2, the card 1 is further provided with a bit 3 drilled in a position preceding the latch bit 4a for recognizing the front and back sides of the card 1.

When information bits are recorded by punching them in this way, a sensor (card reading section) 1 that recognizes the information bits, etc.
0, an optical sensor is used.

Therefore, as shown in FIG. 2, in this card reading section 10, n sensors 11 for information bits are arranged in columns corresponding to the maximum number n of bits formed in the information bit string. At both ends of the information bit sensor 11, latch pit sensors L2a and 12b are arranged to detect the latch bits 4a to 9a and 4b to 9b.

Now, the information bits of the card 1 configured as described above are read by the card reading device 20 shown in FIG.

The data group y of information bits (C in FIG. 4) read by the information bit sensor 11 is supplied to the latch circuits 21 to 26 corresponding to the information bit strings O to 5, and is latched at a predetermined timing to be described later. . Here, the read state is controlled a1 so that the information bit string O is always latched only by the latch circuit 21. Information bits 1-5 are similarly controlled to be read by corresponding latch circuits 22-26.

After the sensor outputs a and b from the latch pit sensors 12a and 12b (Fig. 4 A, B) Lt are outputted to a predetermined clock h (Fig. 4 D) through the ant circuit 45, the up/down counter 40 is supplied to

The sensor outputs a and b can also be supplied to the up/down control circuit 30.

This control circuit 30 includes 1. A pair of D-type frits 7'31.3 act as latching means for sensor outputs a and b.
5, and the sensor output a is supplied as a clock to the flip-flop 35, and the sensor output a inverted by an inverter 36 is supplied as data. Its output (FF
output) and sensor output a are logically multiplied by the AND circuit 37,
This AND output e (O in FIG. 4) is supplied to the set terminal S of the R3 type flip-flop 38.

The AND output e passes through the OR circuit 39 to the flip-flop 3
It is used as a reset pulse f (FIG. 4R) of 1.

One of the flip-flops 31 uses the sensor output a as a clock, contrary to the above.
The inverted data in step 2 is supplied as data. Then, the output (FF output) and the sensor output are ANDed by the AND circuit 33, and this AND output C (Q in FIG. 4) is
It is supplied to the reset terminal R of the type 3 flip-flop 38.

The AND output C passes through the OR circuit 34 to the flip-flop 3
It is used as the reset pulse d (first AF) of No. 5.

Therefore, if the card is inserted in the forward direction, the sensor output a
Since this is obtained faster than the sensor output, an AND output e, which is similar to the sensor output a, can be obtained, thereby holding the flip-flop 38 in the set state. Therefore, the output (up/down pulse) g (41st! IE) of the flip-flop 38 remains at a high level.

On the other hand, if the card 1 is withdrawn midway, the sensor output S is obtained faster than the sensor output a, so when the sensor outputs as in the first AF, the same OR output d is obtained. The flip-flop 38 is reset by this OR output d, and this state continues until the card is removed.

Therefore, the up/down pulse g is inverted to low level and maintained at this level.

Pulse R supplied to OR circuits 34 and 39 represents a reset pulse. The same applies thereafter.

The up/down pulse g is supplied to the counter 40 and the enable signal forming circuit 50 as described above.

Enable signal formation diagram jif! ! 50 is composed of a D-type flip-flop 51, an exclusive OR circuit 52, and a preset type D-type flip-flop 53;
The flip-flop 51 is supplied with the AND output as a clock and the up-down pulse g as data, and the FF output i (fourth AF) obtained from the flip-flop 51 and the up-down pulse g are exclusive ORed.

This exclusive OR output (EOX output) j (Fig. 4G) is supplied as a preset signal to the flip-flop 53, and the AND output is supplied as a clock. The logical sum output becomes the enable signal k (FIG. 4H).

In this example, the counter 40 performs the enable operation when the enable signal is inverted, so even if only an AND output is obtained, the up-down operation is not performed unless the enable signal k becomes low level.

As a result, as shown in FIG. 4, in card insertion I, the count-up operation is prohibited at the timing when the information bit string O is obtained, and the count-up operation starts at the information bit string 1.2. Card exit II, card insertion I1
The same applies to 1. However, card exit II is a countdown operation.

The counter output (4 bits) of the counter 40 is TE.

It is converted into 6-bit decoded outputs DO to D5 by the cog 60 (see FIG. 5).

The decode output Do-D5 is logically multiplied by AND circuits 71 to 76 corresponding to the AND output, and its output (latch pulse) (1-q (■ to N in Figure 4)
The information bit string (data group y) supplied to is latched.

Therefore, when the counter output is "0OOOJ" (no count), only the decode output DO becomes "1" and the latching time! Since only the latch circuit 21 performs the latch operation, the information bits of the information bit string O are latched by the latch circuit 21.

When information bit string 1 is read, the counter 38 counts up at this time, so the decoded output becomes ro.
ooIJ, and only the latch circuit 1122 latches the information bit of the information bit string 1.

Further, when the card 1 is pulled out midway and the card is withdrawn, the information bit string that was read immediately before must be read again. For example, information bit string 2
When the card 1 is removed after being read, this information bit string 2 will be read again.

However, during this information bit reading period, the enable signal k remains at a high level, so the up-down operation of the counter 38 is prohibited, and the decoded output also maintains the previous state. Therefore, the information bits of the information pit string 2 are latched again by the latch circuit 23. Therefore, even if the card 1 is moved in the exit direction, there is no change in the read information obtained, and this will not result in an erroneous detection operation.

Even if the card 1 is removed and then reinserted, an incorrect detection operation will not occur.

The latch output S a = S f and the decode output D5 are supplied to a CPU (not shown), where processing such as information analysis is performed.

In FIG. 1, reference numeral 80 indicates a circuit for determining whether the card 1 is front or back. This is composed of a flip-flop 81 whose sensor output is supplied as a clock, and a flip-flop 82 whose FF output is used as a reset pulse and whose sensor output a is used as a clock.

The FF output r is supplied to the CPU as a front/back discrimination output.

When card 1 is face up, the FF output r (S in FIG. 4) is at a high level.

Note that the OR circuit 83 is a reset pulse forming means for the flip-flop 81.

[Effects of the Invention] As explained above, according to the present invention, in addition to the special feature of simplifying the configuration of the card reading unit, the information pit string can be detected without error even when the card is inserted or removed. has.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an example of a card reading device according to the present invention, FIG. 2 is a diagram showing the relationship between a card and a card reading section, and FIG. 3 is a diagram showing the relationship between an information pit row and a latch pit. FIG. 4 is an explanatory diagram of the reading operation, and FIG. 5 is a diagram showing the relationship between the counter output and the decode output. 1 ・ 2 ・ 3 ・ 4a ~ 9a ・ 4b ~ 9b ・ ・Card・Information bit・Front and back recognition pin・Latch pit・Latch pit 10 ・ 11 ・12a, 12b ・21～26 ・30 ・40 ・50 ・60 ・80 ・a, b ・ 0 k ・ Do-D5 ・ ・Card reading section・Information bit sensor・Latch pit sensor・Latch circuit・Up/down YMM circuit・Up/down counter・Enable signal forming circuit・Decoder・Front/back discrimination circuit・Sensor output ・Up/down pulse ・Enable signal ・Decode output

Claims (1)

[Claims] (1) In a card reading device that reads a card composed of multiple information bit strings and two latch bits provided separately from the information bit strings, a common sensor for the information bit strings and a latch bit are used. a card reading unit provided with first and second sensors, a counter that performs up and down operations in synchronization with the latch bit in response to entry and exit of the card; and a counter that decodes the output of the counter. , a latch means for latching bit information from a corresponding information bit string, and an up-down control circuit to which sensor outputs of the pair of latched bits are supplied, and this up-down control circuit receives the first sensor output. a first data latch means that uses the second sensor output as a clock and uses as data a second sensor output obtained at a timing different from the first sensor output; and second data latch means that uses a first sensor output obtained at a timing as data.