JPS5855B2 - Kirokubaitaini Jiyouhouou Kirokusai Seisuruhouhoutou Souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for recording and reproducing coded data information on a recording medium and using tracks of clock information recorded on the recording medium to control the reproduction of the data information. .

Although the invention has been described with respect to recording and reproducing encoded data information on credit cards, it is clear that said recording and reproducing may also be provided for other types of recording media.

Credit cards are of the type that include a plurality of discrete areas arranged along parallel tracks, such as apertures or dots, forming areas of different transmissivity with respect to the periphery, where the discrete areas contain data information. is expressed in binary form.

In addition to troubleshooting coded data information, credit
The card also includes at least one clock information track.

The number of tracks storing coded binary information is four, and all four tracks are used to provide 16 possible binary combinations.

Therefore, at various progressive positions along the track, different binary characters are stored to store the desired information.

The storage of the binary information occurs at predetermined intervals along the track, so that the binary information is stored at discrete locations along the track.

In order to reproduce the binary information stored on the credit card, a track of clock information is also placed on the credit card, the clock information track being parallel to the binary information track.

In particular, the center track is the clock track, but 2
There are fewer discrete positions of clock information than clock information.

In particular, in certain embodiments of the invention, there is one clock signal for every other binary character.

By using a smaller number of clock positions relative to the number of binary character positions, incorrect timing caused by unauthorized card movement during timing playback can be eliminated.

Reproduction of the data and clock information tracks on the credit card is accomplished using a light emitting diode and a detection diode pair.

In particular, one pair is used to read each of the four data tracks and two pairs are used to read one clock track.

In addition, other pairs of diodes are connected to the leading edge of the card as it enters the card reader and to the leading edge of the card as it enters the card reader.
Detect the same edge of the card when it reaches the bottom of the reader.

4 of the data to represent a binary character in each consecutive position.
Assuming that the track has openings or points at predetermined intervals along the track, the clock
The track has an opening or dot for each letter.

The two pairs of diodes used to read the clock track are spaced the same distance apart as between the characters of the data track.

Therefore, recovery of clock information alternates between the two pairs of clock detection diodes, as one of the diode pairs reads each clock signal.

This modification is a bistable flip-flop (hereinafter referred to as FF).

), so the output from one sensor sets F-F and the output from the other resets F-F.

The change of F--F according to the continuous reading of clock information by the two pairs of clock sensors controls the reproduction of information in the data track and transfers this reproduction information to the storage section.

Due to the precise bistable triggering of F-F, the clock system does not change between states due to small variations in motion as the discrete field passes through the detection threshold of the sensor.

The actual emission/detection pair used to reproduce the information on the credit card operates in a pulsed mode.

For example, a light emitting diode (L
ED) are each turned on approximately every millisecond.

When a card enters the reader, the LEDs that read both the data and clock tracks are pulsed at a rate of approximately 1 millisecond, and the detector is also energized only while pulsing the light emitter.

This reduces the probability of receiving fraudulent data.

The particular type of credit card is of the type disclosed in commonly assigned application to John Earl Schyantlin, filed February 3, 1972.

However, although the present application is based on the type of credit card disclosed in the above-mentioned co-application, the method and apparatus for recording and reproducing information may be applied to other types of credit cards or other types of recording media. It is recognized that this can also be applied.

It is an object of the present invention to provide at least one data detector and at least one pair of clock detectors, to store data information from the data detector by means of a clock signal from one of the clock detectors, and to store data information from the data detector by a clock signal from one of the clock detectors. An object of the present invention is to provide a reproducing device having a self-clock function for reproducing stored information.

A clearer understanding of the coding apparatus and method of the present invention can be obtained with reference to the following description and drawings.

FIG. 1a is a functional block diagram of the logic of the card reader device, and FIG. 1b illustrates the timing sequence of various functions performed in the device of FIG. 1a during one pulse cycle.

In FIG. 1a, a card reader slot 10 is used to accept a credit card having encoded data and clock information in the manner illustrated in FIG.

In order to read the encoded data and clock information and to detect the presence of a credit card, LEDs and photodetectors forming a plurality of light sensors, ie eight, are used in the sensing process.

In particular, the optical sensors are a pair of clock sensors that form clock A and clock B signals and four data sensors that form data 0 to data 3.

The optical sensor described above includes six LEDs grouped together in the first block 12.

The last two photosensors are grouped into block 14
It includes an ED and is used to sense the top and bottom positions of the card as it passes through the card reader slot 10.

A first group of photodetectors 16 receives the information encoded on the card as determined by the light from the group 12 of LEDs.

A second group of two photodetectors 18 receive information for cards that enter the slot and reach the bottom of the slot.

In particular, the information received by the sensor formed by LED 14 and photodetector 18 is used to provide a signal to card presence detector 20 .

The card presence detector generates an output signal (PARK+);
This PARK+ signal is used to activate a group of LEDs 12.

The output signals generated by the photodetectors of group 16 are sent to a group of amplifiers forming group 22.

The output from amplifier 22 is connected to clock logic 24 and data
is sent to register 26.

and a clock logic section 24. Both data registers 26 are controlled by the CHIB- signal, which inhibits card reading until certain conditions are met.

Even assuming these conditions are met, data register 26 is prohibited from operating to receive and pass data information until the data register receives the DRES+ signal from clock logic 24. .

The information transmitted from data register 26 is transferred to buffer 2.
8 and stores the information until buffer 28 is polled by computer communications circuitry, which is not directly related to this application.

To ensure that the various operations described above with reference to the apparatus of FIG. 1a are performed consistently and at the proper times, special operations are performed during different time slots of the overall pulse cycle.

In particular, as shown in Figure 1b, the total cycle is 1.04 m5
during this basic cycle, from LTO to L
It is divided into 10 equal time slots designated T9.

In particular, in the LT0 time slot, the device is checked to determine that the clock logic is cleared.

The LT/ and LT2 time slots are used to sense the A and B clock signals, and the LEDs corresponding to A and B clock sensing are pulsed only during these time slots.

LT3 is the extra used time slot and LT4
The LT7 time slot is used to read encoded data information on a credit card using a data sensor.

LT8 and LT9 are time slots used to track the position of the card when it enters the card reader slot and reaches the bottom of the card reader slot.

FIG. 1c illustrates a standard time slot with a duration of 104 μS, the 10 time slots making up a total pulse cycle.

Within the time slot shown in FIG. 1, the actual clock pulse (CK+) occurs at the end and is shown to have a time interval of 6.5 μS.

2 and 3, an optically encoded credit card 100 is illustrated in FIG. 2 and a card reader 102 illustrated in FIG. Accept 100.

Credit card 100 includes an encoded area 104 having five information tracks designated 106-114.

Center track 110 is a clock track and has one discrete area for every other character formed by the discrete areas of the other four tracks located on either side of the center track.

The discrete area has a different transmittance than the surrounding area, and is either less or more transmittable than the surrounding area.

The discrete areas of the data tracks forming each character are optically offset from each other to maximize the size of the discrete areas while leaving sufficient spacing for the discrete loads to differentiate between areas.

For example, the discrete areas of each track are separated by a distance of 180 mils, and as discussed above, the entire character is formed by one bit from each of the four data tracks.

Internal data track is 90% from external data track
The mil offset allows the truck to be centered on 130 mils, providing sufficient distance for discrete loads.

Since the clock track area is placed on every other data character, the clock track loading interval is 180
That's twice as many mils, or 360 mils.

Of course, discrete areas are illustrated for all possible positions of the data tracks, but for a particular binary character, the specific area given to the four data tracks for a particular character is It is observed that the discrete range of depends on the binary value of this character.

FIG. 3 illustrates card reader 102 and specifically shows slot 116 for accepting credit card 100. FIG.

Also shown are sensor positions for detecting card position and information encoded on the card.

Specifically, sensor location 118 indicates that the card is in card slot 1.
The leading edge of the card as it passes through 16 is detected.

Sensor 120 detects when the card is fully seated within card slot 116.

Sensor locations 122, 124 labeled A and B
is a clock sensor located one character distance apart and used to read the clock range on card 100 in center track 110.

Sensor positions 126--marked 0.1, 2.3
132 is a data sensor used to sense areas of the data track representing individual characters.

FIG. 4 illustrates a logic diagram of the clock section of the card reader, and the clock section of FIG. 4 is included in the entire card reader of FIG. 5.

As mentioned above, the clock tracks on the credit card are located between the data tracks, with one discrete clock region for every other data character.

The clock track is sensed using an LED and a pair of sensing diodes named A and B sensors, the sensor being a third
They are located at positions 122 and 124 in the figure.

The purpose of the logic device of FIG. 4 is to detect a change in clock state from A to B state or from B to A state;
This state change is used to control various functions of the card reader.

Generally, the first of these functions is to transfer data currently stored in data register 26, illustrated in FIG. 1a, to buffer storage 28 for storage.

Second, the data register 26 is cleared to store the new data recovered by the photodetector shown in block 16 of FIG.

The A, B clock sensors detect A light and B light, and their names describe when a change in light is detected in a discrete clock domain by the A or B sensor.

The states of the A and B sensors, designated CEL1- and CEL2-, are applied to a pair of NOR gates 150.152.

Another input to gate 150 is a timing signal LT1-, and an input to gate 152 is a second timing signal LBC derived from timing signal LT2- in a manner described below.
It is K-.

The outputs from the NOR gates 150, 152 are in addition to the first register 154, which is a master-slave type F-F and has separate control from the clock signal CK-, which is shown as an input to F-F154. It will be done.

Furthermore, F-F154 is the first clock register 154.
The CHIB- signal described with reference to FIG. 1a is used to clear the CHIB- signal.

The output from the first clock register 154 is also J
- is added to the second clock register, which is a master-slave type F-F.

F-F156 also receives clock signal CK+ and F- at appropriate times.
Receives CHIB- signal used to clear F156.

BACX+ signal from register 156 and register 154
The BACT+ signal from is used as an input to exclusive OR gate 160.

The output from exclusive 6R gate 160 is a DRES+ signal indicating that correct information is present in data register 26, which causes the information to enter buffer 28 in the manner described below.

In addition to generating the DRES+ signal, the clock logic of FIG. 4 also includes generating the LBCK- signal, which is used as one input to NOR gate 152.

In particular, the output from NOR gate 150, which is the LTA+ signal, is directly connected to J- as one input to master slave F-.
F162 and also J-
is applied to the second input of master/slave F-F 162.

DLTA+ output from F-F162 is NOR gate 16
6 and the second input of NOR gate 166.
The input is provided by timing signal LT2-.

NOR gate 166 inverted by inverter 168
The output from the signal L is applied to the NOR gate 152.
It is BCK-.

Therefore, it is clear that NOR gate 152 operates only when receiving the LBCK- signal to reset F-F 154 at the end of the LT2 time.

However, this setting means that if the A clock is generated at LT1 in the same scanning cycle, the B clock is generated at LT2.
This is done conditionally upon receipt of the DLTA+ signal which inhibits clock signal verification.

The main function of this part of the device is to detect and reject cards that do not have different transmissivity bands.

When this occurs, the A clock pulse sets F-F 162 and inhibits F-F 154 from switching to the B state.

FIG. 5 illustrates a complete logic diagram of a card league implementing the clock logic of FIG.

As seen in FIG. 5, the LEDs at positions 118 and 120 (shown in FIG. 3) are used to detect the edge of the card as it enters the slant and reaches the bottom.

In particular, LED 200 is controlled by a transistor 202 to apply current through LED 200 and bias resistor 204 .

The transistor is activated by a timing signal LT8-.

The edge of the card that has reached the bottom position is also LED 206,
Detected using transistor 208 and resistor 210, clock signal LT9- is applied to control transistor 208.

At appropriate times, light is sent from LEDs 200, 206 to complementary detection diodes 212, 214.

Diodes 212 and 214 are biased by current from the power supply through resistors 216 and 218.

The output of detector 212 is applied to NOR gate 220 which has timing pulse LT8- as a second input.

The output of NOR gate 220 is applied as an input to a second NOR gate 222 which receives input timing pulse LT8-, and the output of NOR gate 220.222 is applied to F-.
Applied as an input to F224.

F-F224 is a master/slave type for J-.
It includes a clock signal and a clear signal CHIB- as inputs.

The output of the detector 214 is applied via an inverter 226 as a first input of a NOR gate 228 which has a timing signal LT9- as a second input.

The output of NOR gate 228 is connected to the clock input and CHIB
- Master/slave F-F23 to J- including clear signal
0 as input.

C0UT- and CD1N- from F-F224,230
The output is NAND gate 2 to generate the PARK+ signal.
32 as an input.

The PARK+ signal is used to control the application of power to the LEDs used to read the coded data information track and the clock track.

In particular, the PARK+ signal is applied to transistor 234, the base of which is biased by a current through resistor 236.

The output of transistor 234 is sent to the base of transistor 242 from a voltage divider including resistors 238 and 240.

Transistor 242 applies power to a plurality of LEDs, represented by one LED 246, through resistor 1244.

There are actually six LEDs, making up the six diodes shown to be present in block 12.

These six diodes are located at locations 122-13 in FIG. 3 to read the data and clock tracks.
It occupies 2.

One diode 246 is shown to represent the remaining diodes, and the circuit is similar for all diodes.

Power application to the diodes is controlled by a clock signal LT1° 2.4, 5.6, and 7, which is shown applied to a plurality of transistors located within block 248.

Output information representing data information and clock information of various information tracks on the credit card is provided by detector 250-2.
Detected by a corresponding detector denoted by 60.

The outputs of these detectors are applied to a plurality of amplifiers illustrated in block 22.

The outputs of the amplifiers in block 22 are six signals, four of which represent data information, and one inverter 2.
applied to a plurality of inverters represented by 62;
Two of the signals are the A and B clock signals and are applied separately to inverters 264 and 266, respectively.

The remainder of the clock logic is shown in FIG. 4 and will not be repeated here.

Data information from Impark 262 is applied to NOR gate 268, which represents the four NOR gates, and
The second input to the gate is the timing signal XLT4,5.6 and 7 which is derived from the timing signal LT4.5.6 and 7.

The output from inverter 268 is applied to J-, representing the four FFs, as the first input to master-slave FF 270, and the DRES+ signal from the clock logic is applied to J-, representing the four FFs.
-Added as a second manpower to the F270.

A clock signal and a CHIB- signal are also applied to F-F 270.

The output from F-F is N, representing four NAND gates.
AND gate 272 and the CHIB- signal is applied to the NA
Applied as the second input of ND gate 272.

The output of NAND gate 272 is applied to OR gate 274, which represents four 6R gates.

The second input of the ORgenicht 274 is a pushbutton input from the keyboard that bypasses automatic reading of the card and allows manual entry of information.

The outputs from all 6R gates 274 are applied to be stored in buffer 28 as data inputs.

The CHIB- signal described above is generated from a pair of signals C0UT+ and CHBX+ applied to NOR gate 278.

The output from NOR gate 278 is applied to an AND gate 280 having various inhibit signals as second inputs to generate the CHIB- signal.

Timing signals XLT4-XLT7 are generated from a plurality of AND gates 282-288.

AND gates 282-288 receive as inputs timing signals LT4-LT7 and output signal RDO from F-F 290.
Has K+.

The input of F-F290 is the reset signal LTO+ and NAND
The output signal from gate 292 is 5ROK+.

The input of NAND gate 292 is a pair of NAND gates 2
This is the output from 94°296.

The inputs of the NAND gates 292 and 294 are the BACT+ and BACT- signals and the clock signals LTB+ and LTA+.

FIG. 6 illustrates a timing diagram for the card reader of FIG. 5 and illustrates the generation of the various signals noted in FIGS. 4 and 5 to aid in understanding the operation of the device.

First, assuming there is no card in the reader, the card read logic is initiated by a low signal CHIB- when the card reader is inhibited from reading cards.

Insert the card into the reader.

There are various conditions that prevent card swiping that are not directly related to this device, but generally they occur when the terminal is disconnected from the line, when there is a significant amount of calls from other terminals, when the terminal is selected, etc. Occurs when writing previously requested information or when there is a special erase signal generated from the rest of the communications network.

All of these signals are provided as one input to gate 280 which forces signal CHIB- low.

Assuming the device is not inhibited from reading cards for the reasons discussed above, the CHIB- signal goes high when the C0UT+ signal goes low.

The C0UT+ signal goes low when the upper card edge detector senses a card entering the reader.

The card edge is sensed by a pair of diodes 200, 212, illustrated in FIG. 5, forming the card edge detector.

When the CHIB- signal is low, two F-Fl 5
4. Clear 156.

These F-Fs, illustrated in FIGS. 4 and 5, are connected as a 2-bit serial input shift register and are used to detect the state of the signals used to time the playback of data characters from the card. Ru.

When the C0UT+ signal goes low, this causes the PARK+ signal shown in FIG. 6 to go high.

The PARK+ signal is used to pulse all the LEDs to sense the coded information on the card and is therefore the first
Contains all diodes shown in block 12 of Figure a.

As illustrated in FIG. 1b, each of the LEDs is pulsed only during specific time slots that form part of the total scan cycle.

As mentioned above, the CHIB- signal initially clears clock registers 154, 156 low.

This is equivalent to the A state because it is the state in which the registers respond to the A clock sensor, which senses the presence of a clock domain on the card's clock track.

When the leading edge of the card enters the reader, as shown in FIG. clock sensor B and position 130
, 132 are covered by the leading edge of the card.

After the C0UT- signal activates the LED and sensor, position 1
Data sensors O and 1 at 26 and 128 detect light pulses before they are covered by the edge of the card.

The A clock sensor shown at location 132 normally detects the light pulse before it is covered by the card.

To ensure that this does not disturb the information in the data register, the data register is preset with a specific code 1011 by the CHIB- signal.

The data sensor locations, particularly locations O and 1, are chosen so that even if a light pulse is detected before it is covered by the card edge, it will not change the current information in the data register.

This is because data sensors 0 and 1 correspond to portions of the preset code that are already in position 1, so receiving light will not change this preset code.

As the card continues to slide into the reader slot, the B clock sensor detects the first clock range.

At this time, the data sensor detects the data pulse,
RD of the output of F-F 290 to gate the sense amplifier output from inverter 262 to data register 270 by timing signals XLT4, 5.6 and 7.
Since the OK signal will not go positive, the data pulse will be ignored.

The output of the B clock sensor will be F- at the end of LT2T2 time.
Set F154.

This setting is conditional on the DLTA+ signal.

The DLTA+ signal is A at time LT1 of the same scan cycle.
When a clock is generated, checking of the LT2T2 time clock signal is prohibited.

The main function of the DLTA+ signal is to detect cards that are transparent to the emission-detection pair.

This DLTA+ signal also ensures that there is a minimum of one scan cycle between changes from the A state to the B state.

This is also true for the change from B to A state, but this occurs because the B clock is sampled after the A clock.

When the BACT+ signal from F-F154 becomes positive, DR
The ES+ signal becomes positive.

This DRES+ signal is a data reset signal that is generated whenever a transition from the B state to the A state or vice versa is detected.

The DRES+ signal is connected to the BACT+ signal and BACX as inputs.
is the output signal from exclusive OR gate 160 with a + signal.

F-F156, which generates the BACX+ signal, is connected to F-F154 as a shift register, so the BAC
The X+ signal goes positive at the next clock transition.

The DRES+ signal is therefore a positive pulse of one hour spindle length (104 μs) that occurs in the time slot following the detection of a clock transition.

The DRES+ signal is used to transfer the contents of data register 270 to buffer storage 28, which transfer occurs in portions throughout the time slot.

Data register 27 on the falling edge of the DRES+ signal.
0 is cleared.

Upon detection of the 1B clock signal, the preset card read code placed in the data register by the CHIB- signal is transferred from the data register to buffer storage 28.

The data register is cleared and the read signal RDOK activates sampling of the photosensitive output to read the first data character from the card.

When data information is detected by the sensor, the corresponding bit in the data register is set.

[detected] pulse sets a bit so that small variations in the detection threshold do not cause problems.

At the normal speed of card movement through the slot, several pulses are generated by each clock and data area.

This is particularly the case for clock tracks, since two clock pulses must be detected for each clock cycle.

However, at typical card speeds, several pulses are detected for each area of the card representing data and clock signals.

Upon detection of the A clock signal in the LT1 time slot, signal BACT+ goes low.

The F-Fs 154 and 156 that generate signals BACT+ and BACX+ are in different states, and the generated DRES+ signal is generated during the B clock to gate the data characters assembled during the previous scan cycle and The data characters are gated to buffer storage 28.

As mentioned above, the data registers have been cleared.

The alternating cycle from A clock detection to B clock detection to A clock detection, etc. continues until all 11 characters have been read from the card and stored in the buffer.

Completion of the read process is accomplished by a positive logic level signal CDIN+ generated when the leading edge of the card intercepts LED 206, which together with detector 214 forms the bottom sensor.

This sensor determines when the bottom of the card reader slot is reached.

The method and apparatus of the coating system of the present invention provides decoding of information on a recording medium, such as a credit card, so that this information can be reliably read by a card league.

A pair of clock sensors to provide clock signals generated by the use of clock tracks containing one clock signal for every other data character and alternate detection between the A and B clock sensors. This increases the reliability of the device and can provide simple self-timing for the data characters on the card.

During playback, the card oscillates as it moves, but this generally does not affect the reading of the data characters since the alternate detection of the clock prevents false readings.

Additionally, problems caused by the transition time from no light to light state are also overcome because the actual reading of the data information does not take place until the other clock signal is generated.

Also, the actual reading is performed at a specific point in the scan cycle, and such reading is performed many times for each clock and data signal.

This ensures proper reading of the data character even if the first reading is incorrect.

Furthermore, this eliminates the problem of false reads since all data characters do not have to be read at the same time, and each bit of a data character is read many times in series, providing high reliability on the final read cycle.

Although the invention has been described with reference to specific embodiments, it will be appreciated that various adaptations and modifications may be made and the invention is limited only by the scope of the appended claims.

[Brief explanation of drawings]

FIG. 1a is a functional block diagram of the card reading logic, FIG. 1b is a timing diagram, and FIG. 1c is a standard time slot. FIG. 2 illustrates an optically encoded credit card implementing the coating system of the present invention. FIG. 3 schematically illustrates the card reader and shows sensor locations for correctly reading the information on the card of FIG. 2. FIG. FIG. 4 illustrates a diagram of the logic of the clock section of the playback device. FIG. 5 illustrates the logic diagram of the entire card reader. FIG. 6 illustrates a timing diagram of the card reader and clock portion of FIGS. 4 and 5. FIG. 10...Card reader slot, 12.14...Light emitting diode group, 16.18...Photodetector group, 20...
Card presence detector, 22...Amplifier, 24...Clock logic, 26...Data register, 28...Buffer, 100...Credit card, 104...Encoding area, 110...Clock track, 106,108,
112, 114...Data track, 102...Card reader.

Claims (1)

Claims: 1. A recording medium having first and second tracks, the first track being recorded at a series of regularly spaced bit positions along the first track. and the second track has a series of clock bits recorded along the second track, one clock bet being every nth data bit (where n is an integer greater than 1). an apparatus for reproducing information from said recording medium having said clock bits corresponding to said clock bits, said at least one data bit detector for reproducing data information of said first track; at least a pair of clock bit detectors spaced apart by interval bit positions;
said clock bit detector for successively reproducing clock information along a track of said clock bit detector, said recording medium and said data bit and clock a device for allowing relative movement between bit detectors in the direction of the first and second tracks; a data storage device;
In response to the data bit detector and the pair of clock bit detectors, data information recovered by the data bit detector is recorded in the data storage device in response to clock information recovered by one of the clock bit detectors. and a control device for reproducing the stored data information from the data storage device in accordance with clock information reproduced by the other of the clock bit detectors. Device.