JPH0321021A - Method and apparatus for chamfering semiconductor substrate - Google Patents

Method and apparatus for chamfering semiconductor substrate

Info

Publication number
JPH0321021A
JPH0321021A JP15602489A JP15602489A JPH0321021A JP H0321021 A JPH0321021 A JP H0321021A JP 15602489 A JP15602489 A JP 15602489A JP 15602489 A JP15602489 A JP 15602489A JP H0321021 A JPH0321021 A JP H0321021A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
grinding
rotating shaft
fixed
grindstone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15602489A
Other languages
Japanese (ja)
Inventor
Katsuaki Nishiyama
西山 勝章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KYUSHU ELECTRON METAL CO Ltd
Osaka Titanium Co Ltd
Original Assignee
KYUSHU ELECTRON METAL CO Ltd
Osaka Titanium Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KYUSHU ELECTRON METAL CO Ltd, Osaka Titanium Co Ltd filed Critical KYUSHU ELECTRON METAL CO Ltd
Priority to JP15602489A priority Critical patent/JPH0321021A/en
Publication of JPH0321021A publication Critical patent/JPH0321021A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To perform mirror-level chamfering in a short time by a method wherein a semiconductor substrate is fixed on a rotating shaft while a disc coarse particle grinding stone, a fine particle grinding stone and abrasive of expanded plastic are fixed on a rotating shaft facing the substrate, and both rotating shafts are rotated to sequentially grind outer peripheral parts of the substrate. CONSTITUTION:A sliced semiconductor A is fixed on a rotating shaft (b) while facing the semiconductor substrate A, a coarse particle grinding stone 3, a fine particle grinding stone 3 and abrasive 4 made of expanded plastic each of which is disc-shaped are fixed on a rotating shaft 1, and while both rotating shafts (b), 1 are rotated to sequentially grind outer peripheral parts of the semiconductor substrate A. That is, by first grinding, edges are treated with a diameter and orientation flat positioning accuracy given, and by second grinding, coarseness on chamfered parts of the semiconductor substrate A are reduced. Then a distorting layer on the surface is removed by the abrasive 4 to further reduce surface coarseness. Thus the semiconductor substrate A can be subjected to mirror-level chamfering effectively.

Description

【発明の詳細な説明】 (産業上の利用分野) 本願発明は、半導体製造工程において単結晶半導体棒を
スライスして得られる半導体基板の面取り方法及びその
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method and apparatus for chamfering a semiconductor substrate obtained by slicing a single crystal semiconductor rod in a semiconductor manufacturing process.

(従来の技術) 面取り加工における半導体基板の加工部位は、端面及び
上下両面の外周縁部であって、一般に第4図に示すよう
に、ダイヤモンドFを固定した砥石Eを用いた研削加工
が施される。具体的には、半導体基板Aは、加工部位を
除く上下両面はクランプB,Bによって固定されたり、
或いは片面を吸着具(図示せず)によって真空吸着によ
り固定され、この固定状態下で半導体基板A及び砥石E
を回転せしめ、研削液を加工部分に供給しながら両者A
,Eを押接して研削加工を行っている。
(Prior art) The parts to be processed on a semiconductor substrate during chamfering are the end face and the outer periphery of both upper and lower surfaces, and as shown in FIG. be done. Specifically, the semiconductor substrate A is fixed on both upper and lower surfaces except for the processing area by clamps B,
Alternatively, one side is fixed by vacuum suction using a suction tool (not shown), and in this fixed state, the semiconductor substrate A and the grinding wheel E are
and both A while supplying grinding fluid to the machining part.
, E are pressed and grinding is performed.

〈発明が解決しようとする課題) ところで半導体基板の端部は、取扱い時の衝撃が多くて
パーティクルの発生源となり易い部分である。従って、
上記研削加工された面(加工面)は、粗さの小さな均一
な加工面であることが要求される。
<Problems to be Solved by the Invention> Incidentally, the edge portion of a semiconductor substrate is a portion that receives a lot of impact during handling and is likely to become a source of particles. Therefore,
The ground surface (processed surface) is required to be a uniform processed surface with small roughness.

殊に、近年デバイスでの高集積化に伴い、パーティクル
の抑制は以前に増して重要な問題となっており、その結
果、今日では面取り部の表面は鏡面状態に近い均一さ(
粗度:  0.1gm以下)が望まれている。
In particular, with the recent increase in device integration, particle suppression has become more important than ever, and as a result, the surfaces of chamfered parts today have a uniformity close to that of a mirror surface (
Roughness: 0.1 gm or less) is desired.

しかし、上記従来の固定砥粒による1段階の研削方式で
は、安定して鏡面レベルの表面粗度を得るのは困難であ
る。すなわち、研削方式による場合は、ダイヤモンド砥
石の粒径が半導体基板の表面粗度と比例する関係にある
ため、その表面に鏡面仕上げを行うには平均粒径が27
bm以下の砥石を必要とする。しかし、この粒径の砥石
では、砥石径のばらつきや砥石の目づまり等に起因して
安定した粗度な保つことが困難となる。そこで、粒径が
2pm以下の砥石を用いるには、その前処理として複数
の前加工を必要とする。ところが、研削加工を複数段に
分割する場合には、各研削段階の装置の軸精度、ブレや
振動精度を各研削段階のみならず全研削段階を通じて保
全しなければならず、更に一連の研削の総所要時間が長
時間化してしまう不都合がある。
However, with the conventional one-stage grinding method using fixed abrasive grains, it is difficult to stably obtain surface roughness on a mirror level. In other words, when using the grinding method, the grain size of the diamond grinding wheel is proportional to the surface roughness of the semiconductor substrate, so to achieve a mirror finish on the surface, the average grain size must be 27.
Requires a whetstone of BM or less. However, with a grindstone having this particle size, it is difficult to maintain stable roughness due to variations in the grindstone diameter and clogging of the grindstone. Therefore, in order to use a grindstone with a grain size of 2 pm or less, a plurality of pre-processing processes are required. However, when the grinding process is divided into multiple stages, it is necessary to maintain the axis accuracy, runout, and vibration accuracy of the equipment for each grinding stage not only at each grinding stage but also throughout the entire grinding stage. There is an inconvenience that the total time required becomes long.

本願発明は、上記実情下において半導体基板に効率的に
鏡面レベルの面取りを施し得る方法及び装置を提案する
ものである。
The present invention proposes a method and apparatus capable of efficiently chamfering a semiconductor substrate to a mirror surface level under the above-mentioned circumstances.

(課題を解決するための手段) すなわち本発明は、前段加工により均一な面状態を得て
局部的な凹凸を除去し、これにより仕上げ加工に支障の
ない表面粗度を短時間に得ること及び、仕上げ加工によ
り表面粗度を0.1gm以下の均一な面状態に短時間で
且つ簡易に行えるようにしたものである。
(Means for Solving the Problems) That is, the present invention aims to obtain a uniform surface condition through pre-processing, remove local irregularities, and thereby obtain a surface roughness that does not hinder finishing processing in a short time. , it is possible to achieve a uniform surface condition with a surface roughness of 0.1 gm or less by finishing processing in a short time and easily.

上記目的を達或するため、本発明は、前段加工を固定砥
粒によるものとし、仕上げ加工はメカノケくカル方式と
なし、両者を結合して半導体基板の面取りを行う点に特
徴を有する。具体的には、本発明は、スライスされた半
導体を回転軸に固定する一方、前記半導体基板に対峙さ
せて各々円板状の粗粒砥石、細粒砥石及び発泡樹脂製の
研磨材を回転軸に固定し、前記両方の回転軸を回転させ
つつ順次、前記半導体基板の外周縁郁を研削加工及び研
磨する半導体基板の面取り方法と、スライスざれた半導
体基板を回転軸に固定してなる半導体基板の回転機構と
、各々円板状の粗粒砥石、細粒砥石及び発泡樹脂製の研
磨材を回転軸に固定してなる研削研磨機構とを備え、前
記両機構において、前記半導体基板と前記砥石及び研磨
材とが、左右及び上下方向に相対的に接離移動可能に設
けられている半導体基板の面取り装置にある。
In order to achieve the above object, the present invention is characterized in that the preliminary processing is performed using fixed abrasive grains, the finishing processing is performed using a mechanical method, and the two are combined to chamfer the semiconductor substrate. Specifically, in the present invention, a sliced semiconductor is fixed to a rotating shaft, and a disk-shaped coarse-grained grindstone, a fine-grained grindstone, and an abrasive material made of foamed resin are respectively mounted on the rotating shaft so as to face the semiconductor substrate. A method for chamfering a semiconductor substrate in which the outer peripheral edge of the semiconductor substrate is sequentially ground and polished while rotating both rotating shafts, and a semiconductor substrate obtained by fixing the sliced semiconductor substrate to the rotating shaft. and a grinding and polishing mechanism each having a disc-shaped coarse-grained grindstone, a fine-grained grindstone, and an abrasive material made of foamed resin fixed to a rotating shaft, and in both of the mechanisms, the semiconductor substrate and the grindstone are connected to each other. and an abrasive material are provided in a semiconductor substrate chamfering device that is provided so as to be movable toward and away from each other in the horizontal and vertical directions.

(作 用) 譬上記粗粒砥石による研削で、基本的形状の付与が短時
間に為し得られる。具体的には該第1次研削加工によっ
て直径・オリエンテーションフラット位置精度が与えら
れエッジ処理がなされる。
(Function) By grinding with the above-mentioned coarse grain grindstone, a basic shape can be obtained in a short time. Specifically, the first grinding process provides diameter/orientation flat position accuracy and performs edge processing.

もっとも、この第1次研削加工は、粗粒砥石によるもの
であるため、局部的な凹凸や研削痕が残存することにな
る。また、研削加工表面の粗度も大きい。
However, since this primary grinding process is performed using a coarse-grained grindstone, local unevenness and grinding marks remain. Furthermore, the roughness of the ground surface is also large.

上記した局部的な凹凸や研削痕は、後述する研磨によっ
てもそのまま残ってしまう。そこで、後述する研磨を施
す前に、上記局部的な凹凸や研削痕を除去するため、細
粒砥石による研削・(第2次研削加工)を施す。この第
2次研削加工によって半導体基板の面取り部における表
面粗度が小さくなる。
The local unevenness and grinding marks described above remain even after polishing, which will be described later. Therefore, before performing the polishing described later, in order to remove the local irregularities and grinding marks, grinding (secondary grinding) using a fine-grained grindstone is performed. This secondary grinding reduces the surface roughness of the chamfered portion of the semiconductor substrate.

上記第2次研削加工は固定砥粒による研削であって、シ
リコンのような脆性材に対しては破壊研削となり、加工
(研削)表層部に破壊層や歪層(以下、「歪層」と総称
する〉が残留してしまう。この歪層の面内不均一は、以
後において単なる研磨を施した場合に、ピッ1〜となっ
て表われてくる。
The above-mentioned secondary grinding process is grinding using fixed abrasive grains, and for brittle materials such as silicon, it is destructive grinding. This in-plane non-uniformity of the strained layer will appear in the form of pips when simple polishing is performed thereafter.

したがって、上記第2次研削加工後の仕上げ加工では、
表面粗度を更に小さくすると同時に上記歪層を除去しな
ければならない。
Therefore, in the finishing process after the above-mentioned secondary grinding process,
The strained layer must be removed at the same time as the surface roughness is further reduced.

そこで、本発明では、第2次研削加工後、エッチング作
用を高めたメカノケくカル方式の研磨を採用する。
Therefore, in the present invention, after the second grinding process, mechanical polishing with enhanced etching effect is employed.

すなわち、発泡樹脂からなる研磨材の使用に際し、好ま
しくはPHIO以上のアルカリ性研磨液を併用し、エッ
チングによって上記歪層を除去し、研磨材によって表面
粗度を更に小さくし得る。
That is, when using an abrasive material made of a foamed resin, preferably an alkaline polishing liquid of PHIO or higher is used in combination, the strained layer is removed by etching, and the surface roughness can be further reduced by the abrasive material.

そして、本発明の構或に依れば、半導体の回転機構と研
削研磨機構の各々の回転軸の軸精度を確保し、ブレや振
動に対処すれば、これらの砥石及び研磨部材が所期の正
確な回転運動を行って、安定した研削・研磨が施せるの
であり、各々の回転軸の位置制御を正確にしておけば、
順次第1次研削加工、第2次研削加工、研磨加工が円滑
に行われる。
According to the structure of the present invention, if the axial accuracy of each rotating shaft of the semiconductor rotation mechanism and the grinding and polishing mechanism is ensured and shake and vibration are dealt with, these grindstones and polishing members can be used as intended. Stable grinding and polishing can be performed by performing accurate rotational movements, and if the position of each rotating axis is accurately controlled,
The primary grinding process, the secondary grinding process, and the polishing process are performed smoothly in this order.

(実施例) 以下、本発明を添付図面に基いて説明する。(Example) Hereinafter, the present invention will be explained based on the accompanying drawings.

第1図は本発明に係る面取り装置の要部を示す一部断面
図、第2図は本発明装置の概念構或図で、本発明は、ス
ライスされた半導体基板Aを回転軸bに固定してなる半
導体基板の回転機構10と、各々円板状の粗粒砥石2、
細粒砥石3及び発泡樹脂製の研磨材4を回転軸1に固定
してなる研削研磨機構11とを備え、前記両機構10.
11において、前記半導体基板Aと前記砥石2.3及び
研磨材4とが、左右及び上下方向に相対的に接離移動可
能に設けられている。ここで粗粒砥石2の平均粒径は2
0〜30pm.細粒砥石3の平均粒径は8〜10JLm
に設定されている。
FIG. 1 is a partial sectional view showing the main parts of a chamfering device according to the present invention, and FIG. 2 is a conceptual diagram of the device according to the present invention. a rotating mechanism 10 for a semiconductor substrate, each having a disk-shaped coarse grain grinding wheel 2;
A grinding and polishing mechanism 11 having a fine-grained grindstone 3 and an abrasive material 4 made of foamed resin fixed to a rotating shaft 1 is provided, and both mechanisms 10.
11, the semiconductor substrate A, the grindstone 2.3, and the abrasive material 4 are provided so as to be movable toward and away from each other in the horizontal and vertical directions. Here, the average grain size of coarse grain grinding wheel 2 is 2
0-30pm. The average grain size of the fine grain grindstone 3 is 8 to 10 JLm
is set to .

なお、Bは半導体基板Aを保持するクランプ、Cは粗粒
砥石2及び細粒砥石3を用いて加工する際に使用する研
削液、Dは研磨部材4を用いる際に使用する研磨液であ
る。
In addition, B is a clamp that holds the semiconductor substrate A, C is a grinding liquid used when processing using the coarse grain grindstone 2 and fine grain grindstone 3, and D is a polishing liquid used when using the polishing member 4. .

次に加工手順に従って説明する。Next, the processing procedure will be explained.

まず、半導体基板AをクランプBで上下よりクランプし
、研削液Cを一定量加工部分に供給しなから粗粒砥石2
を用いて半導体基板Aの外周部を研削する。次に半導体
基板A側(または粗粒砥石2側)を上下させて半導体基
板Aのエッジ部の研削を行う(第1次研削)。このとき
、半導体基板A側と粗粒砥石2側は一定速度で自転させ
、粗粒砥石2側より半導体基板A側に一定荷重をかける
。半導体基板Aの上記研削部分は断面形状でみると図に
示す(イ)に相当する。次に細粒砥石3を用いて研削を
行うが、加工方法は粗粒砥石2を用いたときと同様であ
る。この細粒砥石3による研削部分は(口)に相当する
(第2次研削)。最後に研磨部材4を用いた仕上げ研磨
を行う。研磨液Dを加工部分に供給しながら研磨郁材4
を半導体基板Aに一定加重で押しつける。このときにも
半導体基板A側及び研磨部材4側は各々自転させる。
First, the semiconductor substrate A is clamped from above and below with the clamps B, and a certain amount of grinding fluid C is supplied to the processing part, and then the coarse grain grinding wheel 2
The outer periphery of the semiconductor substrate A is ground using a grinder. Next, the semiconductor substrate A side (or the coarse grain grindstone 2 side) is moved up and down to grind the edge portion of the semiconductor substrate A (first grinding). At this time, the semiconductor substrate A side and the coarse grain grindstone 2 side are rotated at a constant speed, and a constant load is applied from the coarse grain grindstone 2 side to the semiconductor substrate A side. The above-mentioned ground portion of the semiconductor substrate A corresponds to (a) shown in the figure when viewed in cross-sectional shape. Next, grinding is performed using the fine-grained grindstone 3, but the processing method is the same as when the coarse-grained grindstone 2 is used. The part ground by this fine-grained grindstone 3 corresponds to (mouth) (secondary grinding). Finally, final polishing is performed using the polishing member 4. Polishing material 4 while supplying polishing liquid D to the processing part
is pressed against the semiconductor substrate A with a constant load. Also at this time, the semiconductor substrate A side and the polishing member 4 side are each rotated.

なお半導体基板A側(または、研磨郁材4側)は上下方
向に移動させず、外周部とエッジ部の双方を一度に研磨
する。研磨部材4による研磨部分は(ハ)に相当する。
Note that the semiconductor substrate A side (or the polishing material 4 side) is not moved in the vertical direction, but both the outer peripheral part and the edge part are polished at once. The polishing portion by the polishing member 4 corresponds to (c).

ところで、上記第1次研削加工、第2次研削加工、研磨
加工における砥石2,3及び研磨部材4にかかる負荷は
各々異なり、研削液C、研磨液Dの流量及び条件も異な
る。下記表は、この条件の一例を示す。なお、半導体基
板の直径と砥石2,3及び研磨部材4の直径の比率は1
 : 1.5である。
Incidentally, the loads applied to the grindstones 2 and 3 and the polishing member 4 in the first grinding, the second grinding, and the polishing are different, and the flow rates and conditions of the grinding liquid C and the polishing liquid D are also different. The table below shows an example of this condition. Note that the ratio of the diameter of the semiconductor substrate to the diameter of the grinding wheels 2, 3 and polishing member 4 is 1.
: 1.5.

(以下余白) 上記の如き方法によって面取り加工を行った場合、表面
粗さ計による表面状態測定結果(JIS BO601−
1982の規格に基く)では、最大高さ(Rmax)に
於て、面取り加工(第3図の符号5),60gmエッチ
ング(第3図の符号6)、0.1pmエッチング(第3
図の符号7)を施した後には、表面粗度は0. 1 g
.mより著しく小さな値となった。そして、表面のうね
りの高さは平均値0.41Lmであった。また、光学顕
微鏡による面取り部の全面スキャンでは、局部的な研削
痕跡(局部的溝)も認められなかった。更に上記品質的
向上の他に、固定砥粒による研削で、時折発生する目詰
まりによるチッピング及び、後工程での応力集中による
破損、チッピングも減少していたことを確認した。
(Left below) When chamfering is performed using the method described above, the surface condition measurement results using a surface roughness meter (JIS BO601-
1982 standard), at the maximum height (Rmax), chamfering (number 5 in Figure 3), 60gm etching (number 6 in Figure 3), and 0.1pm etching (number 3 in Figure 3).
After applying step 7) in the figure, the surface roughness is 0. 1 g
.. The value was significantly smaller than m. The average height of the surface waviness was 0.41 Lm. In addition, when the entire surface of the chamfered portion was scanned using an optical microscope, no local grinding traces (local grooves) were observed. Furthermore, in addition to the above-mentioned quality improvement, it was confirmed that grinding with fixed abrasive grains reduced chipping due to clogging that occasionally occurs, as well as damage and chipping due to stress concentration in post-processes.

(発明の効果) 以上説明したように、本発明に依れば、短時間に鏡面レ
ベルの面取りを行うことができ、また上記本発明装置に
依れば、軸精度や位置制御の作業が可及的に少なくて済
み、効率的な面取り操業が実施できる。
(Effects of the Invention) As explained above, according to the present invention, mirror-level chamfering can be performed in a short time, and according to the apparatus of the present invention, work on shaft accuracy and position control can be performed. Therefore, the chamfering operation can be carried out efficiently.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る面取り装置の要部を示す一都断面
図、第2図は本発明装置の概念構戒図、第3図は砥粒径
と表面粗度の関係を示すグラフ、第4図は従来装置例を
示す一部断面図である。
FIG. 1 is a cross-sectional view showing the main parts of the chamfering device according to the present invention, FIG. 2 is a conceptual diagram of the device of the present invention, and FIG. 3 is a graph showing the relationship between abrasive grain diameter and surface roughness. FIG. 4 is a partial sectional view showing an example of a conventional device.

Claims (2)

【特許請求の範囲】[Claims] (1)スライスされた半導体を回転軸に固定する一方、
前記半導体基板に対峙させて各々円板状の粗粒砥石、細
粒砥石及び発泡樹脂製の研磨材を回転軸に固定し、前記
両方の回転軸を回転させつつ順次、前記半導体基板の外
周縁部を研削加工及び研磨することを特徴とする半導体
基板の面取り方法。
(1) While fixing the sliced semiconductor to the rotating shaft,
A disk-shaped coarse-grained grindstone, a fine-grained grindstone, and an abrasive material made of foamed resin are respectively fixed to rotating shafts facing the semiconductor substrate, and while rotating both of the rotating shafts, the outer peripheral edge of the semiconductor substrate is sequentially polished. A method for chamfering a semiconductor substrate, the method comprising grinding and polishing a portion of the semiconductor substrate.
(2)スライスされた半導体基板を回転軸に固定してな
る半導体基板の回転機構と、各々円板状の粗粒砥石、細
粒砥石及び発泡樹脂製の研磨材を回転軸に固定してなる
研削研磨機構とを備え、前記両機構において、前記半導
体基板と前記砥石及び研磨材とが、左右及び上下方向に
相対的に接離移動可能に設けられていることを特徴とす
る半導体基板の面取り装置。
(2) A semiconductor substrate rotation mechanism in which a sliced semiconductor substrate is fixed to a rotating shaft, and a disc-shaped coarse-grained grindstone, a fine-grained grindstone, and an abrasive made of foamed resin are each fixed to the rotating shaft. a grinding and polishing mechanism, and in both of the mechanisms, the semiconductor substrate, the grindstone and the polishing material are provided so as to be movable toward and away from each other in the left and right and up and down directions. Device.
JP15602489A 1989-06-19 1989-06-19 Method and apparatus for chamfering semiconductor substrate Pending JPH0321021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15602489A JPH0321021A (en) 1989-06-19 1989-06-19 Method and apparatus for chamfering semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15602489A JPH0321021A (en) 1989-06-19 1989-06-19 Method and apparatus for chamfering semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH0321021A true JPH0321021A (en) 1991-01-29

Family

ID=15618649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15602489A Pending JPH0321021A (en) 1989-06-19 1989-06-19 Method and apparatus for chamfering semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH0321021A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6467674B1 (en) * 1999-12-09 2002-10-22 Casio Computer Co., Ltd. Method of manufacturing semiconductor device having sealing film on its surface
JP2006004955A (en) * 2003-05-30 2006-01-05 Ebara Corp Substrate processing apparatus and substrate processing method
JP2011211246A (en) * 2011-07-28 2011-10-20 Dainippon Screen Mfg Co Ltd Substrate treatment apparatus and substrate treatment method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6467674B1 (en) * 1999-12-09 2002-10-22 Casio Computer Co., Ltd. Method of manufacturing semiconductor device having sealing film on its surface
JP2006004955A (en) * 2003-05-30 2006-01-05 Ebara Corp Substrate processing apparatus and substrate processing method
JP2011211246A (en) * 2011-07-28 2011-10-20 Dainippon Screen Mfg Co Ltd Substrate treatment apparatus and substrate treatment method

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