JPH0320977B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flicker compensator connected in parallel with a load in a circuit having a flicker-generating load.

The circuit configuration of the conventional Fritzker compensator is shown in the first example.
As shown in the figure. 1a, 1b, 1c are phase advancing capacitors, 2a, 2b, 2c are series reactors, 3a,
3b, 3c, 4a, 4b, and 4c are thyristors connected in antiparallel to perform opening/closing control.

1a, 2a, 3a, 4a are No. 1 branches, and with the same configuration, 1b, 2b, 3b, 4b, 1c, 2
c, 3c, and 4c form the No. 2 and No. 3 shunts, and the capacity of each shunt is in the ratio of 1:2:4, and seven-stage control is performed by combining each shunt, and the control is based on the load. 7 is guided from a current transformer (CT) 6 to a current integrating circuit 10. A pulse signal is sent to the sampling circuit 11 from the potential transformer (PT) 5, the phase shift circuit 12, and the timing circuit 13, and the detection circuit 14
Selection circuit 1 for selecting input branch
A closing command is sent from 5, and the gate circuits 18a, 1
Receive at 8b, 18c. 10 is a current integration circuit. Synchronous detection circuits 16a, 16b, 16 that send out pulse signals when the thyristor terminal voltage is around 0V
The signals from c are also connected to the gate circuits 18a, 18b, 18
c and other overcurrent detection circuits 17a, 17b,
A signal is sent from the gate circuit only when the logical product of the signals 17c is established, and the gate amplifiers 19a and 1
The thyristors 9b and 19c are triggered to flow each phase leading current to compensate for the voltage drop.

Next, the operation of the conventional example will be explained with reference to FIG.

Assuming that there is no response delay in the control section, the charging voltage of capacitors 1a, 1b, and 1c is -√2E(V)
becomes. At this time, the detection circuit 14 sends a closing signal to the selection circuit 15 due to the load current (in the figure), but the No. 1 branch is ON
do.

Also, when the load current increases at the middle point in the figure and the input signal switches from the No. 1 branch to the No. 2 branch, the No.
Branch 1 turns OFF, but branch No. 2 turns ON with a half-cycle delay due to the polarity of the SC charging voltage. This resulted in no SC current for half a cycle, which had the disadvantage of generating a break.

When the load current turns off at the middle point in the diagram, the SC current also
Since it can be turned off, the voltage fluctuation will have two voltage drops.

In this way, SC
There is a response delay when turning on due to the polarity of the charging voltage,
Furthermore, depending on the polarity of charging, it is possible to eliminate response delay, but it has the disadvantage that a break occurs when switching the shunt.

This is because the appropriate capacity is selected after detecting the load current, and a closing command is sent to each shunt, but the closing command is switched without determining the closing status of other shunts at the time of switching, which causes a disconnection. It is.

For this reason, even if the response delay was reduced, the flicker reduction effect did not improve much due to the occurrence of breaks.

In order to eliminate the drawback of the current break that occurs when switching the closing shunt in the dual thyristor system, the present invention determines whether or not the shunt can be turned on after switching when switching the closing shunt before proceeding to the next stage. The purpose of the present invention is to provide a flicker compensating device which eliminates the drawback of occurrence of a cut and is highly effective in improving flicker by switching the input signal.

Below, the Fritzker compensator of the present invention is shown in Figs.
This will be explained using the embodiment shown in FIG.

Figure 3 is a circuit diagram of the Fritzker compensator.
1a, 2a, 3a are phase advance capacitors, 2a, 2
b, 2c are series reactors, 3a, 3b, 3c,
4a, 4b, and 4c are thyristors connected in antiparallel.

Furthermore, in order to prevent a transient phenomenon from occurring when the capacitor is turned on, the synchronous detection circuits 16a and 16 generate a pulse signal when the voltage across the thyristor is around 0V.
b, 16c are each thyristor 3a, 4a, 3b, 4
b, 3c, and 4c, respectively.

These 1a, 2a, 3a, and 4a are designated as No. 1 branch,
With the same configuration, there are 2 other branches 1b, 2b, 3b,
4b, 1c, 2c, 3c, 4c, each No. 2
Branch, No. 3 branch. Each capacity is 1:2:4
Seven levels of capacity can be obtained by combining each shunt.

Current transformer (CT) 6 controls the current of load 7 as a control unit.
The voltage is detected by the current integrating circuit 10 and the sampling circuit 11 converts it into a DC voltage. Also, a potential transformer (PT) 5, a phase shift circuit 12, and a timing circuit 1
3 to the sampling circuit 11 causes the detection circuit 14 to hold the detected value, and the selection circuit 15 selects the input branch and sends out a signal, which is sent to the determination circuits 20a, 20b, and 20c. The determination circuits 20a, 20b, and 20c receive signals from the synchronization detection circuits 16a, 16b, and 16c other than the shunts, and determine whether or not the other shunts can be turned on when switching the closing stage. Judgment circuits 20a, 20b,
A closing signal is sent from 20c to the gate circuits 18a, 18b, 18c, and the synchronization detection circuit 16 of the branch
Signals from a, 16b, 16c are also sent to the gate circuit 18
a, 18b, and 18c. Further, signals from overcurrent detection circuits 17a, 17b, and 17c are also sent to gate circuits 18a, 18b, and 18c.

In the gate circuits 18a, 18b, 18c, when the logical product of the input signal, the signals of the synchronization detection circuits 16a, 16b, 16c, etc. is established, the gate amplifier 19
a, 19b, and 19c as a closing signal to trigger the thyristor.

Next, a specific circuit example of the No. 1 branch judgment circuit 20a will be explained with reference to FIG.

The input signal of No. 1 branch is the first OR gate 21
and the trigger input side of the monostable multivibrator 22, respectively. All input signals other than the No. 1 branch are input to the second OR gate 23.

Further, the input signal of the No. 2 branch and the synchronization signal D2 are input to the second AND gate 24a.

Further, the input signal of the No. 3 branch and the synchronization signal D3 are input to the third AND gate 24b.

The outputs of the second and third AND gates 24a and 24b are input to the third OR gate 25, and the output of the OR gate 25 is input to the monostable multivibrator 2.
Connected to the second reset terminal.

In addition, the output of the second OR gate 23 and the output of the monostable multivibrator 22 are input to the first AND gate 26, and the output is input to the first OR gate 26.
1, and the output of the first OR gate 21 becomes the output of the determination circuit 20a.

Note that the same function can be achieved by using a flip-flop instead of the monostable multivibrator 22.

In Figure 4, S1 is the input signal for No. 1 branch, and S2 is
No. 2 input signal, S3 is No. 3 branch input signal, D
2 is the synchronization signal of the No. 2 branch, the synchronization signal of the No. 3 branch,
SS1 is the output signal in FIG.

. . . are lines on which the waveforms shown as A, B, C, . . . , H, respectively, in FIG. 5, which will be described later, appear.

Next, the principle of operation will be explained with reference to FIG.

For example, when the input signal S1 of the No. 1 branch turns from ON to OFF as shown in FIG. 5A and switches to the input signal S2 of the No. 2 branch, the monostable multivibrator 22 is triggered, As shown in Figure 5F, the output is switched from LOW to HIGH, and the first AND
input to gate 26; At this time, the input signal S2 of the No. 2 branch is HIGH as shown in FIG. 5B, and is input from the second OR gate 23 to the first AND gate 26, so the first AND The logical AND is established in the gate 26, and the output switches to HIGH as shown in Fig. 5G and is input to the first OR gate 21, so the output of No. 1 branch continues to be the input signal as shown in Fig. 5H. However, the capacitor current ic ₁ in the No. 1 branch in FIG. 5a is also applied to the dotted line.

The capacitor charging voltage Vc ₂ of the No. 2 branch is shown in Fig. 5b.
In the case of a negative value as shown in FIG. .2 branch is in a state where input is not possible.

Therefore, when the synchronization signal is output after the next half cycle, the second AND gate 24a is activated as shown in FIG.
An AND is established between the input signal S2 and the synchronization signal D2 as shown in FIG. 5D, and the output becomes HIGH as shown in FIG. As shown in Figure 5G, the first AND gate 26 becomes LOW.
The input signal of the No. 1 branch becomes LOW as shown in Fig. 5H, and the No. 1 branch turns OFF.

At this time, in the No. 2 branch, the AND gate of the input signal and the synchronization signal is established, and the No. 2 branch is turned ON.

As a result, the current IC ₁ in the No. 1 branch was able to be energized for an extra half cycle, so the current IC 1 in the No. 1 branch was transferred from the No. 1 branch to the No. 2 branch.
The current ic ₂ in the shunt is passed without interruption, resulting in a composite current (ic ₁ +ic ₂ ) in FIG. 5d.

As described above, the determination circuit for the No. 1 branch has been described, but the No. 2 and No. 3 branches have the same configuration and operate in the same manner. In this case, each section in FIG. 4 receives the input signal of its own branch, and the synchronization signal receives the signal of the other branch.

This causes the switch from No. 1 branch to No. 2 branch, and similarly from No. 1 branch to No. 3 branch, from No. 2 branch to No. 1 branch, and from No. 2 branch to No. 1 branch. It can also operate from the shunt to the No. 3 shunt, etc.

Incidentally, although anti-parallel thyristors are used in the opening/closing section, a triax or the like having an equivalent function can also be used.

As described above, with the present invention, even if there are many loads and welding machines whose capacity changes frequently during load energization, and the capacity changes rapidly due to various overlapping currents during energization, each shunt current can be smoothly switched. On the other hand, it has a high effect of improving frizziness and is of great industrial and practical value.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a conventional flicker compensator, FIG. 2 is a waveform diagram of each part of the conventional flicker compensator, FIG. 3 is a block diagram of an embodiment of the flicker compensator of the present invention, and FIG. The figure is a logic gate circuit diagram of the flicker compensator of the present invention, and FIG. 5 is a waveform diagram of each part of the flicker compensator of the present invention. 1a, 1b, 1c: phase advance capacitor, 2a,
2b, 2c: Series reactor, 3a, 3b, 3
c, 4a, 4b, 4c: thyristor, 15: selection circuit, 16a, 16b, 16c: synchronization detection circuit,
18a, 18b, 18c: gate circuit, 20a,
20b, 20c: Judgment circuit, 21: First OR gate, 22: Monostable multivibrator, 23:
Second OR gate, 24a: Second AND gate,
24b: third AND gate, 25: third OR gate, 26: first AND gate.

Claims (1)

[Claims] 1. A plurality of groups of shunts each consisting of a phase advance capacitor, a series reactor, and a semiconductor switch are provided in parallel with the load, and the voltage across both terminals of each semiconductor switch is
There is a synchronous detection circuit that generates a pulse signal near 0V, a selection circuit that detects the load capacity, selects the closing shunt, and sends out the closing signal, and a selection circuit that detects the load capacity and selects the closing shunt and sends out the closing signal. In addition to receiving it from the synchronization detection circuit, when the input branch is converted from one branch to another, it is determined to continue to hold the input signal of one branch until the synchronization pulse of the other branch is generated. and a gate circuit that receives signals from the determination circuit and the synchronization detection circuit and sends a gate signal to the semiconductor switch, wherein the determination circuit receives an input signal of the first shunt. a monostable multivibrator to which the closing signal is triggered and operates only when the closing signal is OFF, and a second OR gate to which the closing signals of the other shunts are input.
an OR gate, a first AND gate that inputs the output signal of the second OR gate and the output signal of the monostable multivibrator, and inputs the logical product thereof to the first OR gate; The outputs of the second and third AND gates are input to the second and third AND gates into which the input signal of the third branch and the synchronization signal generated when the branch can be closed are input, and the AND gate is A flicker compensator comprising a third OR gate that inputs the signal to the reset terminal of the monostable multi-channel, and seamlessly controls the current during shunt switching.