JPS5951238B2 - Control device for anti-parallel connected thyristor converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for anti-parallel connected thyristor converters using a non-circulating current method, and in particular to a control device for anti-parallel connected thyristor converters that can perform forward/reverse switching safely and in a short time. Regarding equipment.

5. Non-circulating current type anti-parallel connected thyristor converters are widely used as stationary Leonard devices for operating DC motors, cycloconverters for operating AC motors, and in general DC power supplies.

In this case, it has always been an important issue to perform switching control between the positive side thyristor converter and the reverse side thyristor converter safely and in a short time in order to improve the reliability and performance of the above device.

That is, for example, if a command to energize the reverse side converter is received while the positive side converter is energized, if the power supply to the positive side converter is stopped and the gate pulse is given to the reverse side converter without eliminating the gate pulse, the positive side converter will be turned on. A power supply short circuit (so-called anti-parallel short circuit) occurs through the inverter.

Also, when the converter is operating as an inverter, the current (
If the gate pulse is cut off before the current reaches zero (including zero), there is a great risk that commutation will fail and a short-circuit current will flow. on the other hand,
If the switching time is increased in order to safely perform forward/reverse switching, the switching time acts as dead time on the control system, deteriorating the stability and control accuracy of the control system.

Furthermore, when anti-parallel connected thyristor converters are used in a cycloconverter device, a long switching time will have significant negative effects such as a decrease in the output capacity of the converter and a decrease in the upper limit frequency. As described above, in the control device for anti-parallel connected thyristor converters using the non-circulating current method, the positive side converter and the opposite side converter are used. Switching control between side transducers has a significant impact on equipment safety and performance.

However, as described below, conventional control devices are not necessarily satisfactory in terms of switching time and safety, and improvements have been awaited.

Below is Figure 1. A conventional example will be explained using FIG. FIG. 1 is a block diagram showing a conventional example in which anti-parallel connected thyristor converters are used as a stationary Leonard device for driving a DC motor, and FIG. 2 is an operational diagram for explaining the forward/reverse switching operation. In Figure 1, 9,1 is the positive side converter of the anti-parallel connected thyristor converter, 92 is the reverse side converter,
11 is a DC motor operated by a converter; 8 is a connection terminal to an AC power source; 1 has, for example, a speed control device, a current control device, etc., and commands the firing phase of the thyristor to the phase shifter 2;
An automatic control device that gives a forward/reverse switching command to the non-circulating current switching control circuit 5, 3 and 4 are a positive side pulse amplifier and a reverse side that apply pulses to the gates of the thyristors of the positive side converter 91 and the reverse side converter 92, respectively. The pulse amplifier 6 is a current zero detector which receives a signal from a current detector 7 for detecting the current of the converter and produces an output when the current falls below an extremely small set point. Here, at the time of TO in FIG. 2, the forward/reverse switching command 51 given from the lodging control device 1 to the non-circulating current switching control circuit 5 changes from the positive side (level 1 in the diagram) to the reverse side (level o in the diagram). Suppose that it changes to

The automatic control device 1 controls the positive side output current Ip of the positive side converter 91 and makes it smaller in the ith order. T when the positive side output current Ip reaches the setting level Iref or less of the current zero detector 6,
A zero current signal 56 is issued at the point in time (level 1 in the figure)
. At this time T, the positive side output current Ip of the positive side converter 91
Since is not completely zero yet, the positive side converter 91 continues.
Turn on the gate and start phase tailing of the gate pulse (phase tailing release command 52 → level 0
). Then, the time Td until the positive side output current Ip becomes completely zero has elapsed. At the point of time, the positive converter 9
Turn off gate 1 (positive side gate on command 53 → level 0). After that, a predetermined time Td corresponding to the turn-off time of the thyristor element. T passed. Turn on the gate of the reverse side converter 92 at the point in time (reverse side gate on command 5
4→Level 1) and cancels the phase shift that was carried out after detecting zero current. As is known from the above explanation of the operation using FIG.
, and when the gate of the reverse converter 92 is turned on, T.

Since it is released in the following way, it has the following disadvantages. That is,
T. Even if the forward/reverse switching command 51 is issued at the point in time, the phase of the gate pulse is not forcibly narrowed down immediately, so the time (T. to T) until zero current is detected becomes longer. In addition, even after the converter is stopped, phase throttling is continued (T, ~T in FIG. 2). Since the phase throttling is canceled at the time, the rise of the current after the gate of the reverse side converter 92 is turned on becomes slow (slow).
An object of the present invention is to provide a control device for anti-parallel connected thyristor converters in which the switching time of the converters is short.

In the present invention, the phase of the gate pulse is immediately started from the moment a forward/reverse switching command is issued, and the gate pulse of the converter is extinguished after a predetermined period of time has elapsed after the detection of zero current (including almost zero). The phase throttling is canceled at the same time as the gate pulse disappears or after a predetermined period of time has passed, and the gate of the opposite converter is energized after a further predetermined period of time has elapsed.

Also, if the energization command after the disappearance of the gate pulse is to the converter on the opposite side to the side that was energized up to then, the configuration is as described above, and the energization command is directed to the converter on the side that was energized until then. By configuring the system to immediately activate the gate pulse of the converter that was energized and release the phase throttling at the same time, wasteful control operations can be avoided when the energization command returns. can be prevented. The present invention will be explained below based on specific examples. FIG. 3 is a diagram showing one embodiment of the present invention, and is a schematic diagram of a control device that controls anti-parallel connected thyristor converters based on a current pattern and supplies current to a load.

In FIG. 3, 21 is a current control device that controls the current by comparing the current pattern applied from the input terminal 20 and the load current that is the output of the amplifier 22, 2 is a phase shifter that adjusts the phase of the gate pulse, 3 and 4 are positive side converters 9
1 and a positive side pulse amplifier and a reverse side pulse amplifier that apply pulses to the gates of the thyristors of the reverse side converter 92;
8 is an AC power supply terminal, 110 is the load of the converter, 7] and 72 are current detectors that detect the currents of the positive side converter 91 and the reverse side converter 92, respectively; An energization command circuit that generates an energization command WP to the side converter 91 and an energization command WN to the opposite side converter,
A specific example is shown in a part of FIG. 5, which will be described later, and is well known.

61 and 62 are current zero detectors for the positive side converter and the reverse side converter (as mentioned above, it is a detector that detects a relatively small current that is almost impossible to detect a complete current zero)
, 50 is a non-circulating current switching control circuit and a forward/reverse energization command W.
P and WN and forward and reverse current zero detection signals ZP and Z
This circuit receives N as an input and creates a gate pulse distribution signal to the forward/inverse converters 91 and 92 as well as a forced gate pulse phase narrowing signal.

The non-circulating current switching control circuit 50 receives the energization command WP and the zero current detection signal ZP, and receives the outputs of the NOR gates A1 and NOR gates A2, which receive the outputs of A1, and outputs the outputs for a first predetermined time (T2tl). Timer A3, A1 and A
3 and a NAND gate A4 which receives the output of the positive side conversion circuit 91, and which becomes the level O when the first predetermined time has elapsed after the detection of zero current of the positive side conversion circuit 91 (hereinafter, the circuit composed of these A1 to A4 will be referred to as a logic circuit). A), a NOR gate Bl, a NOT circuit B2, a first predetermined time period (T2
-t1) timer B3 that outputs only t1), NAND gate B4
A logic circuit that becomes level O when a first predetermined period of time has elapsed after the detection of zero current in the reverse side converter 92 (hereinafter, the circuit composed of these B1 to B4 will be referred to as logic circuit B).
, timers C and D whose output level becomes 0 for a second predetermined time (T3-T2) after the output level of logic circuit A or B becomes O, NAND gate E1, and NOT circuit E.
2, which becomes level 1 when both the output of logic circuit A and the output of timer D are level 1 and the gate pulse of reverse converter 92 is not energized (hereinafter referred to as these logic circuits). The circuit composed of E1 and E2 is called a logic circuit E), and like the logic circuit E, it is composed of a NAND gate F1 and a not circuit F2, and the output of the logic circuit B and the output of the timer C are both at the level] A logic circuit that becomes level 1 when the gate pulse of the positive side converter 91 is not energized (hereinafter referred to as F1 and F1).
(referred to as logic circuit F), not circuit G1:G4, NOR gate G2, G5, OR gate G3
A logic circuit that outputs a phase throttling signal of the gate pulse of the thyristor converter after the energization command WP or WN becomes level 0 until the output of the logic circuit A or B corresponding to the energization command becomes level 0 ( Below these G1~G
5 is called a logic circuit G). Note that the phase throttling signal of the gate pulse does not become level O at the same time as the output level 0 of logic circuit A or B, but is extended by 1,000 seconds for a second predetermined time (T3-T2) determined by the timer C or D. (However, before T3), the level can be set to 0. In other words, it is sufficient if the phase throttling is released before the on-command for the opposite gate is issued. The above non-circulating current switching control circuit 5
The operation of 0 will be explained using the signal waveform diagram in FIG.

Let us take as an example a case where the current pattern signal 20 changes from the positive side to the negative side as shown in the figure.

When the polarity of the current pattern changes at the time of TO, the energization command WP on the positive side is switched to level 0, and the energization command WN on the opposite side is switched to level 1. At this time, the positive side converter 91 has a current Ip
is flowing, and the output signal ZP of the zero current detector 61 is at level 1. Therefore, the output signal of NOR gate A1 continues to be at level 0, and the output of NAND gate A is also at level 1.
I'm keeping it. On the other hand, the output of timer D, which is composed of a negative edge trigger monomulti (inverse output terminal, is normally level 1, when the input changes from 1 to o, the level becomes o, and after a predetermined time determined by the circuit constant of the mono multi) has elapsed. Since the output of the NAND gate F1 is at level 1, the output of the NAND gate E also remains at level 0, so the NOT circuit E. The output continues to be level 1, and the gate pulse amplifier 3 continues to energize the positive side converter 91. On the other hand, the output of the NOT circuit G1 is at level 0 since the output of the gate A4 is at level 1. Therefore, when the positive side energization command WP becomes level 0, the NOR gate G is activated. The output of changes from level o to level 1. Therefore, from this point TO, the output of the OR gate G3 becomes level 1, and a command to reduce the phase of the gate pulse is forcibly given to the phase shifter 2. Since the phase of the gate pulse is forcibly narrowed, the current Ip of the positive side converter 91 rapidly decreases, and at the time T when the current Ip reaches the comparison level of the current zero detector 61, the output signal ZP of the detector 61 decreases. The level changes from 1 to 0. Therefore, the output level of NOR gate A changes from 0 to 1, and the output level of inverter A2 changes from 1 to 0. For this reason, the output level of timer A (the output terminal is an inverse terminal) composed of a negative edge triggered monomulti switch changes from ] to 0. Therefore, the output of NAND gate A continues to be level 1, and the status of the subsequent gates remains unchanged.
The positive converter 91 continues to be energized in the gate shift state. Timer A. Setting time (first setting time)
T reached. A at the time of. The output level of NAND gate A returns to 1, and therefore the output level of NAND gate A changes from 1 to o. Therefore, the output level of NAND gate E1 is 1,
Also, inverter E. The output level becomes 0, and application of the gate pulse to the positive side converter 91 is stopped. Also, since the output level of the NOT circuit G becomes 1, the NOR gate G2
The output level is 0, orage=toG. The output level of
The phase squeezer is also this T. will be canceled at the same time. In addition, this T. At the point in time, the output level of NAND gate A changes from 1 to o, so the output level of timer C (the output terminal is an inverse terminal) composed of a negative edge trigger monomultiplier changes from 1 to o. On the other hand, the reverse side energization command WN is T.

The output level of NAND gate B1 is 0, and the output level of NAND gate B4 is 1.
It's getting old. However, T. Until the point in time, the output level of NAND gate E is 0, and T. The output level of timer C is o from to the set time T3 of timer C.
Therefore, the output level of the NAND gate F, continues to be 1, and the output level of the NOT circuit F2 is 0, the gate of the reverse converter 92 is not energized, and the gate pulses of both converters are stopped. be. Then, when the output level of timer C returns to 1, all input signal levels of NAND gate F1 become 1, and its output level becomes 0. Therefore, the knot circuit F. The output becomes 1, the gate pulse amplifier 4 gives a gate pulse to the reverse converter 92, and the reverse converter 92 starts energizing. IN indicates the current of the reverse converter 92. In this embodiment, the forward/reverse converter is switched as described above. Note that in the non-circulating current switching control circuit 50, the logic elements B, ~B are the logic elements A, ~A. and logic elements G,,G. are logic elements G,,G. The operation is the same as that described above even when switching to the positive side converter while the reverse side converter is energized, so the explanation will be omitted. As described above, according to this embodiment, since the phase of the gate pulse is forcibly reduced immediately after the energization command changes, the converter current can be rapidly reduced, and the forward/reverse switching time can therefore be significantly shortened. can.

In addition, since the gate pulse throttling command is released before the gate pulse energization of the converter, the phase shifter 2 gives the firing phase according to the on-off power command to the gate pulse or amplifier, and the converter Since it is immediately energized by the gate pulse, there is no delay in the rise of the energizing current, and the current is energized quickly. This has the same effect as shortening the forward/reverse switching time. Furthermore, according to the non-circulating current switching control circuit of the above embodiment, T in the signal waveform diagram of FIG.

~T. If the energization command for the side that has been energized is given again while the gate pulses of both converters are stopped, the gates of the converters can be started immediately (that is, without waiting until time T). That is, since the outputs of timers C and D each have the effect of delaying the gates on the other side, the converters on the same side can be restarted immediately. This has the effect of improving control performance because, for example, when it is necessary to control a load current near zero, the dead time of the control operation is reduced. In addition,
A logic circuit G is added to a conventional control device having the operating characteristics shown in Fig. 2, a forward/reverse switching command 51 is input to G2, and the same forward/reverse switching command 51 is reversed by a knot circuit and a circuit is input to G5. By inputting gate-on commands 53 and 54 to Gl and G4, respectively, phase throttling is performed at the same time as the energization command, and phase throttling is performed at the same time as the gate pulse of the converter on the side that was energized is turned off. It can be canceled.

Even in this case, the release of the phase throttling can be extended by a few thousand seconds using a timer or the like (until before T3).
In the above embodiment, two sets of current detectors were provided to detect zero current on the positive side and negative side, but this is different from the one set on the load side as shown in another embodiment in Fig. 5 described later. A pair of current detectors may be used, or a current detector (not shown) may be provided on the AC power source side.

In this case, if the polarity of the current flowing through the current detector is unknown (for example, when detecting the converter current on the terminal 8 side of the AC power supply), use the polarity of the current pattern, or The polarity of the energizing current can be easily identified by using a gate distribution signal or the like. That is, the positive side and load current zero signals ZP and ZN can be easily created without using two sets of current detectors as shown in FIG. Here, when two sets of current detectors are provided as in the embodiment shown in FIG. It is possible to recover in stages.

In other words, when an anti-parallel short circuit occurs due to erroneous ignition due to noise, the current zero signals ZP, ZN
are both level 1, and the output level of AND gate H1 is 1. Therefore, the output level of the positive edge triggered monomulti H2 (the output terminal is the normal terminal) becomes 1 for a predetermined time, and a gate pulse phase reduction command is forcibly issued to the phase shifter 2 via the OR gate G3, thereby reducing the short-circuit current to zero. do. The time of the monomulti H2 is set so that the current is completely zero and the thyristor maintains the output level for a sufficient period of time to recover its reverse blocking capability. In this way, by using the current zero signal of the forward/reverse converter, a minor anti-parallel short circuit can be automatically recovered, and a situation where the situation progresses to a serious anti-parallel short circuit and stops the operation of the entire device can be avoided. can. In addition, the third
The logic circuit in the non-circulating current switching control circuit 50 in the illustrated embodiment is an example for explaining the main operation of the present invention.
It goes without saying that various modifications of the logic circuit are possible.

In addition, in the logic circuit shown in FIG. 3, when using elements with relatively large variations in the operation time of the logic elements, for example, between the logic elements A1 (B1) and A4 (B4) 501 (501
03) and between logic elements A4 (B4) and E1 (F1) 5
02 (504) etc. (for example, a first-order delay consisting of a resistor and a capacitor, or inserting two stages of knot circuit elements in series) to coordinate the operation of the logic circuit. Therefore, I will only describe the above-mentioned extent here. FIG. 5 is another embodiment of the present invention, which is a block diagram of a control device for operating an AC motor using anti-parallel connected thyristor converters.

Portions in FIG. 5 labeled with the same symbols as in FIG. 3 are the same as in FIG. 3, and therefore their explanation will be omitted.

AC motor 111 (U) such as an induction motor or a synchronous motor
, V, W (N is the neutral point) are 901 to 901 based on the AC waveform pattern and current value standard 27 of the automatic control device 26, which generates a three-phase current pattern according to the operating state of the motor.
It is driven by a control device 903. Protsuku 902-90
3 is similar to 901, so the internal details have been omitted. To explain the inside of the U-phase block 901, the current control device 2
1 uses a signal obtained by multiplying the output of an absolute value circuit 23 that creates the absolute value of a waveform pattern by a current value reference 27 that commands the magnitude of the current by a multiplier 24 as an input reference, and a load current detector 7
The absolute value of the zero detection signal is determined by the absolute value circuit 25 and compared as a feedback signal to adjust the gate pulse phase of the thyristor converter and thereby control the load current. The non-circulating current switching control circuit 50 receives the positive energization command WP and the reverse energization command WN from the energization command circuit 10, as well as the output signal ZP of the positive current zero detector 61 and the output signal ZN of the reverse current zero detector 62. As described above, forward/reverse switching control is performed as an input signal. The energization command generation circuit 10 is configured as follows, so it can start/stop the converter and power/stop the motor.
Braking operation can be switched smoothly.

That is, the AC waveform pattern, the start/stop signal 28, and the power running/braking command 29 are used as input signals, and the signal 2 at the time of starting is
If the level of 8 is set to 1, the output level of the NOT circuit 15 is 0, and the outputs of the NOR gates 17 and 18 are alternately 1 and 0 depending on the output level of the exclusive OR gate 14.
and changes. Here, the level of the power running/braking command 29 is 1.
In the power running state, the output level of the exclusive OR gate 14 changes to level 0 in cycles where the waveform pattern is positive and to level 1 in cycles where the waveform pattern is negative, depending on the signal from the polarity detector 13 of the AC waveform pattern. Therefore, the positive side energization command is at level 1 when the waveform pattern is positive, and at level 0 when the waveform pattern is negative, and the polarity of the waveform pattern and the operation of the energization command match. On the other hand, power running/braking signal 2
9. When the level is set to 0 and a braking command is given, contrary to the above,
When the waveform pattern is positive, the level of the reverse energization command is 1, and when the waveform pattern is negative, the level of the positive energization command is 1, and the polarity of the waveform pattern and the operation of the energization command are opposite. Therefore, the motor current will be in reverse phase, resulting in braking operation. Next, when the level of the start/stop command signal 28 is set to 0 and a stop command is given, the Noah gates 17 and 18
The output levels of both become zero, and based on this, the non-circulating current switching control circuit 50 changes the phase j of the gate pulse of the converter.
(As described above using Figures 3 and 4, phase throttling is forcibly started when the energization command changes to zero.) After the energizing current is reduced to zero, the gate pulse of the converter stops. be done. As described above, when the non-circulating current J switching control circuit shown in FIG. 3 is used, if the energization command circuit 10 shown in FIG. 5 is used as the energization command signal, the converter will start - Switching between stopping and power braking can be easily and smoothly performed.

In addition, when using a bipolar signal whose polarity is changed according to power running and braking as the current value reference 27, as shown in FIG. 6, a polarity discriminator 30 is provided to discriminate the polarity of the current reference value 27. It is easy to create the power running/braking command 29. On the other hand, as shown in FIG. 5, the energization command circuit 10 is configured so that the levels of the forward energization command and the reverse energization command are never set to 1 at the same time. If countermeasures are taken within the non-circulating current switching control circuit to prevent gate pulse energization commands from being issued to both converters at the same time even if they are input at the same time, it is safe to avoid an anti-parallel short circuit accident.

Furthermore, in this case, if you prevent the gate pulse energization on the side that has not been energized and continue to apply the gate pulse energization on the side that has been energized without stopping, commutation failure can be prevented. It is safer because it does not cause any problems. In FIG. 3, the non-circulating current switching control circuit 50 has a circuit configuration that takes measures to prevent anti-parallel short circuits and commutation failures as described above.

In other words, as shown in the figure, the NAND gates E1 and E1, which are the gates for the energization/stop command of the gate pulse of the forward/reverse converter, each use the output of the other side as one of their input conditions, so the forward/reverse energization commands WP and A state in which WN is at level 1 at the same time exists in NAND gates A and B. Even if the output levels of both are 1, for example, if the output level of NAND gate E is 0 and the gate pulse of the positive converter is energized, then NAND gate F and output of NAND gate E Since F is one of the inputs, its output level is 1, and therefore, the output of inverter F is 0, and gate pulse application to the opposite converter is prevented, thereby preventing an anti-parallel short circuit. Furthermore, since the gate pulse of the converter that is energized continues to be connected, commutation failure does not occur and it is safe. A summary of the control operation of the control device of the present invention and its effects will be described below in comparison with a conventional control device.

FIG. 7A shows operating waveforms of a conventional control device, and FIG. 7B shows operating waveforms of a control device according to the present invention. Now, consider a case where the same current pattern signal 20 is given.

Time T when the current pattern signal 20 switches from positive to negative.
The forward/reverse switching command Wp switches from the ``1'' level to the ``0'' level.This point is the same in the conventional case (FIG. 7A), and the forward/reverse switching command 51 changes from ``l'' to the ``0'' level. However, in the case of the present invention, the forward/reverse switching command WP (
7)T. At time , the output signal of OR gate G (
The phase squeeze release command) is set to ``1'' and a forced gate shift (phase squeeze) command is generated.As a result, the positive side output current 1p starts to decrease as shown in FIG. 7B. On the other hand, in the conventional method (FIG. 7A), phase narrowing is started at time t1.In this way, the positive side output current 1p is adjusted to the current zero detection level Iref (ideally zero, but , which is actually a finite value), the current zero detection signal Zp is output, but since the positive current 1p decreases faster as described above, the current zero detection time t1 First, in this respect, it is possible to shorten the switching control time (TO-T3).Next, after the current zero detection time t1, the positive side current 1p becomes completely zero at time T2. As mentioned earlier, since the positive side current 1p decreases quickly, it reaches zero earlier than in the conventional case.

On the other hand, in the conventional case, the reduction rate of the positive current 1p changes depending on the reduction rate and magnitude of the current pattern signal 20, so the time Tdl (t1 ~T2) is longer than that of the present invention.
Therefore, in this respect as well, the switching control time (TO-
T3) can be shortened. Next, during the time Td2 from time T2 to T3, after the thyristor of the positive side converter 91 has completely recovered its blocking ability, the thyristor of the reverse side converter 92 is turned on to reverse the inversion between the forward and reverse side converters. Since the time is for preventing a parallel short circuit, it is required to be longer than the turn-off time of the thyristor, and therefore, there is no difference between the conventional method and the present invention in this respect.

Next, regarding the release of phase throttling, conventionally, at time T3
However, in the present invention, this is performed at time T2, which is before time T3 when the thyristor of the reverse side converter 92 becomes ON.

Phase throttling, that is, gate shift, means to maximize the output voltage of the thyristor on the negative side.If the conventional time T3 remains unchanged, the rise of the negative side current 1N is delayed, but in the case of the present invention, the rise of the negative side current 1N is delayed from time T3. It is clear that the rise is earlier because the phase throttling is canceled in advance (at time T2). This state is shown in FIG. FIG. 8A shows the output current waveform when using the conventional control device, and FIG. 8B shows the output current waveform when using the control device of the present invention. I can see that it's on. As explained in detail above, the present invention starts the phase throttling of the gate pulse immediately from the time when the forward/reverse switching command is issued, continues to throttle the phase until a predetermined time after detecting zero current, and after the predetermined time elapses. At this point, the phase throttling is canceled at the same time as the gate pulse of the converter is extinguished or after a predetermined time has elapsed, and then the gate of the converter on the opposite side is energized after a predetermined time has elapsed. Therefore, it is possible to shorten the forward/reverse switching time and improve the rise of the current after switching, thereby making it possible to obtain a control device for anti-parallel connected thyristor converters with significantly improved control performance.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional control device, Fig. 2 is a signal waveform diagram for explaining the operation of the conventional device, Fig. 3 is a block diagram showing an embodiment of the control device of the present invention, and Fig. 4 is the above-mentioned block diagram. A signal waveform diagram for explaining the operation of the embodiment; FIG. 5 is a block diagram showing another embodiment of the present invention for controlling an AC motor;
FIG. 6 is a plotter diagram showing a part of the embodiment device of FIG. 5 provided with a polarity discriminator, FIG. 7A is a control operation waveform diagram of a conventional control device, and B is a control diagram of a control device according to the present invention. FIG. 8A is an output current waveform diagram of a converter produced by a conventional control device, and FIG. 8B is an output current waveform diagram of a converter produced by a control device according to the present invention. 2... Phase shifter, 3, 4... Pulse amplifier, 10...
- Energization command circuit, 50... non-circulating current switching control circuit,
61, 62... Current zero detector, 71, 72... Current detector, Al, Bl, G2, G5... Noah gate, A
2, B2, G], G4, E2, F2...not circuit,
A3, B3, C, D, H2...timer, A4, B4
, El, Fl... NAND gate, G3... OR gate, H1... AND gate, WP, WN... Energization command, ZP, ZN... Zero current detection signal.

Claims (1)

[Scope of Claims] 1. A positive-side converter that causes current to flow in a predetermined direction through the load in response to an energization command, and a reverse side converter that is connected in antiparallel to this and causes current to flow in the opposite direction to the load in accordance with the energization command. In the thyristor converter, which is composed of a circuit that issues the energization command of the thyristor converter, a circuit that detects zero energization current of the thyristor converter, and an output current after the energization command is switched and the energization current is detected to be almost zero. When the time has elapsed for the thyristor converter to become completely zero, the gate pulse of the converter on the previously energized side is turned off, and when the turn-off time of the thyristor converter has elapsed, the gate pulse of the converter on the opposite side is turned off. A current switching control circuit that turns on the pulse, starts phase narrowing of the converter gate pulse at the same time as the energization command is switched, and simultaneously turns off the gate pulse of the converter that was energized until then, or 1. A control device for anti-parallel connected thyristor converters, comprising means for releasing phase throttling after the pulse is turned off and before the gate pulse of the opposite converter is turned on. 2 Consists of a positive side converter that causes current to flow in a predetermined direction to the load in accordance with the energization command, and a reverse side converter that is connected in antiparallel to this and causes current to flow in the opposite direction to the load in accordance with the energization command. In a thyristor converter, there is a circuit that issues the energization command of the thyristor converter, a circuit that detects zero energization current of the thyristor converter, and a circuit that detects the energization current is almost zero after the energization command is switched, and then the output current becomes completely zero. When the time has elapsed, the gate pulse of the converter that was energized until then is turned off, and the energization command after this gate pulse is turned off is directed to the converter that was energized until then. If this happens, immediately turn on the gate pulse of the converter on the side that was energized until then, and if it is to the converter on the opposite side from the side that was energized until then, turn on the gate pulse of the converter on the side that was energized until then. means for turning on the gate pulse of the opposite converter when the turn-off time of the thyristor converter has elapsed since the turn-off of the gate pulse of the converter; and simultaneously starting the phase reduction of the gate pulse of the converter at the same time as switching the energization command; When the gate pulse of the converter on the side that has been energized is turned on by the above means, at the same time it is turned on, and when the gate pulse of the converter on the side opposite to the side that was energized until then is turned on, the gate pulse is turned on. means for releasing the phase throttling at the same time as the gate pulse of the converter on the side that was energized until then is turned off, or after the gate pulse is turned off and before the gate pulse of the converter on the opposite side is turned on; A control device for an anti-parallel connected thyristor converter, characterized by comprising: