JPS6251076B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thyristor conversion device, and more particularly to a gate stop method for a high voltage thyristor conversion device.

High-voltage thyristor converters used for DC power transmission are often used in a cascade connection for large-capacity power transmission. FIG. 1 shows an example of a general two-group cascade-connected thyristor conversion device.

In Figure 1, the thyristor conversion devices are A and B.
It consists of two groups. In the figure. Code 1~
4 is a thyristor valve (hereinafter simply referred to as a valve) consisting of multiple thyristors connected in series.
U to Z indicate bridge-connected thyristor converters, respectively. Reference numerals 5 to 8 indicate bypass switches connected across each DC output end side of each thyristor converter 1 to 4. The bypass switches 5 to 8 are used when stopping either group A or B due to a change in power transmission capacity or the like. For example, when both groups A and B are in operation, when group A is stopped and the power transmission capacity is halved,
The bypass switches 5 and 7 are turned on to short-circuit the DC output terminals of the thyristor converters 1 and 3 of group A, thereby putting the thyristor converters 1 and 3 into bypass operation. or,
Bypass switches 5 to 7 are also used when the thyristor converters in each group fail and stop. Code 9,
10 is a DC reactor.

FIG. 2 is a block diagram of a gate control circuit for controlling the firing of a thyristor converter. FIG. 3 shows a time chart of each signal. It should be noted that FIG. 2 shows a circuit for the U phase among the U, V, and W phases, and since the other phases have completely similar configurations, their explanations will be omitted to simplify the explanation.

In FIG. 2, reference numeral 11 indicates a flip-flop circuit. A start signal U _ON , which determines the start of the conduction period of the U-phase thyristor valve, is input to the input of the flip-flop circuit 11 as a set signal. The reset signal is an end signal U _OF which determines the end of the conduction period of the U-phase thyristor valve.
_F and a gate block signal GB used to stop the thyristor valve are inputted via an OR circuit 22. The flip-flop circuit 11 outputs a conduction period signal a. This conduction period signal a includes the 120° period during normal operation and the thyristor conversion devices 1 to 4.
Contains the bypass pair period when starting and stopping.

Reference numeral 13 indicates a valve voltage detection circuit for detecting the voltage applied to the U-phase valve 12. This valve voltage detection circuit 13
It outputs a forward voltage signal FV when a forward voltage is applied to it, and outputs a reverse voltage signal RV when a reverse voltage is applied to it. These forward and reverse voltage signals FV and RV are sent to the gate control circuit. Also, the forward voltage signal FV becomes “LOW” corresponding to the sum of the forward voltage drops of the valve.
level, and the reverse voltage signal RV is sent as a "High" level.

Reference numeral 14 indicates a flip-flop circuit. The flip-flop circuit 14 receives the conduction period signal a output from the flip-flop circuit 11 as a set input. By the way, if the reverse voltage period δ after the end of the conduction period signal a is not _greater than the margin angle δ of the thyristor, commutation may fail. Therefore, if the reverse voltage period δ is smaller than the margin angle δ ₀ , it is necessary to continue the conduction period and issue a gate pulse to restart the firing. Therefore, an AND circuit 15 is provided to detect the reverse voltage after the end of the conduction period signal a, and its output is input to the margin angle period determination circuit 16. This margin angle period determination circuit 16 has a reverse voltage period δ of δ ₀ or more (δ>δ ₀ ).
When the signal c is output, the flip-flop circuit 1
The output signal d of 4 is reset. When the reverse voltage period δ is less than δ ₀ (δ<δ ₀ ), the signal c is not output, the flip-flop circuit 14 is not reset, and the output signal d of the flip-flop circuit 14 continues.

Reference numeral 17 indicates an AND circuit. This AND circuit 17 inputs the output signal d of the flip-flop circuit 14 and the forward voltage signal FV of the detection signal of the valve voltage detection circuit 13, and outputs an output signal e when both the signals d and FV are at the "High" level. The output signal e is sent to a pulse circuit 18 and a narrow gate pulse for firing the thyristor is sent to the valve 12.
is applied to each thyristor.

Now, when two groups A and B are in operation, the case where the group to be stopped is set to bypass pair operation and then any of bypass switches 5 to 8 is turned on will be explained with reference to the time chart in Fig. 3. .

In FIG. 3, A and B show the valve voltage waveforms of the U valve and the X valve when the bypass switch is turned on during the bypass pair operation in which the U and X phases are stopped. C is a bypass switch turn-on signal. After the bypass switch is turned on, phase voltage is applied to each valve in the stop group. However, the output signal of the gate control circuit (output signal of the flip-flop circuit 14)
d continues because it is not reset until a signal of a reverse voltage period with a margin angle _δ0 or more is applied. Further, even when the phase voltage of the valve is applied, the signal e is generated from the AND circuit 17 and the gate pulse f is outputted from the pulse circuit 18 at the time when the forward voltage is applied. A reverse voltage is applied to the X bulb until a forward voltage is applied to the U bulb 12 and it is ignited, but the reverse voltage period δ is shorter than the margin angle _δ0 . For this reason, a reverse voltage of a margin angle δ ₀ or more is not applied to either of the UX valves, and the gate pulse continues to be generated.

Generally, a predetermined detection level is set for forward voltage and reverse voltage detection by the valve voltage detection circuit 13, so that the forward voltage signal FV and the reverse voltage signal RV
Depending on the mutual level difference between the two, the reverse voltage may not be detected after the bypass switch is turned on.
In addition, if the gate pulse is continuously output as described above and the valve operation cannot be stopped, the gate power supply will gradually decrease in a circuit where the gate current is generated by the valve like this circuit. Problems also occur.

Therefore, the present invention solves the above-mentioned conventional drawbacks,
An object of the present invention is to provide a gate stop method that can stop a gate pulse without damaging a valve.

The present invention will be described in detail below based on illustrated embodiments. FIG. 4 is a block diagram showing an embodiment of a gate control circuit using the gate stop method according to the present invention. The parts in FIG. 4 that are different from those in FIG. 3 are the parts surrounded by broken lines. Since the other parts are the same, they will be given the same reference numbers and the explanation will be omitted.

The AND circuit 19 receives the bypass switch input signal c, the stop signal g of the U valve 12, and the forward voltage signal FV of the valve 12. The valve stop signal g is a gate block signal that stops the valve 12.
When GB is output, it is a continuous signal until the next start signal U _ON is output. The output signal h of the AND circuit 19 is input to the timer circuit 20. The timer circuit 20 outputs the signal i of the on period Td in response to the rise of the pulse of the signal h. Note that this timer circuit 20 does not receive the input signal h while outputting the signal i during the on period Td. The signal i is input to the pulse circuit 21, and the pulse circuit 21 outputs a signal j having a pulse width Tz at the falling edge of the signal i, that is, at the rise time Td of the first pulse of the signal h.

The AND circuit 22 uses the gate pulse f outputted from the pulse circuit 18 and the signal j as input signals, and locks the gate pulse f during the output period of the signal j to prohibit the output of the gate pulse k to the valve 12.

When the bypass switch is turned on and the gate block signal GB, which is a stop signal for the valve 12, is output, the conduction period signal a of the valve 12 ends;
Since the valve 12 may have insufficient margin angle,
It is not possible to immediately reset the flip-flop circuit 14 and stop the gate pulse k. However, after the gate block signal GB, the forward voltage signal
If FV is detected, it can be determined as follows. That is, (1) commutation failure has not occurred because voltage is applied to the valve 12, or (2) the gate pulse k when the first forward voltage signal FV is generated after the gate block signal GB. Either actually served as a protection against commutation failure of the valve 12, or.

Therefore, after the gate block, at least 1
Delay Td for a certain period of time after the forward voltage signal is detected, and then
Gate pulse k pulse with a cycle margin
By locking P ₁ only once (singular) (only once instead of all pulses after Td), valve 12
If no commutation failure has occurred within valve 12
A phase voltage is applied to . Therefore, a reverse voltage is applied for a period of _δ0 or more, and the output signal d of the flip-flop circuit 14 is reset.

On the other hand, after locking _P1 of gate pulse k, if valve 12 has failed commutation, _P2 of gate pulse k is output again to re-ignite valve 12, so protection can be achieved. .

In the above embodiments, it has been explained that the number of gate pulses is locked at one or several times, but the gate pulse k may also be locked for a predetermined period of time corresponding to the number of pulses.

As described above, according to the present invention, the gate pulse can be reliably stopped without damaging the valve with a simple circuit configuration. It is possible to prevent problems such as a decrease in performance. Additionally, after one or more gate pulses are locked, the gate pulse circuit is reactivated, providing complete valve protection against all mains circuit conditions.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the general configuration of a thyristor conversion device connected in two groups in cascade, Fig. 2 is a block diagram showing a conventional gate control circuit, and Fig. 3 shows the operation of Figs. 1 and 2. FIG. 4 is a block diagram of a gate control circuit using the gate stop method according to the present invention, and FIG.
It is a time chart showing the operation of the figure. 1-4...Thyristor conversion device, 5-8...Bypass switch, 11...Flip-flop circuit, 12...Valve, 13...Valve voltage detection circuit, 14...Flip-flop circuit, 15...AND circuit, 16... ...Margin angle period determination circuit, 17...
...AND circuit, 18...pulse circuit, 19...AND circuit, 20...timer, 21...pulse circuit, 22...AND circuit, 23...OR circuit.

Claims (1)

[Scope of Claims] 1. A thyristor valve composed of a plurality of thyristors connected in series or in series and parallel, and a bypass switch connected between its DC output terminals;
In a thyristor conversion device comprising a firing control circuit for controlling firing of each of the thyristors, the bypass switch input signal, the gate block signal of the thyristor conversion device, and when a forward voltage is applied to the thyristor, Stopping the thyristor conversion device by locking one or more gate pulses output from the ignition control circuit or for a predetermined time after a predetermined time has passed after a logical sum condition with the generated signal is satisfied. A gate stop method for a thyristor conversion device characterized by: