JPH0311177B2 - - Google Patents

Info

Publication number
JPH0311177B2
JPH0311177B2 JP58194549A JP19454983A JPH0311177B2 JP H0311177 B2 JPH0311177 B2 JP H0311177B2 JP 58194549 A JP58194549 A JP 58194549A JP 19454983 A JP19454983 A JP 19454983A JP H0311177 B2 JPH0311177 B2 JP H0311177B2
Authority
JP
Japan
Prior art keywords
circuit
branch
shunts
signal
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58194549A
Other languages
Japanese (ja)
Other versions
JPS6087628A (en
Inventor
Kenji Morisada
Kazuyuki Doi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichikon KK
Original Assignee
Nichikon KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichikon KK filed Critical Nichikon KK
Priority to JP58194549A priority Critical patent/JPS6087628A/en
Publication of JPS6087628A publication Critical patent/JPS6087628A/en
Publication of JPH0311177B2 publication Critical patent/JPH0311177B2/ja
Granted legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/30Reactive power compensation

Landscapes

  • Supply And Distribution Of Alternating Current (AREA)
  • Control Of Electrical Variables (AREA)

Description

【発明の詳細な説明】 本発明はフリツカー発生負荷を有する回路にお
いて、負荷と並列に接続したフリツカー補償装置
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flicker compensator connected in parallel with a load in a circuit having a flicker-generating load.

従来例のフリツカー補償装置の回路構成を第1
図に示す。
The circuit configuration of the conventional Fritzker compensator is shown in the first example.
As shown in the figure.

1a,1b,1cは進相用コンデンサ、2a,
2b,2cは直列リアクトル、3a,3b,3
c,4a,4b,4cはサイリスタで、逆並列に
接続され、開閉制御を行う。
1a, 1b, 1c are phase advance capacitors, 2a,
2b, 2c are series reactors, 3a, 3b, 3
Thyristors c, 4a, 4b, and 4c are connected in antiparallel to perform opening/closing control.

1a,2a,3a,4aをNo.1分路とし、同様
な構成で、1b,2b,3b,4b,1c,2
c,3c,4cにてNo.2、No.3分路となり、各々
の容量は1:2:4の比として、各分路の組合せ
により7段制御を行うものであり、その制御は負
荷7の電流を変流器(CT)6より電流積分回路
に導かれる。計器用変圧器(PT)5と移相回路
12とタイミング回路13よりサンプリング回路
11にパルス信号を送出し、検出回路14である
値を保持し、投入分路選択用の選択回路15より
投入指令を送出し、ゲート回路18a,18b,
18cで受ける。サイリスタ端子電圧が0V付近
にてパルス信号を送出する同期検出回路16a,
16b,16cからの信号もゲート回路18a,
18b,18cで受け、他の過電流検出回路17
a,17b,17cの信号の論理積が成立したと
きのみゲート回路より信号を送出し、ゲートアン
プ19a,19b,19cよりサイリスタトリガ
ーし、各進相電流を流して電圧降下を補償する。
1a, 2a, 3a, 4a are No. 1 branches, and with the same configuration, 1b, 2b, 3b, 4b, 1c, 2
c, 3c, and 4c form the No. 2 and No. 3 shunts, and the capacity of each shunt is in the ratio of 1:2:4, and seven-stage control is performed by combining each shunt, and the control is based on the load. 7 is guided from a current transformer (CT) 6 to a current integrating circuit. A pulse signal is sent to the sampling circuit 11 from the potential transformer (PT) 5, phase shift circuit 12, and timing circuit 13, a certain value is held in the detection circuit 14, and a closing command is issued from the selection circuit 15 for selecting the closing branch. , and gate circuits 18a, 18b,
Received at 18c. A synchronization detection circuit 16a that sends out a pulse signal when the thyristor terminal voltage is around 0V,
Signals from 16b and 16c are also connected to gate circuits 18a and 18a.
18b and 18c, and other overcurrent detection circuit 17
Only when the AND of the signals a, 17b, and 17c is established, a signal is sent from the gate circuit, the gate amplifiers 19a, 19b, and 19c trigger the thyristors, and each phase-advanced current flows to compensate for the voltage drop.

次に従来例の動作を第2図により説明する。 Next, the operation of the conventional example will be explained with reference to FIG.

制御部では応答遅れはないものと仮定し、コン
デンサ1a,1b,1cの充電電圧は−√2E
(V)とする。このとき負荷電流(図中)によ
り検出回路14より投入信号を選択回路15に
送出するが、進相用コンデンサ(以下SCという)
充電電圧の極性により、半サイクル遅れの図中
点にてNo.1分路がONする。
Assuming that there is no response delay in the control section, the charging voltage of capacitors 1a, 1b, and 1c is -√2E.
(V). At this time, depending on the load current (in the figure), the detection circuit 14 sends a closing signal to the selection circuit 15.
Depending on the polarity of the charging voltage, the No. 1 shunt turns ON at the middle point in the diagram with a half-cycle delay.

また負荷電流が図中点にて増加し、No.1分路
よりNo.2分路に投入信号が切り換わつたとき、No.
1分路はOFFするが、No.2分路はSC充電電圧の
極性のため、半サイクル遅れにてONする。
Also, when the load current increases at the middle point in the figure and the input signal switches from the No. 1 branch to the No. 2 branch, the No.
Branch 1 turns OFF, but branch No. 2 turns ON with a half-cycle delay due to the polarity of the SC charging voltage.

このためにSC電流は半サイクル間なしとなり、
切れ目発生の欠点を有していた。
Therefore, the SC current is zero for half a cycle,
It had the disadvantage of generating cuts.

図中点で負荷電流がOFFすると、SC電流も
OFFできるため、電圧変動としては2回の電圧
降下を有することになる。
When the load current turns off at the middle point in the diagram, the SC current also
Since it can be turned off, the voltage fluctuation will have two voltage drops.

このように両サイリスタ方式においても、SC
充電電圧の極性により投入時に応答遅れを有し、
また充電の極性によつては応答遅れなしにするこ
とも可能であるが、分路切り換わり時に切れ目が
発生する欠点を有していた。
In this way, SC
There is a response delay when turning on due to the polarity of the charging voltage,
Furthermore, depending on the polarity of charging, it is possible to eliminate response delay, but it has the disadvantage that a break occurs when switching the shunt.

これは負荷電流検出後適正容量を選択し、各分
路に投入指令を送出するのみで、切換時に他分路
の投入状況を判定せずに投入指令を切り換えるた
めに、切れ目発生が起こるものである。
This is because the appropriate capacity is selected after detecting the load current, and the closing command is sent to each shunt, but the closing command is switched without determining the closing status of other shunts at the time of switching, which causes the disconnection. be.

このために応答遅れが小さくなつても切れ目発
生によりフリツカー改善効果があまり向上しない
欠点があつた。
For this reason, even if the response delay was reduced, there was a drawback that the flicker reduction effect was not improved much due to the occurrence of breaks.

本発明は両サイリスタ方式の投入分路の切り換
わり時に発生する電流切れ目の欠点をなくすため
に、投入分路の切り換わり時に、切り換わり後そ
の分路の投入可否を判定してから次段への投入信
号を切り換えることにより、切り目発生の欠点を
なくし、フリツカー改善効果の高いフリツカー補
償装置を提供するものである。
In order to eliminate the drawback of the current cutoff that occurs when switching the closing shunt in the dual thyristor system, the present invention determines whether or not the shunt can be turned on after switching when switching the closing shunt before proceeding to the next stage. The purpose of the present invention is to provide a flicker compensating device which eliminates the disadvantage of the generation of cuts and is highly effective in improving flicker by switching the input signal.

以下、本発明のフリツカー補償装置を第3図お
よび第4図に示す実施例により説明する。
The flicker compensator of the present invention will be explained below with reference to the embodiments shown in FIGS. 3 and 4.

第3図はフリツカー補償装置の回路説明図で、
1a,2a,3aは進相用コンデンサ、2a,2
b,2cは直列リアクトル、3a,3b,3c,
4a,4b,4cはサイリスタで逆並列接続され
ている。
Figure 3 is a circuit diagram of the Fritzker compensator.
1a, 2a, 3a are phase advance capacitors, 2a, 2
b, 2c are series reactors, 3a, 3b, 3c,
4a, 4b, and 4c are thyristors connected in antiparallel.

さらにコンデンサ投入時に過渡現象を起こさせ
ないために、サイリスタ両端電圧が0V付近にて
パルス信号を発生する同期検出回路16a,16
b,16cが各サイリスタ3a,4a,3b,4
b,3c,4cに各々接続されている。
Furthermore, in order to prevent a transient phenomenon from occurring when the capacitor is turned on, the synchronous detection circuits 16a and 16 generate a pulse signal when the voltage across the thyristor is around 0V.
b, 16c are each thyristor 3a, 4a, 3b, 4
b, 3c, and 4c, respectively.

この1a,2a,3a,4aをNo.1分路とし、
これと同一構成で他に2分路1b,2b,3b,
4b,1c,2c,3c,4cを有し、各々No.2
分路、No.3分路とする。各々の容量は1:2:4
の比とし、各分路の組合せにより7段階の容量が
得られる。
These 1a, 2a, 3a, and 4a are designated as No. 1 branch,
With the same configuration, there are 2 other branches 1b, 2b, 3b,
4b, 1c, 2c, 3c, 4c, each No. 2
Branch, No. 3 branch. Each capacity is 1:2:4
Seven levels of capacity can be obtained by combining each shunt.

制御部として負荷7の電流を変流器(CT)6
にて検出し、電流積分回路10、サンプリング回
路11にて直流電圧に変換する。また計器用変圧
器(PT)5と移相回路12とタイミング回路1
3よりサンプリング回路11への投入信号によ
り、検出回路14に検出値を保持させ、選択回路
15により投入分路が選択され信号を送出し、判
定回路20a,20b,20cへ送られる。判定
回路20a,20b,20cはその分路以外の同
期検出回路16a,16b,16cから信号を受
けており、投入段切り換わり時に他分路の投入可
否を判定させている。判定回路20a,20b,
20cよりゲート回路18a,18b,18cへ
投入信号が送られ、その分路の同期検出回路16
a,16b,16cからの信号もゲート回路18
a,18b,18cに送られる。また過電流検出
回路17a,17b,17cの信号もゲート回路
18a,18b,18cに送られる。
Current transformer (CT) 6 controls the current of load 7 as a control unit.
The voltage is detected by the current integrating circuit 10 and the sampling circuit 11 converts it into a DC voltage. Also, a potential transformer (PT) 5, a phase shift circuit 12, and a timing circuit 1
3 to the sampling circuit 11 causes the detection circuit 14 to hold the detected value, and the selection circuit 15 selects the input branch and sends out a signal, which is sent to the determination circuits 20a, 20b, and 20c. The determination circuits 20a, 20b, and 20c receive signals from the synchronization detection circuits 16a, 16b, and 16c other than the shunts, and determine whether or not the other shunts can be turned on when switching the closing stage. Judgment circuits 20a, 20b,
A closing signal is sent from 20c to the gate circuits 18a, 18b, 18c, and the synchronization detection circuit 16 of the branch
Signals from a, 16b, 16c are also sent to the gate circuit 18
a, 18b, and 18c. Further, signals from overcurrent detection circuits 17a, 17b, and 17c are also sent to gate circuits 18a, 18b, and 18c.

ゲート回路18a,18b,18cでは投入信
号、同期検出回路16a,16b,16cの信号
などの論理積が成立したとき、ゲートアンプ19
a,19b,19cに投入信号として送られ、サ
イリスタをトリガーする。
In the gate circuits 18a, 18b, 18c, when the logical product of the input signal, the signals of the synchronization detection circuits 16a, 16b, 16c, etc. is established, the gate amplifier 19
a, 19b, and 19c as a closing signal to trigger the thyristor.

次に動作原理を第4図により説明する。 Next, the principle of operation will be explained with reference to FIG.

第4図aは負荷電流および電源電圧波形図、b
は負荷電流量を直流分で示す波形図、cは選択回
路からのNo.1分路投入信号波形図、dは選択回路
からのNo.2分路投入信号波形図、eはNo.1分路用
判定回路から送出される信号波形図、fはNo.1,
No.2分路の同期検出回路より送出されるパルス信
号波形図、gはコンデンサ1aの進相電流ic1
波形図hはコンデンサ1bの進相電流ic1波形図、
iは合成電流ic1+ic2の波形図、jは電圧降下に
等価的な電圧波形図である。
Figure 4a is a load current and power supply voltage waveform diagram, b
is a waveform diagram showing the load current amount as a DC component, c is a waveform diagram of the No. 1 shunt closing signal from the selection circuit, d is a waveform diagram of the No. 2 shunt closing signal from the selection circuit, and e is a waveform diagram of the No. 1 shunt closing signal from the selection circuit. Signal waveform diagram sent from the road determination circuit, f is No.1,
Pulse signal waveform diagram sent out from the synchronization detection circuit of No. 2 branch, g is the leading phase current i c1 of capacitor 1a,
Waveform diagram h is a waveform diagram of advanced phase current i c1 of capacitor 1b,
i is a waveform diagram of the composite current i c1 +i c2 , and j is a voltage waveform diagram equivalent to a voltage drop.

第4図aにおいて、Eは電源電圧、iwは負荷電
流を示し、負荷が図中点より投入し、変流器よ
り検出され、選択回路15により、No.1分路に、
第4図cのごとく投入指令を送出したとする。
In Fig. 4a, E indicates the power supply voltage, and iw indicates the load current.The load is applied from the middle point in the figure, detected by the current transformer, and transferred to the No. 1 branch by the selection circuit 15.
Assume that a closing command is sent as shown in FIG. 4c.

このとき、進相用コンデンサ1aは負に充電さ
れているとすると、同期検出回路16aよりのパ
ルス信号は、第4図fのごとく電源電圧Eが真の
ピーク付近にて同期パルスを送出している。
At this time, assuming that the phase advance capacitor 1a is negatively charged, the pulse signal from the synchronization detection circuit 16a sends out a synchronization pulse when the power supply voltage E is near its true peak, as shown in FIG. 4f. There is.

上述の投入信号第4図cと、この同期パルスが
一致するc点よりサイリスタ3a,4aがON
し、No.1分路の進相電流が流れる。
Thyristors 3a and 4a are turned on from point c where the above-mentioned closing signal c in Figure 4 and this synchronization pulse match.
Then, the leading phase current of No. 1 branch flows.

さらに点より負荷電流が約2倍に増加し、遅
れ無効電力も2倍となると、選択回路15によ
り、第4図c,dのごとく、No.1分路からNo.2分
路に投入信号が切り換えられる。
Furthermore, when the load current increases approximately twice from this point and the delayed reactive power also doubles, the selection circuit 15 sends a signal to the No. 1 branch to the No. 2 branch as shown in Fig. 4c and d. can be switched.

しかしNo.2分路はNo.1分路と同様に、進相用コ
ンデンサ1bは負に充電されていると仮定する
と、No.1分路と同様に第4図fのごとく同期パル
スを送出しているため、投入信号が切り換わつた
時点では、No.2分路はONできないことになる。
However, the No. 2 branch, like the No. 1 branch, sends out synchronizing pulses as shown in Figure 4 f, assuming that the phase advancing capacitor 1b is negatively charged. Therefore, the No. 2 branch cannot be turned on at the time the input signal is switched.

このようなとき、No.1分路用判定回路20aは
投入指令を継続し、半サイクル後No.2分路の同期
検出回路16bよりの同期パルスを受けてから、
No.1分路の投入信号を消し、同時にNo.2分路用判
定回路20bでは、同期パルスと投入信号により
サイリスタ3b,4bをONし、第4図hの点
より進相電流を流し、合成でみると第4図iのご
とく切れ目がなく連続的に流れることになる。
In such a case, the No. 1 branch judgment circuit 20a continues to issue the closing command, and after receiving the synchronization pulse from the No. 2 branch synchronization detection circuit 16b after half a cycle,
The closing signal of the No. 1 branch is turned off, and at the same time, in the No. 2 branch judgment circuit 20b, the thyristors 3b and 4b are turned on by the synchronizing pulse and the closing signal, and a phase-advanced current is caused to flow from the point h in Fig. 4. When viewed as a composite, it flows continuously without any breaks as shown in Figure 4i.

ただ、負荷電流iwが点より増加しているに
もかかわらず、進相電流は充電電圧の極性により
半サイクル遅れとなり、第4図jのごとく電圧降
下が発生するが、従来例のごとく切れ目発生に比
較し、フリツカー改善効果が著しく向上できるも
のである。
However, even though the load current iw has increased from the point, the leading phase current is delayed by half a cycle due to the polarity of the charging voltage, and a voltage drop occurs as shown in Figure 4 j, but a discontinuity occurs as in the conventional example. Compared to the above, the fritzer improvement effect can be significantly improved.

なお、上述の実施例では、No.1分路からNo.2分
路への切り換わりについて述べたが、No.1分路か
らNo.3分路へ、No.2分路からNo.3分路へ等々も同
様に行なうことができる。
In addition, in the above-mentioned embodiment, switching from No. 1 branch to No. 2 branch was described, but switching from No. 1 branch to No. 3 branch and from No. 2 branch to No. 3 branch was described. The same can be done for shunting and so on.

また逆並列サイリスタと同等の機能を有するト
ライアツクを使用しても同様に行うことができ
る。
Further, the same operation can be performed using a triax having the same function as an anti-parallel thyristor.

本発明により、負荷通電中に容量が頻繁に変化
するものや、溶接機が多数あり、通電中の各種重
なり電流のため、容量切り換えが頻繁にある場合
でも、フリツカー改善効果が高いものとなる。
According to the present invention, even if the capacity changes frequently during load energization, there are many welding machines, and the capacity is frequently switched due to various overlapping currents during energization, the flicker improvement effect is high.

以上のように本発明のフリツカー補償装置は、
両サイリスタによる高速応答性を生かし、かつ分
路切り換わり時に発生する切れ目をなくすことに
より、従来に比較してフリツカー改善効果を向上
でき、工業的ならびに実用的価値の大なるもので
ある。
As described above, the Fritzker compensator of the present invention has the following features:
By taking advantage of the high-speed response of both thyristors and eliminating the break that occurs when switching the shunt, it is possible to improve the flicker reduction effect compared to the conventional method, which is of great industrial and practical value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のフリツカー補償装置の回路ブロ
ツクダイヤグラム、第2図は同従来のフリツカ補
償装置の各部の波形図、第3図は本発明のフリツ
カー補償装置の一実施例の回路ブロツクダイヤグ
ラム、第4図は同本発明のフリツカ補償装置の各
部の波形図である。 1a,1b,1c:進相用コンデンサ、2a,
2b,2c:直列リアクトル、3a,3b,3
c,4a,4b,4c:サイリスタ、7:負荷、
15:選択回路、16a,16b,16c:同期
検出回路、18a,18b,18c:ゲート回
路、20a,20b,20c:判定回路。
FIG. 1 is a circuit block diagram of a conventional flicker compensator, FIG. 2 is a waveform diagram of each part of the conventional flicker compensator, and FIG. 3 is a circuit block diagram of an embodiment of the flicker compensator of the present invention. FIG. 4 is a waveform diagram of each part of the flicker compensator of the present invention. 1a, 1b, 1c: phase advance capacitor, 2a,
2b, 2c: Series reactor, 3a, 3b, 3
c, 4a, 4b, 4c: thyristor, 7: load,
15: selection circuit, 16a, 16b, 16c: synchronization detection circuit, 18a, 18b, 18c: gate circuit, 20a, 20b, 20c: determination circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 進相用コンデンサ、直列リアクトルおよび半
導体スイツチにより構成された分路を負荷と並列
に複数群設け、該分路を開閉制御してなるフリツ
カー補償装置において、各半導体スイツチの両端
子電圧が0V付近にてパルス信号を発生する同期
検出回路と、負荷容量を検出して投入分路を選択
し投入信号を送出する選択回路と、投入された分
路以外の他の分路の信号を上記同期検出回路から
受けるとともに、投入分路がある分路から他の分
路に変換されたとき、他の分路の同期パルスが発
生するまで継続してある分路の投入信号を保持す
る判定回路と、該判定回路および同期検出回路か
らの信号を受けて半導体スイツチにゲート信号を
送出するゲート回路とを備え、分路切換時に電流
の切れ目なく制御することを特徴とするフリツカ
ー補償装置。
1. In a fritsker compensation device in which multiple groups of shunts each consisting of a phase advance capacitor, a series reactor, and a semiconductor switch are provided in parallel with the load, and the shunts are controlled to open and close, the voltage at both terminals of each semiconductor switch is around 0V. A synchronous detection circuit that generates a pulse signal at the synchronous detection circuit, a selection circuit that detects the load capacity, selects the input shunt, and sends out the input signal, and a synchronous detection circuit that detects the signals of other shunts other than the input shunt. a determination circuit that receives the input signal from the circuit and continues to hold the input signal of one branch until a synchronization pulse of the other branch is generated when the input branch is converted from one branch to another; A flicker compensator comprising a gate circuit that receives signals from the determination circuit and the synchronization detection circuit and sends a gate signal to a semiconductor switch, and controls the current without interruption when switching shunts.
JP58194549A 1983-10-17 1983-10-17 Flicker compensator Granted JPS6087628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58194549A JPS6087628A (en) 1983-10-17 1983-10-17 Flicker compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58194549A JPS6087628A (en) 1983-10-17 1983-10-17 Flicker compensator

Publications (2)

Publication Number Publication Date
JPS6087628A JPS6087628A (en) 1985-05-17
JPH0311177B2 true JPH0311177B2 (en) 1991-02-15

Family

ID=16326381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58194549A Granted JPS6087628A (en) 1983-10-17 1983-10-17 Flicker compensator

Country Status (1)

Country Link
JP (1) JPS6087628A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0641348U (en) * 1992-10-22 1994-05-31 日新電機株式会社 Injection circuit type active filter
JP5965277B2 (en) * 2012-10-10 2016-08-03 株式会社指月電機製作所 Capacitor device

Also Published As

Publication number Publication date
JPS6087628A (en) 1985-05-17

Similar Documents

Publication Publication Date Title
US5808378A (en) Control arrangement and method for high-speed source transfer switching system
JPH0740761B2 (en) AC electric vehicle control device
US4079443A (en) Circuit arrangement for starting up a converter having forced commutation with correct phase
JPH0311177B2 (en)
US4058738A (en) Method and circuit arrangement for starting up a converter having forced commutation with the correct phase
CA1159522A (en) System for coupling a capacitance to an ac voltage network
JPH0320977B2 (en)
EP0231315A1 (en) Induction motor drive arrangement
JP2830619B2 (en) Static var compensator
JPH0832364B2 (en) Power supply for welding machine
JP2001275255A (en) Voltage compensating device
JPH08314557A (en) Controller for reactive power compensator
US11431241B2 (en) Frequency converter with simplified pre-charging circuit
JP2703586B2 (en) Flicker compensator
JP3077300B2 (en) Instantaneous voltage drop compensator
SU1102015A1 (en) Method of adjusting three-phase zero-point three-phase thyristor
JP2671388B2 (en) Voltage detection circuit in voltage fluctuation suppression device
SU1339828A1 (en) Method of controlling switching device of three-phase capacitor stack
SU1350743A1 (en) Thyristor converter protection method
SU851640A1 (en) Method of switching-over two m-phase ac networks
JPH10253680A (en) Test method for short-time withstand current of switchgear
JPH08314559A (en) Rush current suppressor for transformer
JPS61255418A (en) Power-factor controlling device of power receiving line
JPH0746763A (en) Reactive power regulator
JPS5638994A (en) Controller for synchronous motor