JPS6087628A - Flicker compensator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flicker compensator N connected in parallel with the load in a circuit having a flicker-generating load.

FIG. 1 shows the circuit configuration of a conventional flicker compensation device.

la, lb, lc are phase advancing capacitors, 2as2bs2
C is series reactor, 3a13b13C14a14b1
4C is a thyristor connected in antiparallel to perform opening/closing control.

La, 2a, 3a, 4a are A1 branch, and with the same configuration, 1b, 2b, 3b, 4b, 1c, 2
c, 3c, and 4c are A2 and A3 branches, each capacity is 1:2:4 ratio, and the combination of each branch is 7.
It performs stage control, in which the current of the load 7 is guided from a current transformer (CT) 6 to a current integrating circuit. Instrument change 1: 'E'S'!: Phase shift circuit] 2 and timing circuit 1
30 Sends a pulse signal to the sampling circuit 11, holds a certain value in the detection circuit 14, sends a closing command to the selection circuit 15 for selecting a closing branch, and gates circuits 18a and 18b.
.

Accepted at 18C. Synchronous detection circuit 16a116b, 1 that sends out a PALNU signal when the thyristor terminal voltage is near OV
The signal from 6C is also received by gate circuits 18a, 18b%18C, and other overcurrent detection circuits 17'a, 1'7b.

A signal is sent from the gate circuit only when the logical product of the signals of 17C is established, and the gate amplifiers 19a and 19b%19C
The thyristor is triggered and each phase leading current flows to compensate for the voltage drop.

Next, the operation of the conventional example will be explained with reference to FIG.

Assuming that there is no response delay in the control section, capacitor 1
The charging voltage of a, 1b, and lc is -v'T E (V). At this time, the load current is sent to the load current (input signal from the input detection circuit 14 in the figure to the all selection circuit). The A1 branch is turned on at point 0 in the figure.

Also, the load current increases at point 0 in the figure, and the A1 shunt changes to the A2 shunt.
When the input signal is switched to the shunt, the grave 1 shunt is OFF.
However, the A2 branch turns on with a half-cycle delay because of the SC charging voltage polarity.

For this reason, the SC'Ft flow is not present for half a cycle, which has the disadvantage of generating a cut.

When the load current turns OFF at point [F] in the diagram, the SC current also turns OFF.
Since FF is possible, the voltage fluctuation has two voltage drops.

In this way, even in the double thyristor system, there is a response delay when the shunt is turned on due to the shunt nature of the SCC charging voltage, and depending on the charging polarity, it is possible to eliminate the response delay, but there is a delay when the shunt is switched. It had the disadvantage of occurring.

This is done by simply selecting the appropriate capacity ♀ after detecting the load current and sending a closing command to each shunt, and switching the closing command without determining the closing status of other shunts at the time of switching. It happens.

For this reason, even if the response delay is reduced, there is a drawback that the Schifflicker improvement effect cannot be improved significantly due to the occurrence of breaks.

In order to eliminate the drawback of the current cutoff that occurs when switching the closing shunt of the double thyristor system, the present invention has been designed to switch the closing shunt Dll to 9 and then turn on the shunt. The present invention provides a flicker compensating system m which eliminates the drawback of occurrence of a cut and has a high flicker improvement effect by switching the input signal to the next stage after determining whether or not it is possible.

Hereinafter, the 7 Ritzker compensator of the present invention will be explained as shown in FIGS. 3 and 4.
This will be explained based on the embodiment shown in the figures.

Naoyu 1kon Akdol, 3as 3bs 3C% 4as
4j and 4c are thyristors connected in reverse series.

Furthermore, in order to prevent transient phenomena from occurring when the capacitor is turned on, the synchronization detection circuit 16a% 16b% 16C generates a pulse signal when the voltage across the thyristor is around τV. l 3a, 4aN 3b% 4b, 3C.

4C, respectively.

These 1a, 2a13a, 4a are the A1 branch, and two other branches with the same configuration are 1b, 2b, 3b, 4b11c,
It has 2C, 3C, and 4C, each with 2 branches and /163 branches. The respective capacitances are in a ratio of 1:2:4, and the shunt combination provides a shunt stage capacitance.

As a control section, the current of the load 7 is detected by a transformer (CT) 6, and converted into a DC voltage by a current detection circuit 10 and a sampling circuit 1]. In addition, the detection circuit 14 is made to hold the detected value by the input signal to the sampling circuit 1 from the transformer (PT) 5 for a total of 8g, the phase shift circuit 12, and the timing table circuit 13, and the selection circuit 15 causes the input branch to be set. The selected signal is sent to the determination circuits 20a, 20bx, and 20c. The determination circuits 20a, 20b, and 20c receive signals from the synchronization detection circuits 16a, 16b, and 16c other than the shunt, and determine whether the other shunt is closed (nf) or not when the closing stage is switched. A closing signal is sent from the judgment circuits 20a, 20b, 20c to the gate circuits 18a', 18b, 18c, and the same detection circuits 16a, 16b of the branch circuits are sent.
The signal from S16c is also sent to gate circuits 18a, 18b,
Sent to 18c. In addition, overcurrent detection circuits 17a, 17
The signal of b117c is also gate circuit 18 as 18 bs
Sent to 18c.

In the gate circuit 18 a s 18 b s 18 c, when logic 11 such as the input signal and the signals of the synchronization detection circuits 16 a, 16 b, '16 c is established, the gate amplifier 19
a, 19b, 19c as a closing signal to trigger the thyristor.

Next, the principle of operation will be explained with reference to Fig. 4.

Figure 4(a) shows the load current and core voltage waveform diagram, To
) is the negative current amount′! Waveform diagram shown in I-plane flow, (C) is flat 1 branch input signal waveform diagram from the selection circuit, 0) is A2 branch input signal waveform diagram from the selection circuit, (e) is for A1 branch No. 18 waveform diagram sent from the judgment circuit, (f) is a pulse signal waveform diagram sent out from the synchronization detection circuit of A1゜A2 branch, @) is the advanced phase current iG1 of capacitor 1a, waveform diagram Q
l) is the leading phase current tct waveform diagram of capacitor 1b, (1)
is a waveform diagram of the composite current ic1 + icg, and (j) is a voltage waveform diagram equivalent to a voltage drop.

In Fig. 4 (a), E indicates the source pressure, 1w indicates the load 1! current, the load is applied from the point in the diagram, the current is detected by the current transformer, and the selection circuit 15 selects the current. Assume that a closing command is sent to the A1 branch as shown in FIG. 4(C).

At this time, assuming that the phase advance capacitor 1a is negatively charged, the pulse signal from the synchronization detection circuit 16a is
As shown in FIG. 4(f), the synchronizing pulse is sent out when the power supply voltage E is near its true peak.

Thyristor 3a14a turns ON from point C where this synchronizing pulse matches the above-mentioned input No. 1g (C) in Figure 4.
The leading phase current of the FLi shunt flows.

Furthermore, when the load current increases approximately twice from the zero point and the delayed reactive power also doubles, the selection circuit 15 selects the
), (d), the input signal is switched from the A1 branch to the flat 2 branch.

However, like the A1 branch, the A2 branch, assuming that the phase advance capacitor 1b is negatively charged, will send out the synchronizing signal as shown in Figure 4(f), just like the A1 branch. If it is not working, the input signal is switched A) It&a.

In this case, the A2 branch cannot be turned on.

In such a case, the AI branch judgment circuit 20a continues to issue the input command, and receives the synchronization signal from the same J'gj detection circuit 16b of the second branch after half a cycle, and then outputs the force, ra, A,
Turn off the input signal of branch 1 and at the same time turn off the judgment circuit 2 for branch A2.
At 0b, the thyristors 3b and 4b are turned ONL by the same J'd3)
, a phase-advanced current is passed from Hiro, and when viewed in combination, it flows continuously without any breaks as shown in Figure 4 (i).

However, even though the load current iw is increasing from the 0 point, the leading phase current is delayed by half a cycle due to the polarity of the charging voltage, and a voltage drop occurs as shown in Figure 4 (j).
Compared to the conventional example in which cuts occur, the flicker improvement effect can be significantly improved.

In addition, in the above-mentioned embodiment, switching from A1 branch to flat 2 branch was described, but when switching from A1 branch to flat 3 branch,
The same can be done from the A2 branch to the flat 3 branch, etc.

Further, the same operation can be performed using a triac having the same function as an anti-parallel thyristor.

According to the present invention, flicker can be improved even when the capacity 9 changes frequently while the load is energized, there are many connected machines, and the capacity is frequently changed due to the various types of current during 1 Jf 1 electric current. It will be highly effective.

As described above, the flicker compensation device of the present invention takes advantage of the high-speed response of both thyristors and eliminates the break that occurs when switching the shunt, thereby improving the flicker improvement effect compared to the conventional one. It is of great industrial and practical value.

[Brief explanation of drawings]

No. 11 is 1 of the conventional flicker compensation device! 2 is a waveform diagram of each part of the conventional flicker compensator, and FIG. 3 is a diagram of the present invention. FIG. 41, which is a circuit block diagram of an embodiment of the force compensator, is a waveform diagram of each part of the flicker compensator of the present invention. 1as 1bs IC: phase advance conte-9-2a,
2b, 2C: i column! J7ri)/l/3a, 3b, 3
C, 4a, 4b, 4C: Thyristor 7: Load 15: Selection circuit "ia% 16b% 16C: Synchronous detection circuit 18a,
18b% 180: Gate circuit 2tJas 20b,
20c: Judgment circuit Special pestle Applicant: Nippon Capacitor Industry Co., Ltd. Figure 1 Figure 2 Figure 8 Figure 4

Claims (1)

[Claims] A flicker compensator comprising a plurality of groups of shunts each composed of a phase advance capacitor, a series reactor μ, and a semiconductor switch is provided in parallel with a load, and the shunts are controlled to open and close,
A synchronization detection circuit generates a pulse-less signal when the voltage at both terminals of each semiconductor switch is near the dead line, a selection circuit detects the load capacity, selects closing or shunting, and sends the closing 4M signal. The signal from the other shunt is received from the synchronization detection circuit, and when the input shunt is converted from one shunt to another shunt, it continues until the synchronization pulse of the other shunt is generated. It is equipped with a judgment circuit that holds the signal when the shunt is turned on, and a gate circuit that receives No. 1a from the judgment circuit and the synchronization detection circuit and sends a gate signal to the semiconductor switch. A flicker compensation device characterized by continuous control.