JP2004254428A - Static reactive power compensator - Google Patents

Static reactive power compensator Download PDF

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Publication number
JP2004254428A
JP2004254428A JP2003042295A JP2003042295A JP2004254428A JP 2004254428 A JP2004254428 A JP 2004254428A JP 2003042295 A JP2003042295 A JP 2003042295A JP 2003042295 A JP2003042295 A JP 2003042295A JP 2004254428 A JP2004254428 A JP 2004254428A
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Prior art keywords
capacitor
arm
voltage
thyristors
tsc
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JP2003042295A
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JP4037284B2 (en
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Takafumi Fujimoto
貴文 藤本
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Toshiba Corp
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Toshiba Corp
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/10Flexible AC transmission systems [FACTS]

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive static reactive power compensator(TSC: Thyristor Switched Capacitor). <P>SOLUTION: An arm 2 composed of thyristors only, and an arm 3 partially composed of the thyristors (with the number of pieces which can withstand an AC voltage) and the rest of which is composed of diodes (with the number of pieces which can withstand a DC voltage at charge) are connected as shown in Fig., and this compensator controls gate signals supplied to the thyristors so that the signal stop applications of currents 4, 5, and 6 at the zero point of the currents after the application of currents of negative polarity by the arm 3 of each phase after the reception of a TSC stop command. Hereby, the arms 2 and 3 have withstand voltages enough both at the charge and after the discharge of a capacitor 1 after the stoppage of TSC, whereby this can reduce the number of required thyristors using inexpensive diodes. Moreover, a capacitor discharge device 7 becomes unnecessary by giving the gate signals to the thyristors of the arms 2 and 3 thereby discharging them. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、コンデンサを半導体素子によりオン・オフさせる静止型無効電力補償装置に関する。
【0002】
【従来の技術】
コンデンサをオン・オフさせ無効電力を制御する静止型無効電力補償装置(以下、TSCと略す。TSC:Thyristor Switched Capacitor)には、コンデンサをオン・オフさせるためのスイッチとして半導体素子が用いられている。TSCは交流電力調整を行うことから電流を双方向に通電させる必要があるため、図5に示すように半導体素子はアーム2、3Aの如く逆並列接続となる。通常、半導体素子にはサイリスタが用いられ、ゲート発生装置からのゲート信号により双方向の通電を行っている。以下、サイリスタを用いた場合のTSCについて記述する。
【0003】
サイリスタは所定の電圧に耐えるよう複数個直列接続されるが、サイリスタの直列数は、図3の(a)に示すように、TSCが停止した後のコンデンサ1に充電された直流電圧に電源の交流電圧が重畳した電圧に耐えるよう設計される。コンデンサに充電される直流電圧の極性は、TSCが停止する直前に通電していたサイリスタの方向で決定される。サイリスタは電流が零になることでオフするので、図6に示すように、TSC停止指令を受けた後の電流零点で3相それぞれがオフする。
【0004】
すると、コンデンサに充電される直流電圧は、必ず3相のうち2相は同極性、残る1相は逆極性となり、TSC停止指令とアーム2またはアーム3Aの通電時期により、アーム2、3Aには直流電圧に交流電圧の重畳した波形が、正極性、負極性のどちらかで印加されることになる。
【0005】
更に、コンデンサ1に充電された直流電圧を放電するため、図5に示すように、各コンデンサ1にはコンデンサ放電装置7が別に設けられている。TSC停止後、コンデンサ放電装置7を動作させ、コンデンサ1に充電された電荷を放電させる。
【0006】
なお、コンデンサを、逆並列接続した一対のサイリスタによりオン・オフさせるTSCにおいて、コンデンサの初期充電が必要な場合に、充電時の突入電流による異常電圧を抑制するために充電をソフトスタートさせる技術は、既に知られている(例えば、特許文献1参照。)。
【0007】
【特許文献1】
実開平6−75016号公報(第1頁、図1)
【0008】
【発明が解決しようとする課題】
前述のように、サイリスタとしては、コンデンサの直流電圧と電源の交流電圧が重畳した電圧の正極性・負極性共に耐えるよう直列数を決定しておく必要があり、数多くのサイリスタを必要とし、また各コンデンサには放電装置を必要としていた。
【0009】
従来、このような課題を解決する技術は知られておらず、特許文献1にも、このような課題を解決する技術、すなわち、サイリスタ数の低減や、放電装置の不要化については、開示されていない。
【0010】
そこで、本発明の目的は、必要とするサイリスタの数を低減し、また放電装置を不要とすることも可能で、安価な静止型無効電力補償装置を提供することにある。
【0011】
【課題を解決するための手段】
前記目的を達成するために、本発明は、コンデンサを、ゲート信号により導通する半導体素子を含む第1および第2の回路を逆並列に接続した回路によりオン・オフさせる静止型無効電力補償装置において、第1の回路はその全てをゲート信号により導通する半導体素子で構成するとともに、第2の回路はその一部をゲート信号により導通する半導体素子、残る一部をダイオードで構成し、静止型無効電力補償装置を停止させる場合に、第2の回路の側で導通が止まるように半導体素子に供給するゲート信号を制御するゲート信号供給制御手段を備えたことを特徴とする。
【0012】
このような構成の本発明によれば、第2の回路の一部を安価なダイオードとすることで、第2の回路の全素子をゲート信号により導通する半導体素子にする必要がなく、静止型無効電力補償装置を安価なものとすることができ、また、ゲート信号を供給するゲート信号伝送路の削減が可能となる。
【0013】
ここで、さらに、ゲート信号供給制御手段を、静止型無効電力補償装置停止後、コンデンサの電荷を放電させるためのゲート信号を、第1および第2の回路の半導体素子に供給するように制御するものとすることもできる。
【0014】
このような構成とすることで、コンデンサの放電装置を設置する必要がなくなる。
【0015】
【発明の実施の形態】
以下、図面を参照して本発明の実施形態について詳細に説明する。
【0016】
(第1の実施形態)
本発明の第1の実施形態に係るTSCについて説明する。
【0017】
図1は、この実施形態の主要部の構成を示す図、図2は、この実施形態の動作を説明するための、各相の電流波形およびゲートを制御するための信号を示す図である。
【0018】
図1において、1はコンデンサ、2は図2(a)の正極性電流を通電する半導体素子をM個直列接続したアーム、3は図2(a)の負極性電流を通電する半導体素子をN個直列接続したアーム、4、5、6は3相の各電流を示す。なお、7はコンデンサ放電装置である。
【0019】
図2(a)において、8、9、10は図1の相4、5、6の電流に対応する電流波形で、TSC停止指令を受けた後の各相の負極性電流の通電後の電流零点で3相それぞれがオフする様子を示したものである。また、図2の(b)〜(k)はTSC停止指令を受けた後の各相の負極性電流の通電後の電流零点で3相それぞれをオフするようにゲートを制御するための信号を示したものである。
【0020】
TSC停止指令によりアーム2またはアーム3の電流4の通電を止めるのに、アーム3による負極性電流を通電した後の電流零点で行うように制御する。
【0021】
例えば、電流4の相については、TSCの運転中は、アーム2およびアーム3のサイリスタには、図示しないゲート制御装置から図2に示すようなゲート信号(c)、(d)がそれぞれ供給されているが、図示しないゲート制御装置においては、TSC停止指令のゲート信号を受けた後は、図2に示すTSC停止指令信号(b)と、負極性電流通電期間に相当する信号(e)とのANDが成立したときそれ以降のアーム2へのゲート信号(c)の供給を停止するとともに、ANDが成立してから少し遅れてそれ以降のアーム3へのゲート信号(d)の供給も停止するように制御する。従って、アーム2またはアーム3の電流4は、図2(a)の8で示すように、負極性電流を通電した後の電流零点でストップする。
【0022】
電流5についても同様に、TSC停止指令信号(b)と負極性電流通電期間に相当する信号(h)とのANDの成立でそれ以降のアーム2へのゲート信号(f)の供給を停止し、ANDが成立してから少し遅れてそれ以降のアーム3へのゲート信号(g)の供給も停止するように制御する。従って、電流5は、図2(a)の9で示すように、負極性電流を通電した後の電流零点でストップする。
【0023】
更に、電流6についても、TSC停止指令信号(b)と負極性電流通電期間に相当する信号(k)とのANDの成立でそれ以降のアーム2へのゲート信号(i)の供給を停止し、ANDが成立してから少し遅れてそれ以降のアーム3へのゲート信号(j)の供給も停止するように制御する。従って、電流6は、図2(a)の10で示すように、負極性電流を通電した後の電流零点でストップする。
【0024】
以上のように、TSC停止指令を受けた後の各相の電流波形は図2(a)のようになり、コンデンサ1に充電される極性は図1のように、アーム2には順方向電圧、アーム3には逆方向電圧となる。このときの電圧波形を図3に示す。3相とも同一方向にコンデンサが充電される。
【0025】
図3において(a)はコンデンサが充電されている時の波形、(b)はコンデンサが放電し終えたときの波形を示す。コンデンサが充電されている時の図3の(a)では、アーム2には直流電圧と交流電圧が重畳した波形が順方向に印加され、アーム3には直流電圧と交流電圧が重畳した波形が逆方向に印加されることになる。また、コンデンサが放電し終えたときの図3の(b)では、アーム2、3とも順方向、逆方向に等しい交流電圧が印加されることになる。
【0026】
そこで、アーム2は直流電圧と交流電圧が重畳した波形が順方向に印加されても順方向耐電圧を有するよう全ての半導体素子をサイリスタとする。コンデンサ1の放電後には、アーム2には順方向、逆方向とも電圧が印加されるが、サイリスタは逆方向耐電圧も有するので、耐電圧は十分有する。
【0027】
続いて、アーム3は直流電圧と交流電圧が重畳した波形が逆方向に印加されても逆方向耐電圧を有するよう一部の半導体素子をサイリスタ、残る一部の半導体素子をダイオード(整流素子)とする。コンデンサ放電装置7を用いてコンデンサ1を放電させた後には、アーム3には順方向、逆方向とも電圧が印加され、ダイオードでは順方向電圧をブロックすることはできないが、アーム3の一部の半導体素子をサイリスタとすることで順方向耐電圧も有し、耐電圧は十分有する。
【0028】
前述のアーム2の半導体直列数Mは直流電圧と交流電圧が重畳した波形が順方向に印加されても耐えうる個数となる。アーム3の半導体直列数Nは、コンデンサ1放電後の交流電圧に耐えうるよう設計したサイリスタ個数N1と、コンデンサ1に充電された直流電圧に耐えうるよう設計したダイオード個数N2との合計となる。
【0029】
以上のように構成されたこの実施形態において、アーム3の一部をダイオードとすることで、図示しないゲート発生装置のゲート信号回路の一部を削減でき、またゲート発生装置からアーム3へのゲート信号伝送路の削減が可能となる。
【0030】
さらに、アーム3の一部を安価なダイオードとすることで、より安価な静止型無効電力補償装置を提供することができる。
【0031】
なお、上述の説明では、アーム2はサイリスタをM個直列に接続した一列のものとしたが、一列のものに限らず、サイリスタをM個直列に接続したものを複数列並列に接続したものとしてもよい。また、アーム3についても、一列のものに限らず、サイリスタN1個とダイオードN2個とを直列に接続したものを複数列並列に接続したものとしてもよい。
【0032】
(第2の実施形態)
次に、本発明の第2の実施形態に係るTSCについて説明する。この第2の実施形態は、3相のアーム2、3にゲート信号を与えることで、コンデンサ1の電荷の放電を行うようにしたもので、前述の第1の実施形態におけるコンデンサ放電装置7を不要としたものである。
【0033】
図4は、この実施形態の動作を説明するための、放電電流波形およびゲートを制御するための信号を示す図である。
【0034】
前述の第1の実施形態において、TSC停止後、コンデンサ1は3相全て同一方向に充電されているので、3相のアーム2、3のサイリスタに図示しないゲート発生装置からゲート信号を与えることで、コンデンサ1からの放電が可能となる。すなわち、3相のアーム2のサイリスタに図示しないゲート発生装置から図4に示すゲート信号(b)を与えることで、コンデンサ1は逆方向に充電されるので、次はアーム3のサイリスタに図示しないゲート発生装置から図4に示すゲート信号(c)を与える。するとコンデンサ1はTSC停止後と同じ方向に充電される。
【0035】
このように、アーム2、3に周期的に図示しないゲート発生装置からゲート信号(b)、(c)を与えることで、半導体素子の抵抗や回路の抵抗で放電電流は減衰していき、コンデンサ1からの放電電流は図4(a)のように振動波形となり、やがてコンデンサ1の電荷は零になる。
【0036】
なお、アーム2、3のサイリスタにそれぞれ図4に示すゲート信号(b)、(c)を与える代わりに、それぞれ図4に示すゲート信号(d)、(e)を与えてもよい。
【0037】
この第2の実施形態によれば、コンデンサ1専用の放電装置7を設けることなく、コンデンサ1の放電が可能となり、より安価な静止型無効電力補償装置を提供することができる。
【0038】
【発明の効果】
以上のような構成の本発明によれば、使用する半導体素子の一部を安価なダイオードとすることができ、より安価な静止型無効電力補償装置を提供できる。
【0039】
また、コンデンサ専用の放電装置を設けることなく、コンデンサの放電を可能とし、より安価な静止型無効電力補償装置を提供することもできる。
【図面の簡単な説明】
【図1】本発明の第1の実施形態に係るTSCの主要部の構成を示す図。
【図2】第1の実施形態の動作を説明するための、各相電流波形およびゲートを制御するための信号を示す図。
【図3】第1の実施形態における各アームに印加される電圧波形を示す図。
【図4】第2の実施形態の動作を説明するための、放電電流波形およびゲートを制御するための信号を示す図。
【図5】従来のTSCの主要部の構成を示す図。
【図6】従来のTSCの各相電流波形を示す図。
【符号の説明】
1…コンデンサ
2…正極性電流通電アーム
3…負極性電流通電アーム
4、5、6…各アーム通電電流
7…コンデンサ放電装置
8、9、10…各アーム通電電流波形
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a static reactive power compensator that turns a capacitor on and off with a semiconductor element.
[0002]
[Prior art]
In a static reactive power compensator (hereinafter abbreviated as TSC, TSC: Thyristor Switched Capacitor) for controlling reactive power by turning on / off a capacitor, a semiconductor element is used as a switch for turning on / off the capacitor. . Since the TSC performs AC power adjustment, it is necessary to pass current in both directions. Therefore, as shown in FIG. 5, the semiconductor elements are connected in antiparallel as in the arms 2 and 3A. Usually, a thyristor is used as a semiconductor element, and bidirectional energization is performed by a gate signal from a gate generator. Hereinafter, TSC in the case of using a thyristor will be described.
[0003]
A plurality of thyristors are connected in series to withstand a predetermined voltage. As shown in FIG. 3A, the number of thyristors is connected to the DC voltage charged in the capacitor 1 after the TSC is stopped. Designed to withstand the superimposed voltage of AC voltage. The polarity of the DC voltage charged in the capacitor is determined by the direction of the thyristor that was energized immediately before the TSC stopped. Since the thyristor is turned off when the current becomes zero, as shown in FIG. 6, each of the three phases is turned off at the current zero point after receiving the TSC stop command.
[0004]
Then, the DC voltage charged in the capacitor must be the same polarity for two of the three phases and the opposite polarity for the remaining one phase. Depending on the TSC stop command and the energization timing of arm 2 or arm 3A, A waveform in which an AC voltage is superimposed on a DC voltage is applied in either a positive polarity or a negative polarity.
[0005]
Further, in order to discharge the DC voltage charged in the capacitor 1, each capacitor 1 is separately provided with a capacitor discharging device 7 as shown in FIG. After stopping the TSC, the capacitor discharge device 7 is operated to discharge the electric charge charged in the capacitor 1.
[0006]
In the TSC where the capacitor is turned on / off by a pair of anti-parallel thyristors, when the capacitor needs to be initially charged, the technology for soft-starting charging in order to suppress abnormal voltage due to inrush current during charging is Is already known (see, for example, Patent Document 1).
[0007]
[Patent Document 1]
Japanese Utility Model Publication No. 6-75016 (first page, FIG. 1)
[0008]
[Problems to be solved by the invention]
As described above, as the thyristor, it is necessary to determine the series number so that both the positive polarity and the negative polarity of the voltage obtained by superimposing the DC voltage of the capacitor and the AC voltage of the power source are required, and a large number of thyristors are required. Each capacitor required a discharge device.
[0009]
Conventionally, a technique for solving such a problem has not been known, and Patent Document 1 discloses a technique for solving such a problem, that is, a reduction in the number of thyristors and an unnecessary discharge device. Not.
[0010]
Accordingly, an object of the present invention is to provide an inexpensive static reactive power compensator that can reduce the number of necessary thyristors and eliminate the need for a discharge device.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a static reactive power compensator in which a capacitor is turned on / off by a circuit in which a first and a second circuit including a semiconductor element that is conducted by a gate signal are connected in antiparallel. The first circuit is composed of semiconductor elements that are all conductive by a gate signal, and the second circuit is a semiconductor element that is partially conductive by a gate signal and the remaining part is a diode, which is a static invalid When the power compensator is stopped, gate signal supply control means is provided for controlling a gate signal supplied to the semiconductor element so that conduction is stopped on the second circuit side.
[0012]
According to the present invention having such a configuration, since a part of the second circuit is an inexpensive diode, it is not necessary to make all elements of the second circuit conductive semiconductor elements by a gate signal. The reactive power compensator can be made inexpensive, and the number of gate signal transmission paths for supplying gate signals can be reduced.
[0013]
Here, the gate signal supply control means further controls the gate signal for discharging the charge of the capacitor to the semiconductor elements of the first and second circuits after stopping the static reactive power compensator. It can also be.
[0014]
With this configuration, it is not necessary to install a capacitor discharge device.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
(First embodiment)
The TSC according to the first embodiment of the present invention will be described.
[0017]
FIG. 1 is a diagram showing a configuration of a main part of this embodiment, and FIG. 2 is a diagram showing a current waveform of each phase and a signal for controlling a gate for explaining the operation of this embodiment.
[0018]
In FIG. 1, 1 is a capacitor, 2 is an arm in which M semiconductor elements that conduct positive current of FIG. 2 (a) are connected in series, and 3 is a semiconductor element that conducts negative current of FIG. The arms 4, 5, and 6 connected in series indicate currents of three phases. Reference numeral 7 denotes a capacitor discharge device.
[0019]
In FIG. 2 (a), 8, 9, and 10 are current waveforms corresponding to the currents of phases 4, 5, and 6 in FIG. 1, and the current after energization of the negative current of each phase after receiving the TSC stop command. It shows how each of the three phases is turned off at the zero point. 2 (b) to 2 (k) show signals for controlling the gates so that the three phases are turned off at the current zero point after energization of the negative polarity current of each phase after receiving the TSC stop command. It is shown.
[0020]
In order to stop the energization of the current 4 of the arm 2 or the arm 3 by the TSC stop command, control is performed so as to be performed at the current zero point after the negative current by the arm 3 is energized.
[0021]
For example, for the phase of current 4, during operation of the TSC, gate signals (c) and (d) as shown in FIG. 2 are supplied to the thyristors of arm 2 and arm 3 from a gate control device (not shown). However, in the gate control device (not shown), after receiving the gate signal of the TSC stop command, the TSC stop command signal (b) shown in FIG. 2 and the signal (e) corresponding to the negative current conduction period When the AND is established, the supply of the gate signal (c) to the arm 2 thereafter is stopped, and the supply of the gate signal (d) to the arm 3 thereafter is also stopped a little after the AND is established. Control to do. Therefore, the current 4 of the arm 2 or 3 stops at the current zero point after the negative current is applied, as indicated by 8 in FIG.
[0022]
Similarly, for the current 5, the supply of the gate signal (f) to the arm 2 is stopped when the AND of the TSC stop command signal (b) and the signal (h) corresponding to the negative current conduction period is established. Control is performed so that the supply of the gate signal (g) to the arm 3 thereafter is stopped a little after the AND is established. Therefore, the current 5 stops at the current zero point after the negative current is applied, as indicated by 9 in FIG.
[0023]
Further, for the current 6, the supply of the gate signal (i) to the arm 2 thereafter is stopped by the AND of the TSC stop command signal (b) and the signal (k) corresponding to the negative current conduction period. Then, the control is performed so that the supply of the gate signal (j) to the arm 3 thereafter is stopped a little after the AND is established. Accordingly, the current 6 stops at the current zero point after the negative current is applied, as indicated by 10 in FIG.
[0024]
As described above, the current waveform of each phase after receiving the TSC stop command is as shown in FIG. 2A, and the polarity charged in the capacitor 1 is the forward voltage in the arm 2 as shown in FIG. The arm 3 has a reverse voltage. The voltage waveform at this time is shown in FIG. The capacitors are charged in the same direction for all three phases.
[0025]
3A shows a waveform when the capacitor is charged, and FIG. 3B shows a waveform when the capacitor has been discharged. In FIG. 3A when the capacitor is charged, the arm 2 has a waveform in which a DC voltage and an AC voltage are superimposed in the forward direction, and the arm 3 has a waveform in which the DC voltage and the AC voltage are superimposed. It will be applied in the reverse direction. Further, in FIG. 3B when the capacitor has been discharged, the AC voltages equal in the forward direction and the reverse direction are applied to the arms 2 and 3.
[0026]
Therefore, the arm 2 uses all the semiconductor elements as thyristors so as to have a forward withstand voltage even when a waveform in which a DC voltage and an AC voltage are superimposed is applied in the forward direction. After the capacitor 1 is discharged, a voltage is applied to the arm 2 in both the forward and reverse directions. However, since the thyristor also has a reverse withstand voltage, the withstand voltage is sufficient.
[0027]
Subsequently, the arm 3 is configured such that some semiconductor elements are thyristors and some remaining semiconductor elements are diodes (rectifier elements) so as to have a reverse breakdown voltage even when a waveform in which a DC voltage and an AC voltage are superimposed is applied in the reverse direction. And After the capacitor 1 is discharged using the capacitor discharge device 7, a voltage is applied to the arm 3 in both the forward and reverse directions, and the diode cannot block the forward voltage. By using a semiconductor element as a thyristor, it also has a forward withstand voltage and a sufficient withstand voltage.
[0028]
The number M of semiconductor series in the arm 2 described above is a number that can withstand a waveform in which a DC voltage and an AC voltage are superimposed in the forward direction. The semiconductor series number N of the arm 3 is the sum of the thyristor number N1 designed to withstand the AC voltage after discharging the capacitor 1 and the diode number N2 designed to withstand the DC voltage charged in the capacitor 1.
[0029]
In this embodiment configured as described above, a part of the arm 3 is a diode, so that a part of the gate signal circuit of the gate generator (not shown) can be reduced, and the gate from the gate generator to the arm 3 can be reduced. The signal transmission path can be reduced.
[0030]
Furthermore, a cheaper static reactive power compensator can be provided by using a part of the arm 3 as an inexpensive diode.
[0031]
In the above description, the arm 2 is assumed to be a single row in which M thyristors are connected in series. However, the arm 2 is not limited to a single row, and a plurality of M thyristors connected in series is connected in parallel in a plurality of rows. Also good. Further, the arm 3 is not limited to a single row, and a plurality of thyristors N1 and diodes N2 connected in series may be connected in parallel in a plurality of rows.
[0032]
(Second Embodiment)
Next, the TSC according to the second embodiment of the present invention will be described. In the second embodiment, a gate signal is applied to the three-phase arms 2 and 3 to discharge the electric charge of the capacitor 1, and the capacitor discharge device 7 in the first embodiment described above is provided. It is unnecessary.
[0033]
FIG. 4 is a diagram showing a discharge current waveform and a signal for controlling the gate for explaining the operation of this embodiment.
[0034]
In the first embodiment described above, after the TSC is stopped, the capacitor 1 is charged in the same direction in all three phases. Therefore, by applying a gate signal from a gate generator (not shown) to the thyristors of the three-phase arms 2 and 3. The capacitor 1 can be discharged. That is, when the gate signal (b) shown in FIG. 4 is applied to the thyristor of the three-phase arm 2 from the gate generator (not shown), the capacitor 1 is charged in the reverse direction, so that the thyristor of the arm 3 is not shown next. The gate signal (c) shown in FIG. 4 is given from the gate generator. Then, the capacitor 1 is charged in the same direction as after the TSC is stopped.
[0035]
As described above, when the gate signals (b) and (c) are periodically supplied to the arms 2 and 3 from the gate generator (not shown), the discharge current is attenuated by the resistance of the semiconductor element and the resistance of the circuit. The discharge current from 1 becomes a vibration waveform as shown in FIG. 4A, and the charge of the capacitor 1 eventually becomes zero.
[0036]
Instead of providing the gate signals (b) and (c) shown in FIG. 4 to the thyristors of the arms 2 and 3, respectively, the gate signals (d) and (e) shown in FIG.
[0037]
According to the second embodiment, it is possible to discharge the capacitor 1 without providing the discharge device 7 dedicated to the capacitor 1, and it is possible to provide a cheaper static reactive power compensator.
[0038]
【The invention's effect】
According to the present invention configured as described above, a part of the semiconductor element to be used can be an inexpensive diode, and a more inexpensive static reactive power compensator can be provided.
[0039]
Further, it is possible to provide a more inexpensive static reactive power compensator that can discharge a capacitor without providing a capacitor-specific discharge device.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a main part of a TSC according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a current waveform for each phase and a signal for controlling a gate for explaining the operation of the first embodiment;
FIG. 3 is a view showing voltage waveforms applied to each arm in the first embodiment.
FIG. 4 is a diagram showing a discharge current waveform and a signal for controlling a gate for explaining the operation of the second embodiment.
FIG. 5 is a diagram showing a configuration of a main part of a conventional TSC.
FIG. 6 is a diagram showing each phase current waveform of a conventional TSC.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Capacitor 2 ... Positive polarity current conduction arm 3 ... Negative polarity current conduction arm 4, 5, 6 ... Each arm conduction current 7 ... Capacitor discharge device 8, 9, 10 ... Each arm conduction current waveform

Claims (2)

コンデンサを、ゲート信号により導通する半導体素子を含む第1および第2の回路を逆並列に接続した回路によりオン・オフさせる静止型無効電力補償装置において、前記第1の回路はその全てをゲート信号により導通する半導体素子で構成するとともに、前記第2の回路はその一部をゲート信号により導通する半導体素子、残る一部をダイオードで構成し、静止型無効電力補償装置を停止させる場合に、前記第2の回路の側で導通が止まるように前記半導体素子に供給するゲート信号を制御するゲート信号供給制御手段を備えたことを特徴とする静止型無効電力補償装置。In a static reactive power compensator in which a capacitor is turned on / off by a circuit in which a first and a second circuit including a semiconductor element that is conducted by a gate signal are connected in antiparallel, the first circuit is a gate signal In the case where the second circuit is composed of a semiconductor element that is partly conducted by a gate signal and the remaining part is constituted by a diode, and the static reactive power compensator is stopped, A static reactive power compensator comprising gate signal supply control means for controlling a gate signal supplied to the semiconductor element so that conduction is stopped on the second circuit side. 前記ゲート信号供給制御手段は、静止型無効電力補償装置停止後、前記コンデンサの電荷を放電させるためのゲート信号を、前記第1および第2の回路の半導体素子に供給するように制御するものであることを特徴とする請求項1に記載の静止型無効電力補償装置。The gate signal supply control means controls to supply a gate signal for discharging the charge of the capacitor to the semiconductor elements of the first and second circuits after the static reactive power compensator stops. The static reactive power compensator according to claim 1, wherein:
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101675569A (en) * 2007-05-18 2010-03-17 Abb技术有限公司 Static var compensator apparatus
JP2014017963A (en) * 2012-07-09 2014-01-30 Mitsubishi Electric Corp Static reactive power compensator
JP7425533B2 (en) 2020-08-12 2024-01-31 東芝三菱電機産業システム株式会社 reactive power compensator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109936149A (en) * 2019-03-27 2019-06-25 安徽三联学院 A kind of capacitor fast-switching switch circuit maintaining technology based on DC voltage

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101675569A (en) * 2007-05-18 2010-03-17 Abb技术有限公司 Static var compensator apparatus
JP2014017963A (en) * 2012-07-09 2014-01-30 Mitsubishi Electric Corp Static reactive power compensator
JP7425533B2 (en) 2020-08-12 2024-01-31 東芝三菱電機産業システム株式会社 reactive power compensator

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