JP2830619B2 - Static var compensator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static var compensator having a control unit capable of changing the control of an inverter unit between a steady state and a transient state.

[0002]

2. Description of the Related Art In a system with a variable load such as an electric vehicle, a static var compensator as shown in FIG. 4 is applied. It is assumed that the system bus 4 is connected to the power supply 1 and the variable load 3 is applied thereto. On the other hand, the GTO is connected to the system bus 4 via the transformer 8
Are connected to the inverter 9 connected in full bridge. Reference numeral 10 denotes a capacitor as a power source of the voltage source inverter. As such a control circuit for the inverter 9, the power fluctuation suppression control circuit 12 which receives the system bus voltage signal and the bus current signal from the PT5 for system bus voltage detection and the CT6 for system bus current detection has Calculate Q. On the other hand, the bus voltage signal is subtracted from the system voltage reference value Vref by the adder 18, and the system voltage constant control circuit 11
A difference voltage signal ΔV is output to the adder 19, and ΔV and Q are added by the adder 19 and input to the reactive current control circuit 14. On the other hand, the conduction current of the inverter 9 is detected by the CT 17, and the reactive power value signal Q ₁ is obtained by the reactive power detector 21, and the reactive current control circuit
At 14, Q ₁ is subtracted from ΔV + Q, and a delay corresponding to a reactive current generated in the system bus 4 by the inverter 9,
Or advanced phase reactive power signal i _s is obtained, and inputs the PWM gate control circuit 15. Wherein if i _s is a reactive power signal of the slow phases may be caused to flow into the leading phase reactive current corresponding to the reactive power signal of the phase lag to the system bus 4 via a transformer 8 from the inverter 9, i _{If s} is a leading reactive power signal, it may be configured so that a lagging reactive current flows into the system bus 4. Accordingly, the PWM gate control circuit 15, if i _s is a reactive power signal of the slow phase, the synchronizing signal from the synchronizing power supply circuit 13, between - [pi] / 2 than π / 2, i _s equivalent the leading phase current so as to flow into the system bus 4 in accordance with the magnitude of the i _s, by varying the PWM pulse width theta ₁ through? ₅ as shown in FIG. 2, whereas invalid i _s is the phase advance If it is the power signal, the synchronization signal from the synchronization source circuit 13, between than [pi / 2 of the 3 [pi] / 2, a i _s equivalent of the slow current so as to flow into the system bus 4, the i _s size The inverter current is arbitrarily controlled by making the PWM pulse width θ _{6 to} θ ₁₀ variable accordingly. These PW
The M pulses θ _{1 to} θ ₅ or θ _{6 to} θ ₁₀ are input to the gate drive circuit 16 to send a leading reactive current or a lagging current to the system bus 4, and the system bus voltage is continuously controlled to be constant. . In this case, the switching loss of the inverter is
Since the number increases in proportion to the carrier frequency that generates the PWM pulse, the loss increases when high-speed control is always performed by PWM.

[0003]

By the way, in an electric railway load, an instantaneous voltage drop occurs due to an inrush current caused by turning on an AT feeder (a feeder line constituted by an autotransformer) and switching on a train. However, there is no need to adjust the feeder line voltage in a rapid response to voltage fluctuations in the feeder line except in the case of the above-mentioned transient state. The present invention controls the output current of the inverter to suppress the system voltage fluctuation by performing high-speed control of the inverter by PWM by switching the carrier frequency only when the instantaneous voltage drop occurs. The purpose is to reduce the switching loss of the inverter section by the PWM high-speed control.

[0004]

FIG. 1 is a block diagram showing an embodiment of the present invention.
The present invention will be described. 4 denote the same parts.
The configuration of the circuit shown in FIG. 1 and that shown in FIG. 4 are different from those shown in FIG. 1 in that a PWM carrier frequency switching circuit 20 is provided, and the switching circuit 20 increases a carrier frequency by a CB input signal. Frequency carrier,
The carrier frequency is input to the PWM gate control circuit 15.
When the system bus 4 is stationary, the PWM gate control circuit 15
Late phase inputs, or advanced phase reactive power signal i _s is modulated by the power supply frequency and the same frequency of the carrier, Figure 3
Each emit one pulse PWM signal half cycle having a pulse width according to the magnitude of i _s as shown in, and input to the gate drive circuit 16, controls the inverter 9. For i _s is lagging input to PWM gate control circuit 15, to produce the inverter current advances in current as shown in FIG. 3, and generates a rectangular wave, and supplying reactive power, i _s progresses For phases,
Similarly, as shown in FIG. 3, the inverter current generates a rectangular wave so as to generate a delayed current, and the inverter 9 is controlled to consume the reactive power. Voltage variation caused by inrush current switching-on or the like of a train, for example by CB-on signal, switches the carrier frequency to an integer multiple of the power frequency in the PWM carrier frequency switching circuit 20 modulates the i _s in the carrier. The control of the inverter 9 by inputting the PWM gate signal to the gate drive circuit 16 is as described above. When there is a CB release signal, the carrier frequency has the same cycle as the power supply frequency,
PWM signal by the i _s becomes one of the square wave pulses width modulation, controls the inverter 9.

[0005]

As described above, according to the present invention, the switching loss is reduced as a rectangular wave output in the steady state, and only the voltage fluctuation caused by the rush current during the transient fluctuation (such as switching on the train) is controlled by the PWM high-speed control. By doing so, the instantaneous voltage drop is suppressed. Further, when a steady state is reached, the switching loss is reduced by returning to a rectangular wave output. Accordingly, the efficiency of the inverter operation can be increased by suppressing the transient voltage fluctuation and reducing the total operation loss.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention in a block diagram.

FIG. 2 shows a PWM output waveform during a transition according to the present invention.

FIG. 3 shows a PWM output waveform in a steady state according to the present invention.

FIG. 4 is a block diagram showing a conventional static var compensator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power supply 2 System impedance (XL) 3 Load 4 System bus 5 Load voltage detection PT 6 Load current detection CT 7 PT 8 Transformer 9 Inverter 10 Capacitor 11 System voltage constant control circuit 12 Power fluctuation control circuit 13 PLL (synchronous circuit) 14 Reactive current control circuit 15 PWM gate control circuit 16 Gate drive circuit 17 Inverter current detection CT 18, 19 Adder 20 PWM carrier frequency switching circuit 21 Inverter generated reactive power detection circuit

Claims (1)

(57) [Claims] 1. A static type in which an inverter is connected to a system bus in order to suppress a voltage fluctuation of a system bus, and a leading or lagging current flows from the inverter into the bus to suppress the voltage fluctuation of the bus. In the reactive power compensator, a circuit for obtaining a load reactive power signal from a system bus voltage and a load current, a circuit for comparing a system voltage with a system voltage reference value to obtain a difference signal therebetween, and adding output signals from both circuits. A circuit for subtracting the output invalid signal of the inverter from the added signal, a PWM gate control circuit for performing PWM control using the subtracted signal and a carrier signal, and a carrier frequency in the gate control circuit for a power supply frequency. A PWM carrier frequency switching circuit for switching to a high-speed carrier frequency by an external signal from a square wave of one half cycle; A static var compensator wherein an inverter is operated by introducing an output signal from a PWM control circuit to a gate drive circuit.