JPH03205872A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable uniformity of in-chip element characteristics through uniformity of the distribution of in-chip temperature due to power consumption and through fixation of power distribution by arranging dummy blocks provided with wirings which feed power to unused RAM macros. CONSTITUTION:In a RAM gate array type semiconductor integrated circuit device having a functional constitution which includes a logic circuit gate array 109 and a plurality of RAM macros 101-108 and does not use part 107, 108 of the RAM macros 101-108, dummy blocks 117, 118 provided with wirings which feeds power to the unused RAM macros 107, 108 are constituted. For example, RAM macros 101-106 are prepared to realize a necessary number of bits and words, while RAM blocks 111-116 each constituting one block by one macro are provided. Further, to realize the function of model unnecessary unused RAM macros 107, 108 are provided with RAM blocks 117, 118 with wirings for power feed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a gate array type semiconductor integrated circuit with a RAM having a gate array for a logic circuit and a plurality of RAM macros. [Prior art] A conventional gate array type semiconductor integrated circuit with RAM has a third
As shown in the figure, multiple RAM macros 301, 302, 303, 304, 30 are installed in order to realize the number of bits and words required for each product in individual product design.
5, 306 are arbitrarily switched by the wiring pattern.

At this time, RAM macro 3 that does not require any input/output signals
Regarding 07 and 308, the wiring pattern for power supply was generally not connected.

[Problem to be solved by the invention]

In recent years, as information processing devices such as computers have become more sophisticated, there has been a demand for shorter system cycle times. For this reason, so-called RAM-equipped gate array type semiconductor integrated circuits, which are equipped with a gate array for logic circuits and a plurality of RAM macros, are now popular. Generally speaking, RAM is equipped with a plurality of macros so that the number of bits, number of words, and other functional configurations can be changed arbitrarily for each type of RAM. For that purpose, RAM using a single macro or multiple macros
Multiple types of blocks (patterns for the wiring process, used to realize functional configurations such as the number of bits and number of words) are prepared in advance, and in the design of individual products, one selects and places them from among these. At this time, wiring patterns for power supply were not connected to RAM macros that did not require input/output signals, but as RAM blocks became larger-scale integration, the following problems arose. It started coming.

(A) Temperature distribution within the chip becomes non-uniform.

(B) Uneven voltage drop due to different current paths between used and unused macros (C) Due to the above reasons,
Non-uniformity of circuit characteristics.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has a dummy RAM block in which power supply wiring is connected to an unused block that no longer requires input/output signals when the number of bits and words constituting a desired product type is achieved. He is reprimanded for doing so. [Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram showing a first embodiment of the present invention.

RAM macros 101, 102, 103, 104, which are gate arrays with RAM, have a gate array 109 in the center of a semiconductor chip and eight RAM macros around it.
105 and 106 are provided to realize the required number of bits and words. R with one block (wiring pattern for realizing function) using one macro at the same time
AM blocks 111, 112, 113, 114, 115
, 116. RAM macros 107 and 108 are unused RAM macros that are unnecessary for realizing the functions of the product, and dummy RAM blocks 117 and 118 are provided therein with wiring groups for power supply. FIG. 2 is a layout diagram showing a second embodiment of the present invention.

This is a gate array with RAM that uses block configuration, with two RAM macros as one block. One RAM block 211 is formed by the RAM macros 201 and 202, and a dummy RAM block 212 is formed by the unused RAM macros 203 and 204.

〔Effect of the invention〕

As explained above, the present invention provides power supply by arranging dummy blocks to which wiring for power supply is connected even to unused RAM macros in individual types of gate array type semiconductor integrated circuits with RAM. By making the temperature distribution within the chip uniform due to consumption and making the voltage distribution constant, the characteristics of the elements within the chip can be made uniform, so even things that were previously defective can be repaired by adopting the present invention. effective. Furthermore, it is possible to average out variations in characteristics among various products, which is useful in securing the operating margin of the system.

[Brief explanation of drawings]

1 and 2 are layout diagrams showing first and second embodiments of the present invention, and FIG. 3 is a layout diagram showing an example of a conventional semiconductor integrated circuit. 10,20.30...LSI chip, 101,102
,103,104,105,106,201,202,
203, 204, 301, 302, 303, 304, 3
05.306...RAM macro, 107,108,2
03,204...Unused RAM macro, 109,20
5,309...gate array, 111,112,11
3,114,115,116,211...RAM block, 212...Dummy RAM block, 307.3
08...Unused RAM macro.

Claims (1)

[Scope of Claims] 1. In a gate array type semiconductor integrated circuit with a RAM having a functional configuration including a gate array for a logic circuit and a plurality of RAM macros and leaving a part of the RAM macros unused, A semiconductor integrated circuit comprising a dummy block provided with wiring for supplying power to a RAM macro. 2. The semiconductor integrated circuit according to claim 1, wherein each of the RAM macros comprises one block or a dummy block. 3. The semiconductor integrated circuit according to claim 1, wherein the dummy block is composed of two RAM macros.