JPH03201560A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce parasitic resistance of a power source line by forming a shunt of the power source line of a conductive layer equal to that of a grounding line or gate electrodes of MOS transistors for load. CONSTITUTION:Gate electrodes 14a to 17a, a grounding line 26, gate electrodes 12a, 13a of MOS transistors 12, 13 for load, active layers 37, 38 of the MOS transistors 12, 13 for load and a power source line 15 are formed of conductive layers of mutually different layers on a semiconductor substrate. A shunt 34 of the power source line 18 is formed of a conductive layer equal to that of the grounding line 26 or the gate electrodes 12a, 13a of the MS transistors 12, 13 for load. Therefore even if the active layers 37, 38 and the power source line 18 are made as thin as approximately 100 angstrom so that their sheet resistance is approximately 10<4>OMEGA/square, by making the shunt as thick as 1000 angstrom, composite sheet resistance of the power source line 18 and the shunt is reduced to approximately 2X10<2>OMEGA/square.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is referred to as a stacked CMO3-3RAM, in which a load MOS transistor of a flip-flop constituting a memory cell is stacked on a bulk transistor. This relates to semiconductor memory.

[Summary of the Invention] In the semiconductor memory as described above, the present invention reduces the area of the memory cell by forming a shunt of the power supply line with a conductive layer in the same layer as the ground line or the gate electrode of the load MOS transistor. Even though the conductive layer forming the power supply line is made thinner, the parasitic resistance of the power supply line can be lowered without increasing the size or complicating the manufacturing process.

[Conventional technology]

Complete CMO3-3 with memory cells as shown in Figure 3
In order to reduce the chip area of the RAM to be as small as that of a resistive load type MO3 SRAM, a PMO5 transistor 12.1 is used as a load for the flip-flop 11 that constitutes the memory cell.
3 is made up of thin film transistors, and this thin film transistor is used as a bulk transistor on the drive NMOS transistor 14 and 15 and on the transfer NMOS transistor 16.
．． The so-called stacked CMO3-
3RAM is being considered (for example, "Nikkei Microdevices J (1988, 9) P, 123-130)".

In such a stacked CMO3-3RAM, PMOS
An important point is to reduce the leakage current of transistors 12 and 13. As a method for realizing this, it is considered that a method of thinning the polycrystalline Si layer forming the active layer of the PMOS transistors 12 and 13 is considered to be effective.

[Problem to be solved by the invention]

By the way, in stacked CMOS-S RAM, P
Generally, the power source material 18 is also formed of the same polycrystalline Si layer as the polycrystalline Si layer forming the active layer of the MOS transistors 12, 13.

Therefore, if this polycrystalline 5iJi is formed into 71 films as described above, the electrical resistance of the power supply line 18 will increase, which is disadvantageous for high-speed operation and stability of the memory cell.

On the other hand, if an attempt is made to lower the resistance of the power supply vA18 by newly providing a conductive layer to solve this problem, the area of the memory cell will increase and the manufacturing process will become complicated.

[Means to solve the problem]

In the semiconductor memory according to the present invention, a driving MOS transistor 14.15 and a transfer MOS transistor 16.1
7, the grounding line 26, and the gate electrode 1 of the load MOS transistor 12.13.
2a, 13a, and the load MOS transistor 12.
13 active layers 37, 38 and power source &'i 18 are formed of conductive layers of different layers on the semiconductor substrate, and the ground line 26 or the gate electrode 12a of the load MOS transistor 12, 13, A shunt 34 of the power supply line 18 is formed by the conductive layer in the same layer as the conductive layer 13a.

[Effect]

In the semiconductor memory according to the present invention, the shunt 34 of the power supply line 18
is formed, but the driving MOS transistor 14.
Compared to the conductive layer on which the gate electrodes 14a" and 17a of the transfer MOS transistors 15 and 16 and 17 are formed, the conductive layer on which the shunt 34 is formed has generally more leeway in terms of layout. .

Further, the conductive layer in which the shunt 34 of the power supply MA18 is formed is originally the conductive layer in which the ground i26 or the gate electrodes 12a, 13a of the load MOS transistors 12.13 are formed, and the newly provided conductive layer It's not a layer.

〔Example〕

Hereinafter, the first and second embodiments of the present invention will be explained with reference to FIGS. 1 and 2.
This will be explained with reference to the figures.

FIG. 1 shows a first embodiment. In this first embodiment, the impurity diffusion regions 21a to 21g, which are the source/drain regions of the driving NMo5 transistor 14.15 and the transfer NMOS transistor 16.17, are
It is formed in a semiconductor substrate.

Gate electrodes 14a-173 of transistors 14-17 are formed of a first polycrystalline Si layer on an insulating film (not shown) on the semiconductor substrate. However, the gate electrodes 16a and 17a are part of the word line 22.

The gate electrode 14a connects to the impurity diffusion region 21 through a contact hole 23 formed in an insulating film on the semiconductor substrate.
connected to d. Further, the gate electrode 15a is connected to the impurity diffusion regions 21b and 2 through the contact holes 24.25.
Connected to 1f.

The gate electrodes 14a, 15a, the word line 22, and the surface of the semiconductor substrate are covered with an interlayer insulating film (not shown), and a ground YA 26 and conductive layers 27 and 28 are provided on the insulating crotch between the eyebrows.
is formed by the second polycrystalline Si layer.

The ground line 26 is connected to the impurity expansion region 21c etc. via a contact hole 31 etc. formed in the insulating film below the ground line 26. The conductive layers 27.28 are connected to the impurity diffusion regions 21g and 21e through the contact holes 32.33, respectively, and are connected to the impurity diffusion regions 21g and 21e, respectively.
They extend alternately from 21e to above the word line 22.

The ground wire 26, conductive layers 27, 28, etc. are covered with an interlayer insulating film (not shown), and on this interlayer insulating film, PMO
Gate electrodes 12a, 13a of S transistors 12.13
and the shunt 34 of the power supply line 18 are formed of the third polycrystalline Si layer.

By forming the gate electrodes 12a and 13a in this way from a polycrystalline St layer different from that of the gate electrodes 14a and 15a, it is possible to make the gate lengths different from each other, as is clear from FIG. can.

The gate electrodes 12a, 13a are connected to gate electrodes 14a, 15a, respectively, through contact holes 35, 36 formed in the glabella insulating film below them.

The gate electrodes 12a, 13a, the shunt 34, etc. are covered with a dielectric film (not shown), and on this gate insulating film, there is a power supply line 18 and a 1MOS connected to the power supply line 18.
The active JiJ37.38 of transistor 12.13 is
It is formed by a fourth polycrystalline Si layer.

The power supply line 18 is connected to the shunt 34 via contact holes 41, 42, etc. formed in the insulating film below the power supply line 18. The drain region of the active layer 37.38 is connected to the gate electrodes 13a, 12 through contact holes 43.44.
a, respectively.

The power supply line 18, active layers 37, 38, etc. are covered with a glabellar insulating film (not shown), and bit lines 45, 46 are formed from the A1 layer on this glabellar insulating film.

The bit lines 45 and 46 are respectively connected to the AII lines N27 and 28 on the word line 22 through contact holes 47 and 48 formed in the underlying insulating film.

In the first embodiment as described above, as is clear from FIG. 1, the word &? The shunt 3
4 is extended.

Therefore, even if the gate electrodes 12a, 13a of the 1MO3l-transistor 12.13 and the shunt 34 are both formed of the 31st to 5th polycrystalline Si layer, they are completely separated and the shunt 34 can function as a shunt for the power supply line 18.

Therefore, in order to reduce the leakage current of the 1MOS transistor 12.13, the active layer 37.3B and the power supply line 18 are thinned to a thickness of about 100 mm, so that the sheet resistance of these becomes about 10'Ω/unit. Also, the thickness of the shunt 34 is 10
00 people, the combined sheet resistance of the power supply line 18 and the shunt 34 decreases to about 2×10 2 Ω/port.

Even if the shunt 34 and the power supply line 18 extend approximately on the boundary line between the two memory cells, the bit line 45.46 is connected to the conductive Fi27.28.
5.46 and impurity diffusion N21g.

There will be no problem in connection with 21e.

In addition, in the above first embodiment, the PMOS transistor 1
2.13 gate electrodes 12a, 13a and shunt 34 are formed from the third layer of polycrystalline Si layer, power supply line 18 and active layer 3
Although 7.38 and 7.38 are formed using the fourth polycrystalline Si layer, these may be reversed.

FIG. 2 shows a second embodiment. In this second embodiment, the shunt 34 of the power line 18 is formed of the same 2Nth polycrystalline Si layer as the ground 126, and the shunt 34 and the power line 18 extend over the word line 22. 1, except that the shunt 49 of the word line 22 and the shunt 50 of the ground line 26 are formed by the second 11 layer above the bit line 45, 46. This embodiment has substantially the same configuration as the first embodiment shown in FIG.

However, bit lines 45 and 46 are connected to contact holes 32 and 33.
are directly connected to the impurity diffusion regions 21g and 21e, respectively. Further, the power supply line 18, the word line 22, the ground line 26, and these shunts 34, 49, 50 are connected to each other in the region between the memory cells for every several memory cells.

In the second embodiment as well, since the power supply line 18 is provided with the shunt 34, it is possible to make the active layer 37, 38 and the power supply cotton 18 thin in order to reduce the leakage current of the PMO3I transistor 12, 13. , the acoustic sheet resistance between the power supply line 18 and the shunt 34 is low.

Note that the shunt 49.5.0 of the word line 22 and ground line 26
It is also possible to form these shunts 49.50 from a refractory metal layer and to place these shunts 49.50 below the bit lines 45.46. Moreover, the shunt 34 of the electric A-line 18 and the shunt 49 of the word line 22 may be interchanged.

〔Effect of the invention〕

In the semiconductor memory according to the present invention, the conductive layer in which the power line shunt is formed generally has a margin in the layout, so the area of the memory cell does not increase, and the power line shunt is formed. Since the conductive layer is not a newly provided conductive layer, the manufacturing process is not complicated, and even if the conductive layer forming the power line is thinned, the parasitic resistance of the A-line is low.

[Brief explanation of drawings]

1 and 2 are plan views of the first and second embodiments of the present invention, respectively, and FIG. 3 is a complete CMOS to which the present invention can be applied.
FIG. 2 is an equivalent circuit diagram of a memory cell of SRAM. In addition, in the symbols used in the drawings, 11
-Flip-flop I2, I3--------・-・・-
-----PMO3) Ranjisk 12 a, l 3
a --------Gate electrode 14.15.16.17 4a1 18-...26-.4 37,3. -----NMOS transistor low a, 17a Gate electrode power supply line ground line shunt active layer 15a, 1 8- ・----------

Claims (1)

[Claims] A flip-flop is constituted by a pair of drive MOS transistors to which a ground line is connected and a pair of load MOS transistors to which a power supply line is connected. In a semiconductor memory in which a memory cell is constituted by a MOS transistor for driving, a gate electrode of each of the driving MOS transistor and a transfer MOS transistor, the ground line, a gate electrode of the load MOS transistor, The active layer of the load MOS transistor and the power supply line are formed of conductive layers in different layers on a semiconductor substrate, and the conductive layer is in the same layer as the ground line or the gate electrode of the load MOS transistor. A semiconductor memory in which a shunt of the power supply line is formed by.