JP2000174143A - Static ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the dimension of a static RAM in the direction of data lines and to reduce the capacity of the data lines and, in addition, to increase the driving speed of the RAM. SOLUTION: A static RAM is provided with NMOS elements N1 and N2 for drive, NMOS elements N3 and N4 for transfer, and an element for load on the main surface of a semiconductor substrate. The NMOS elements N1 and N2 and N3 and N4 are formed in the direction of word lines and metallic word lines are connected to gate electrodes in elements (cells).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a static RA
M (SRAM), especially CMOS (complementar
y metal oxide semiconductor) type static RAM
The present invention relates to a technology capable of reducing the capacity of a data line and increasing the speed.

[0002]

2. Description of the Related Art A conventional CMOS SRAM (static RAM) is used.
FIG. 7 shows an example of andom access memory). In FIG. 7, reference numeral 1 denotes an active region, on which a filled oxide film is formed. Reference numeral 2 denotes a gate electrode layer, on which a gate insulating film is formed. Reference numeral 3 denotes a region directly connecting the gate electrode and the active region. In the process of silicidation of both surfaces of the active region and the gate electrode, only the region 3 is connected by a silicide layer by removing a spacer formed on a side surface of the gate electrode.

[0004] Reference numeral 4 denotes a contact hole for opening an interlayer insulating film. After the contact hole 4 is formed, the first metal wiring layer is connected to the base through the contact hole 4. N1, N2, N3, N4 are NMOS
(N channel metal oxidesemiconductor) element, P
1 and P2 are PMOS (P-channel metal oxid
e semiconductor) element. Usually, N1 and N2 are referred to as driving (driver) NMOS elements, and N3 and N4 are referred to as transfer (transfer) NMOS elements.

FIG. 8 shows a P-well (Pwe11), an N-well (Nwe11) and a p-well in the CMOS SRAM shown in FIG.
FIG. 4 is a diagram showing a formation (doping) region of a + layer and an n + layer;
5 is a region where a P well and an n + layer are formed, and 6 is an N
This is a region where the well and the p + layer are formed. That is, the region 5 is formed with an NMOS device, and the region 6 is formed with a PMOS device.

FIG. 9 is a view showing a metal wiring region in the CMOS type SRAM shown in FIG. 7, in which 7 is a first metal wiring layer, and 8 is a first metal wiring layer on the first metal wiring layer 7.
Reference numeral 9 denotes a second metal wiring layer, W denotes a word line, and D1 and D2 denote data lines.

A large-capacity high-density and low-power capacitor is demanded at the same time by a resistance load type cell in which a resistance element made of a polycrystalline (poly) silicon layer is used as a load.

[0007] The technology relating to the CMOS type and the resistive load type SRAM is described in, for example, “Introduction to Ultra-LSI” published by Kyushu Kagaku Co., Ltd. on May 30, 1992, from page 21 of “Basics of MOS Integrated Circuit”. Page 23, Page 61 to 6
It is described on page 6.

[0008]

SUMMARY OF THE INVENTION As a result of studying the above prior art, the present inventor has found the following problems.

The conventional CMOS SRAM has a feature that the dimension in the word line direction is small but the dimension in the data line direction is large. In this case, the word line is formed of silicide, and its resistance is as large as 5 ohm (Ω) / □, so that it is suitable for reducing the length of the word line to reduce the word line delay. On the other hand, since the dimension in the data line direction is long and the interval between adjacent data lines is small, there is a problem that the data line capacity increases.

An object of the present invention is to provide a technique which can reduce the size in the data line direction and the data line capacity in a static RAM.

Another object of the present invention is to provide a static RAM.
It is an object of the present invention to provide a technique capable of speeding up the operation of the device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A driving NMO is provided on the main surface of the semiconductor substrate.
A static RAM having an S element, a transfer NMOS element, and a load element, wherein the driving NMOS element and the transfer NMOS element are formed in a word line direction, and the word line is formed in a gate electrode in the element (cell). Connected to.

(2) An NMO for driving is provided on the main surface of the semiconductor substrate.
A CMOS static RAM having an S element, a transfer NMOS element, a load PMOS element, and a field insulating film (element isolation region) between the NMOS element and the load PMOS element; An NMOS element and a transfer NMOS element are formed in a word line direction, and the word line is connected to a gate electrode in the element (cell).

(3) The load element is a load PMOS.
An element or a resistance load element.

Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.

In all the drawings for describing the embodiments, parts having the same functions are given the same reference numerals, and their repeated explanation is omitted.

[0019]

(Embodiment 1) FIG. 1 is a plan view showing a schematic structure of a cell (element) of a CMOS type SRAM according to an embodiment of the present invention. An (or N-type) silicon substrate is used. 1
Reference numeral 1 denotes an active region, on which a filled oxide film is formed. Reference numeral 12 denotes a gate electrode, on which a gate insulating film (gate oxide film) is formed.
Reference numeral 13 denotes a region for directly connecting the active region 11 and the gate electrode 12. In the process of silicidizing both surfaces of the active region 11 and the gate electrode 12, only the region 13 is connected by a silicide layer by removing a spacer formed on a side surface of the gate electrode.

Reference numeral 14 denotes a contact hole formed in the first interlayer insulating film, and thereafter, a first-layer metal wiring (for example,
(Using Al or Cu) is connected to the base through the contact hole 14. N1, N2, N3 and N4 are N-channel MOS devices (hereinafter referred to as NMOS), respectively, and P1 and P2 are P-channel MOS devices (hereinafter referred to as PMOS), respectively. Usually, N1 and N2 are referred to as drive (driver) NMOSs, and N3 and N4 are referred to as transfer (transfer) NMOSs.

FIG. 2 shows the formation (doping) region of the P-type well (hereinafter, referred to as Pwell), the N-type well (hereinafter, referred to as Nwell), the p + layer, and the n + layer in the CMOS SRAM shown in FIG. 15 is a formation region of a Pwell and n + layer, and 16 is a formation region of an Nwell and p + layer. That is, the region 15 is an NMOS, the region 16
Are formed with PMOS.

FIG. 3 is a diagram showing a metal wiring region in the CMOS type SRAM shown in FIG. 1, and FIG.
It is sectional drawing cut | disconnected by the -A 'line. Reference numeral 17 denotes a first-layer metal wiring (for example, using Al or Cu);
A through hole for opening the second interlayer insulating film on the metal wiring 17 of the layer, 19 is a metal wiring of the second layer (for example, using Al or Cu), and W is a metal wiring 17 of the first layer. , D1 and D2 are data lines made of a second-layer metal wiring 19, 20 is a filled oxide film (element isolation region), 17A is an electrode (pad), 17B is a word line, 17C is a power supply line, 21 Is a first interlayer insulating film, 22 is a second interlayer insulating film, and 23 is a W plug.

As shown in FIGS. 1 to 4, a CMOS SRAM cell (element) according to the present embodiment comprises a Pwell 15A and an n + on a semiconductor substrate (P-type silicon substrate) 10.
The region (doping region) 15 where the layer 15B is formed and N
doping region 1 in which well 16 and p + layer 16B are formed
6 are formed. An N-type gate electrode 15D is formed on the n + layer 15B with a gate insulating film (gate oxide film) 15C interposed therebetween, and a gate insulating film (gate oxide film) 16C is formed on the p + layer 16B. A P-type gate electrode 16D is formed interposed therebetween. A first-layer metal wiring 17 is formed thereon with a first interlayer insulating film 21 interposed therebetween, and a second-layer metal wiring 19 is formed thereon with a second interlayer insulating film 22 interposed therebetween. Have been. The n + layer 15
The B and p + layers 16B are connected to the electrodes (pads) 17A by W plugs 23 through the through holes 14 in the first interlayer insulating film 21 respectively. These electrodes (pads) 17A are connected to the data lines D1 and D2 formed of the second metal wiring layer 19 by the W plug 23 through the through hole 18 opening the second interlayer insulating film 22.
2 respectively.

The first-layer metal wiring 17 includes:
Electrode (pad) 17A, word line 17B, power supply wiring 17
C is formed. That is, on the main surface of the semiconductor substrate 10, a driving NMOS element, a transfer NMOS element, a load PMOS element,
Field insulating film (element isolation region) 20 between S element
Wherein the driving NMOS element and the transfer NMOS element are formed in the word line direction, and the word line 17B which is the first-layer metal wiring 17 is provided in the element (cell). It is connected to the gate electrode 15A (not shown in FIG. 4).

The data lines D1 and D2 formed in the second metal wiring layer 19 are connected to the electrodes (through the W plugs 23) through the through holes 18 opening the second interlayer insulating film 22. Pad 17A. The electrode (pad) 17A is connected to the n + layer 15B or the p + layer 16B through a through hole 14 in the first interlayer insulating film 21 and a W plug 23, respectively.

Table 1 shows an example of the dimensions (examples in the case of the 0.2 μm rule) of each part of the element (cell) of the CMOS type SRAM of the present embodiment.

[0027]

Table 1 Conventional cell Present invention Vertical 3 μm 2 μm Horizontal 2 μm 3 μm Data line width 0.5 μm 0.5 μm Data line length 3 μm (per cell) 2 μm (per cell) Adjacent data line 0.4 μm 0.5 μm Hereinafter, the outline of the method of manufacturing the CMOS SRAM of the present embodiment will be briefly described with reference to FIG.

As shown in FIG. 5A, a filled oxide film (element isolation region) 20 is formed on a silicon substrate (Si substrate) 10. For example, a trench is formed in the Si substrate 10, a CVD (chemical vapor deposition) oxide film is embedded, and a CMP (chemical mechanical polishin) is formed.
It is formed by flattening in g).

Next, as shown in FIG. 5B, Pwells 15A and Nwells 16A (well regions) are formed by ion implantation. Thereafter, as shown in FIG. 5C, the gate oxide films 15C and 16C made of a silicon oxide film are formed.
Is formed, and an N-type gate electrode 15D and a gate oxide film 16C made of polysilicon are formed thereon.

Next, as shown in FIG. 6A, an n + diffusion layer 15B and a p + diffusion layer 16B are formed by ion implantation, and then, as shown in FIG. A silicide (for example, using cobalt (Co) silicide) 15D2 is formed. Then, FIG.
As shown in FIG. 3, a second interlayer insulating film (for example, using phosphor silicate glass: PSG) 21 is formed on the side spacers 15D1 and the silicide 15D2, and a first metal wiring layer is formed thereon. Then, the first metal wiring layer is patterned to form electrodes (pads) 17A, word lines 17B,
And a power supply wiring 17C.

The electrode (pad) 17A, word line 17
B, a second interlayer insulating film 22 is formed on the power supply wiring 17C, a second metal wiring layer is formed thereon, and is patterned to form a second metal wiring 19 as a second metal wiring 19. Form lines D1 and D2.

As described above, the CMO of this embodiment
According to the S-type SRAM, the driving (driver) NMOS
And a transfer (transfer) NMOS are formed in the direction of the word line W, and the word line W is connected to the gate electrode 15D or 16D in the element (cell) to reduce the size in the direction of the data lines D1 and D2. Can be
In addition, the capacity of the data line W can be reduced. Thereby, the operation of the static RAM can be made faster.

It goes without saying that a resistance load element may be used instead of the load PMOS.

As described above, the present invention has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and may be variously modified without departing from the gist of the present invention. Of course.

[0035]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

According to the static RAM of the present invention, the driving (driver) NMOS and the transfer (transfer) N
A MOS driver NMOS and a transfer NMOS are formed in the direction of a word line, and the word line is a semiconductor element (cell).
By connecting to the gate electrode inside, the dimension in the direction of the data line can be reduced, and the capacitance of the data line can also be reduced. Thereby, the operation of the static RAM can be made faster.

[Brief description of the drawings]

FIG. 1 is a CMOS type SRA according to an embodiment of the present invention.
FIG. 2 is a plan view showing a schematic configuration of an M cell (element).

FIG. 2 shows a P-type well (Pwell), an N-type well (Nwell), a P + layer, and the like in the CMOS SRAM shown in FIG.
It is a figure which shows the formation (doping) area | region of an N + layer.

FIG. 3 is a diagram showing a metal wiring region in the CMOS SRAM shown in FIG. 1;

FIG. 4 is a cross-sectional view taken along line A-A 'of FIG.

FIG. 5 is a cross-sectional view of each step for explaining the method for manufacturing the CMOS SRAM of the embodiment.

FIG. 6 is a cross-sectional view of each step for explaining the method for manufacturing the CMOS SRAM of the embodiment;

FIG. 7 shows a conventional CMOS SRAM (static random access memory).
FIG. 3 is a plan view showing an example of access memory).

FIG. 8 is a diagram showing formation (doping) regions of a P-well (Pwell), an N-well (Nwell), a p + layer, and an n + layer in the CMOS SRAM shown in FIG. 7;

9 is a diagram showing a metal wiring region in the CMOS SRAM shown in FIG. 7;

[Explanation of symbols]

Reference Signs List 10: P-type semiconductor substrate (P-type silicon substrate), 11: Active region, 12: Gate electrode layer, 13: Region for directly connecting active region and gate electrode, 14: Contact for opening second interlayer insulating film Holes, N1, N2, N
3, N4 ... NMOS element, P1, P2 ... PMOS element,
15: formation region of Pwell and N + layers; 16: formation region of Nwell and P + layers; 17: first metal wiring layer;
17A: electrode (pad), 17B: word line, 17C ...
Power supply wiring, 18: first through hole above first-level metal wiring, 19: second-level metal wiring layer, W: word line, D1, D2: data line, 10: P-type semiconductor substrate ( Silicon substrate), 15A ... Pwell, 15B ... p + diffusion layer,
15C, 16C: gate oxide film, 15C, 15D: N-type gate electrode, 16A: Nwell, 16B: n + diffusion layer, 1
5D: P-type gate electrode, 15D1, 16D1: side spacer, 15D2, 16D2: silicide, 20: filled oxide film (element isolation region), 21: first interlayer insulating film, 22: second interlayer insulating film, 23 ... W plug.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masataka Minami 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Masayuki Kojima Josuihoncho, Kodaira-shi, Tokyo 5-20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Business Headquarters (72) Kinya Mitsumoto Inventor 5-20-1, Kamisumihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Co., Ltd. Semiconductor Business Headquarters 5F048 AB01 AC03 BE03 BG14 CC19 5F083 BS02 BS14 GA03 JA35 JA36 JA37 LA02 LA12 MA06 MA19 NA01 PR40

Claims (2)

[Claims] 1. A static RAM having a driving NMOS element, a transfer NMOS element, and a load element on a main surface of a semiconductor substrate, wherein the driving NMOS element and the transfer NMOS element are arranged in a word line direction. A static RAM formed, wherein the word line is connected to a gate electrode in an element (cell). 2. A driving NMOS element, a transfer NMOS element, a load PMOS element, and a driving NMOS element on a main surface of a semiconductor substrate.
A CMOS static RAM having a field insulating film (element isolation region) between the NMOS element and a load PMOS element, wherein the driving NMOS element and the transfer NMOS element are formed in a word line direction, A static RAM, wherein a line is connected to a gate electrode in an element (cell).