JPH0320116B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In current television services, a scanning method called interlacing is used. That is,
One image (frame) is transmitted by two vertical scans (fields), and these scan lines are transmitted as many times as possible without causing flickering to the viewer's eyes in a limited frequency band. It was designed to try.

However, in the CCIR method, for example, the field frequency is 50 Hz, and flickering cannot be completely removed at this frequency, and flickering can be felt, especially on screens with high brightness.

In view of these points, the present invention attempts to prevent the above-mentioned flickering, which is called screen flicker, in the current television system. That is, in the present invention, a television signal transmitted in a one-frame, two-field interlaced manner is sequentially supplied to and stored in a one-field memory, and vertical scanning is performed at twice the speed. A first field formed by a vertical scan of the velocity is formed by every other horizontal scan line of the stored television signal, a second sub-field is formed by the remaining horizontal scan lines, and a second sub-field is formed by the remaining horizontal scan lines, resulting in four sub-fields. It displays one frame of video.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a signal from an antenna 1 is supplied to a video detection circuit 4 through a tuner 2 and a video intermediate frequency circuit 3, and the video signal is detected. This detected video signal is supplied to a random access memory (RAM) 5 having a storage capacity for one field. Furthermore, the video signal is supplied to the synchronization separation circuit 6, and the separated vertical and horizontal synchronization signals are sent to the RAM.
The signal is supplied to the control circuit 7. Further, the vertical synchronization circuit of the separation circuit 6 is supplied to the doubler circuit 8 to generate a signal with twice the frequency, and this signal is sent to the phase correction circuit 9.
is supplied to Furthermore, the horizontal and vertical synchronizing signals from the separation circuit 6 are supplied to a timing generation circuit 10 to generate a signal at a predetermined timing, which will be described later. This signal is supplied to the phase correction circuit 9, and the corrected signal is supplied to the RAM control circuit 7. Further, a horizontal synchronizing signal from the separation circuit 6 is supplied to a clock generation circuit 11, and a clock signal of the timing of picture elements in the generated video signal is supplied to a control circuit 7. The signal from this control circuit 7 is the RAM 5
is supplied to perform writing and reading, which will be described later. This read signal is supplied to the picture tube 13 through the video signal processing circuit 12.

Further, a horizontal synchronizing signal from the separation circuit 6 is supplied to the deflection coil 15 through the horizontal output circuit 14. Also, the signal from the correction circuit 9 is transmitted to the vertical output circuit 1.
6 to the deflection coil 15.

In this circuit, the horizontal deflection is performed at the same speed as the detected signal, while the vertical deflection is performed at twice the speed.

In FIG. 2, for example, if the video signal of the upper half of the odd field is stored at the address in the upper half of RAM 5 at the middle point of the odd field of the original video signal, then from this point onwards, the uppermost address of RAM 5 is stored. At the same time that reading starts from
The video signals of the lower half of the odd field are sequentially written to the addresses of the lower half of the RAM 5. In this case,
Reading is performed for every other horizontal scanning line address (indicated by ◯ or △) of the stored video signal (indicated by an arrow). Therefore, the read address gradually approaches the write address, and the write address and read address coincide at the end of the odd field. The video signal of the first sub-field is formed by the signals of every other horizontal scanning line read during this time, and the signals of the remaining horizontal scanning lines are stored in every other address of the RAM 5. .

Furthermore, at the start of the even field, RAM5
At the same time, the video signal of the first horizontal scanning line of the even field is written to the uppermost address. Thereafter, every other address in the RAM 5 is sequentially read out, and at the same time, the signals of the even field are sequentially written to all addresses, and the video signal of the second sub-field is written in the remaining horizontal scanning lines until the point in the center of the even field. is formed, and the video signal of the upper half of the even field is written to the address of the upper half of the RAM 5.

In the same manner, video signals of the third and fourth sub-fields are formed using the signals of the even-numbered fields.
When the fourth subfield is formed, RAM5
The video signal of the upper half of the odd field is stored at the address in the upper half, and the state is returned to the above-mentioned initial state.

Therefore, the video signals of every other horizontal scanning line of the odd-numbered field are read out to the first subfield, the video signals of the remaining horizontal scanning lines are read out to the second subfield, and the third, The video signal of the even field is similarly read out to the fourth subfield. This signal is passed through the processing circuit 12 to the picture tube 1.
3.

Furthermore, a signal with twice the frequency of the vertical synchronizing signal is formed, and the horizontal scanning position of the first sub-field described above is equal to every other horizontal scanning position including the top of the odd-numbered fields as shown in FIG. The horizontal scanning position of the second sub-field is made equal to the remaining horizontal scanning position of the odd-numbered field as shown in FIG. The phase of the signal is corrected to equal similar horizontal scan positions.

Therefore, the vertical deflection is doubled, the phase is corrected as described above, and every other horizontal scanning line is read out, so that in each of the first to fourth sub-fields, as shown in FIG. Horizontal scanning lines of ~ are displayed, and one frame of video is displayed.

In this way, television signals are displayed, but according to the present invention, the field frequency is doubled, so even in the CCIR system, for example, the field frequency is doubled.
Hz, and no surface flicker occurs at all.

Furthermore, since the deterioration of vertical resolution due to surface flicker (Kelf actor) is eliminated, the vertical resolution of the screen is improved.

In addition, the storage capacity of random access memory is 1
Since a field is sufficient, the memory capacity is small.

Note that the present invention is applicable not only to the CCIR system but also to other television systems such as the NTSC system.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of an example of the present invention, Figures 2 and 3.
The figure is a diagram for explaining the same. 5 is a random access memory, 7 is a RAM control circuit, and 18 is a doubling circuit.

Claims (1)

[Claims] 1. Input television signals transmitted in a 1-frame, 2-field interlaced manner are sequentially supplied to a field memory and stored, and vertical scanning is performed in 2 fields.
a first sub-field formed by vertical scanning at twice the speed is formed by every other horizontal scanning line of the stored television signal;
The horizontal scanning position of the sub-field is formed by the remaining horizontal scanning lines, and the above-mentioned one frame of video is displayed in the four sub-fields, and the display of the first to fourth sub-fields is based on the above-mentioned input. A television receiver that doubles the vertical frequency without changing the horizontal frequency by performing deflection correction to maintain the interlace relationship of the television signal. 2. The television receiver according to claim 1, wherein the field memory is constituted by a random access memory having a storage capacity for one field that can be read and written at the same time.