JPH0320075A - Manufacture of programmable element - Google Patents

Manufacture of programmable element

Info

Publication number
JPH0320075A
JPH0320075A JP1155427A JP15542789A JPH0320075A JP H0320075 A JPH0320075 A JP H0320075A JP 1155427 A JP1155427 A JP 1155427A JP 15542789 A JP15542789 A JP 15542789A JP H0320075 A JPH0320075 A JP H0320075A
Authority
JP
Japan
Prior art keywords
films
oxide
nitride
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1155427A
Other languages
Japanese (ja)
Other versions
JPH0831563B2 (en
Inventor
Ichiro Matsuo
一郎 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP1155427A priority Critical patent/JPH0831563B2/en
Publication of JPH0320075A publication Critical patent/JPH0320075A/en
Publication of JPH0831563B2 publication Critical patent/JPH0831563B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To avoid the concentration of an electric field and stabilize the dielectric breakdown voltage by adopting structure that the thickness of insulating films changes gradually at the ends of program sections. CONSTITUTION:A P-type semiconductor substrate 11 is separated into a plurality of regions by field insulating films 12, and N<+>-type diffusion layers 13 to be the lower electrodes of programmable elements are formed in the separated regions. Subsequently, nitride silicon films 14 are formed on parts of the diffusion layers 13, and oxide films 15 and oxide nitride films 16 are formed by oxidizing the surfaces of the diffusion layers 13 and nitride silicon films 14 in an oxidizing atmosphere. Then, the laminates of the oxide nitride films 16 with the nitride silicon films 14 make program sections 17. When the upper electrodes 18 are made out of polycrystalline silicon films after that, the oxide films 15 become to have structure being such that their film thickness increases gradually at the ends of the program sections 17. This avoids the concentration of an electric field and makes it possible to obtain stable dielectric breakdown voltage.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路に組み込1れた電気的にプロ
グラム可能なプログラマブル素子の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing an electrically programmable device incorporated in a semiconductor integrated circuit.

従来の技術 半導体集積回路のうち,使用者が購入した後に内容を電
気的に書き込むことのできるいわゆるPROM( Pr
ogrammable  ROM)は望む内容のROM
(Read Only Memory)がただちに得ら
れるためにひろく用いられている。
Among conventional semiconductor integrated circuits, there are so-called PROMs (PROMs) into which the contents can be electrically written after purchase by the user.
ogrammable ROM) is a ROM with the desired content.
(Read Only Memory) is widely used because it can be obtained immediately.

1た論理回路の分野に釦いても、やはb使用者が購入し
た後に内容を電気的に書き込むことのできるいわゆるP
LD( Programmable  LogicDe
vice  )が類似の目的のため用いられている。
Even if we are in the field of logic circuits, there is also so-called P, which allows the user to electrically write the contents after purchasing it.
LD (Programmable LogicDe
vice ) is used for similar purposes.

FROMやPLDを構或するためには外部から記憶内容
が電気的に書き込め、かつ電源を切ってもその記憶内容
が保持されるようなプログラマブル素子を用いる必要が
有る。
In order to construct a FROM or a PLD, it is necessary to use a programmable element that allows storage contents to be written electrically from the outside and that retains the storage contents even when the power is turned off.

従来,このようなプログラマブル素子の製造に好適な製
造方法は例えば以下に示すようなものであった。
Conventionally, a manufacturing method suitable for manufacturing such a programmable element has been, for example, as shown below.

第2図a ”− cは従来のプログラマブル素子の製造
方法を示す工程順断面図であう、これを参照して説明す
る。
FIGS. 2A to 2C are step-by-step cross-sectional views showing a conventional method of manufacturing a programmable device.

1ず第2図aに示すように、P型半導体基板1をフィー
ルド絶縁膜2によシ複数の領域に分離し、分離された領
域中にプログラマブル素子の下部電極となるN+型拡散
層3を形戒する。
1. As shown in FIG. 2a, a P-type semiconductor substrate 1 is separated into a plurality of regions by a field insulating film 2, and an N+-type diffusion layer 3, which will become a lower electrode of a programmable element, is formed in the separated regions. Admonish the formal precepts.

次に第2図bに示すように、拡散層3を熱的に酸化する
ことによう厚さ1 0 mm程度のプログラム用酸化膜
4を形成した後多結晶シリコン膜6を全面に戒長させる
Next, as shown in FIG. 2b, after thermally oxidizing the diffusion layer 3 to form a programming oxide film 4 with a thickness of about 10 mm, a polycrystalline silicon film 6 is formed over the entire surface. .

ついで第2図Cに示すように多結晶シリコン膜5の一部
を選択的にエッチング除去して上部電極61とする。
Then, as shown in FIG. 2C, a portion of the polycrystalline silicon film 5 is selectively etched away to form an upper electrode 61.

この後,通常の半導体集積回路の製造工程にしたがって
拡散層3および上部電極61のそれぞれに対する電気的
接続が形成される。
Thereafter, electrical connections to each of the diffusion layer 3 and the upper electrode 61 are formed according to a normal semiconductor integrated circuit manufacturing process.

プログラミングは上部電極61と拡散層3との間に適当
な電圧を印加し、酸化膜4の絶縁を破壊することによう
行われる。
Programming is performed by applying an appropriate voltage between the upper electrode 61 and the diffusion layer 3 to break down the insulation of the oxide film 4.

発明が解決しようとする課題 最近の半導体集積回路の製造にかいては、加工寸法や形
状の精度を高めるためにいわゆるドライ・エッチング法
が用いられることが一般的であるが,以上に示したよう
な従来のプログラマブル素子の製造方法では、上部電極
61をドライ・エッチングにより加工しようとすると、
その下地となる酸化膜4の膜厚が10mm程度と薄いた
めエッチングが拡散層3に1で達しやすく、拡散層3が
損傷を受け、結果として接合の漏れ電流が発生しやすい
という課題がある。
Problems to be Solved by the Invention In recent manufacturing of semiconductor integrated circuits, it is common to use so-called dry etching methods to improve the accuracy of processing dimensions and shapes. In the conventional method of manufacturing a programmable element, when attempting to process the upper electrode 61 by dry etching,
Since the thickness of the underlying oxide film 4 is as thin as about 10 mm, etching easily reaches the diffusion layer 3, causing damage to the diffusion layer 3, resulting in a problem in that leakage current at the junction is likely to occur.

さらに上部電極61の端の部分では電圧を印加した際に
電界が集中するため酸化膜4が本来の絶縁破壊電圧より
も低い電圧で破壊されてしまうという課題もある。
Furthermore, since the electric field is concentrated at the end portion of the upper electrode 61 when a voltage is applied, there is also the problem that the oxide film 4 is broken down at a voltage lower than the original dielectric breakdown voltage.

課題を解決するための手段 上記のような課題を解決するための本発明のプログラマ
ブル素子の製造方法は,下部電極となる半導体基板上の
プログラム部分となる一部分に窒化シリコン膜層を含む
絶縁膜を形成する工程と,酸化する工程と、前記絶縁膜
の表面を完全に覆う上部電極を形成する工程とを含むも
のである。
Means for Solving the Problems In order to solve the above-mentioned problems, the method for manufacturing a programmable element of the present invention includes forming an insulating film containing a silicon nitride film layer on a portion of the semiconductor substrate that will become the lower electrode and will become the program area. The method includes a step of forming an upper electrode, an oxidizing step, and a step of forming an upper electrode completely covering the surface of the insulating film.

作  用 本発明のプログラマブル素子の製造方法では,プログラ
ムされる部分以外の絶縁膜の膜厚が厚くできるため上部
電極のエッチング時に工程上の余裕が十分取れる。1た
プログラム部分の端では絶縁膜の厚さが滑らかに変化す
るため電界の集中が無く安定した絶縁破壊電圧が得られ
る。
Function: In the method for manufacturing a programmable element of the present invention, the thickness of the insulating film other than the portion to be programmed can be increased, so that sufficient margin can be taken in the process when etching the upper electrode. Since the thickness of the insulating film changes smoothly at the end of the programmed portion, there is no concentration of electric field and a stable dielectric breakdown voltage can be obtained.

実施例 本発明のプログラマブル素子の製造方法の一実施例につ
いて、第1図awdを参照して説明する。
Embodiment An embodiment of the method of manufacturing a programmable element according to the present invention will be described with reference to FIG.

筐ず第1図aに示すように,P型半導体基板11をフィ
ールド絶縁膜12により複数の領域に分離し、分離され
た領域中にプログラマブル素子の下部電極となるN+型
拡散層13を形戒する。
As shown in FIG. 1a, a P-type semiconductor substrate 11 is separated into a plurality of regions by a field insulating film 12, and an N+-type diffusion layer 13, which will become the lower electrode of the programmable element, is formed in the separated regions. do.

次に第1図bに示すように,拡散層13上の一部に膜厚
1 0 n m程度の窒化シリコン膜14を周知の曳フ
ォトエッチング等の方法によう形成する。
Next, as shown in FIG. 1B, a silicon nitride film 14 having a thickness of about 10 nm is formed on a portion of the diffusion layer 13 by a well-known method such as photo-etching.

この窒化シリコン膜14は膜厚が薄いため下地の拡散層
13に損傷を与えることなくエッチングすることができ
る。また断面形状はさほど重要でないので下地に対する
選択比の大きいウェット・エッチングを行うこともでき
る。
Since this silicon nitride film 14 is thin, it can be etched without damaging the underlying diffusion layer 13. Further, since the cross-sectional shape is not so important, wet etching with a high selectivity to the underlying layer can be performed.

ついで第1図Cに示すように、soot:程度の温度の
酸化雰囲気中で拡散層13かよび窒化シリコン膜140
表面を酸化し,酸化膜16かよび酸化窒化@16を形戒
する。この酸化の寡に酸化膜16の膜厚が100nm程
度になるような条件下で行うと,拡散層13の酸化速度
は低不純物濃度の場合に比して3倍程度と大きく、1た
窒化シリコン膜14の酸化速度は非常に小さいため、酸
化窒化lIi16の膜厚は1〜2nm程度となる。なか
、酸化窒化膜16と窒化シリコン膜14との積層がプロ
グラム部分17となる。
Then, as shown in FIG.
The surface is oxidized to form an oxide film 16 and an oxynitride @16. If this oxidation is performed under conditions such that the thickness of the oxide film 16 is about 100 nm, the oxidation rate of the diffusion layer 13 is about three times higher than when the impurity concentration is low. Since the oxidation rate of the film 14 is very low, the film thickness of the oxynitride lIi 16 is about 1 to 2 nm. Among them, the stacked layer of the oxynitride film 16 and the silicon nitride film 14 becomes the program portion 17.

次に第1図dに示すように、多結晶シリコン膜からなる
上部電極18を形成する。この時、上部電極18の端が
酸化膜16上に来るようにすれば、多結晶シリコン膜の
ドライ・エッチングに際して下地が損傷を受けることは
ない。また酸化@16はデログヲム部分17の端部に訃
いてその膜厚が徐々に増加するような構造になるため,
電界の集中が避けられ安定した絶縁破壊電圧が得られる
Next, as shown in FIG. 1d, an upper electrode 18 made of a polycrystalline silicon film is formed. At this time, if the end of the upper electrode 18 is placed on the oxide film 16, the underlying layer will not be damaged during dry etching of the polycrystalline silicon film. In addition, since the oxide @16 forms a structure in which it falls at the end of the derogom part 17 and its film thickness gradually increases,
Concentration of electric field is avoided and stable breakdown voltage can be obtained.

この後、通常の半導体集積回路の製造工程にしたがって
拡散層13および上部電極18のそれぞれに対する電気
的接続を形成すればよい。
Thereafter, electrical connections to each of the diffusion layer 13 and the upper electrode 18 may be formed according to a normal semiconductor integrated circuit manufacturing process.

なか、上記の実施例では説明の都合上プログラム部分1
7を酸化窒化膜16と窒化シリコン膜14との積層膜と
したが,これは実施例の構或に従う必要はなく,窒化シ
リコン膜の下に半導体基板11が酸化された酸化膜があ
ってもよい。
In the above embodiment, for convenience of explanation, program part 1 is
7 is a laminated film of an oxynitride film 16 and a silicon nitride film 14, but this need not follow the structure of the embodiment, and even if there is an oxide film where the semiconductor substrate 11 is oxidized under the silicon nitride film. good.

発明の効果 以上の様に,本発明のプログラマブル素子の製造方法で
は、プログラムされる部分以外の絶縁膜をデログヲム部
分の絶縁膜よりも厚くできるため、下地の半導体基板に
損傷が加わることがない。またプログラム部分の端部に
おいて絶縁膜の厚さが徐々に変化する構造となるため,
電界の集中がなく絶縁破壊電圧が安定する。その結果と
して,高性能,高信頼性のプログラマブル集積回路が得
られる。
Effects of the Invention As described above, in the programmable device manufacturing method of the present invention, the insulating film in the part other than the programmed part can be made thicker than the insulating film in the programmable part, so that the underlying semiconductor substrate is not damaged. Also, since the thickness of the insulating film gradually changes at the edge of the program area,
There is no concentration of electric field and the breakdown voltage is stable. The result is a programmable integrated circuit with high performance and high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a − dは本発明のプログラマブル素子の製造
方法の実施例を示す工程順断面図,第2図a〜Cは従来
例のプログラマブル素子の製造方法を示す工程順断面図
である。 11・・・・・・基板,12・・・・・・フィールド絶
縁膜,13・・・・・・N 型拡散層,14・・・・・
・窒化シリコン膜,16・・・・・・酸化膜、16・・
・・・・酸化窒化膜,17・・・・・・プログラム部分
、18・・・・・・上部電極。
FIGS. 1A to 1D are step-by-step sectional views showing an embodiment of the programmable element manufacturing method of the present invention, and FIGS. 2A to 2C are process-order sectional views showing a conventional programmable device manufacturing method. 11...Substrate, 12...Field insulating film, 13...N-type diffusion layer, 14...
・Silicon nitride film, 16...Oxide film, 16...
... Oxynitride film, 17 ... Program portion, 18 ... Upper electrode.

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜に電圧を印加して絶縁を破壊することによりプロ
グラムを行うプログラマブル素子の製造方法において、
下部電極となる半導体基板上のプログラム部分となる一
部分に窒化シリコン膜層を含む絶縁膜を形成する工程と
、該窒化シリコン膜をマスクとして前記半導体基板表面
を酸化すると同時に該窒化シリコン膜層の表面をも酸化
する工程と、前記絶縁膜の表面を完全に覆う上部電極を
形成する工程とを含むことを特徴とするプログラマブル
素子の製造方法。
In a method for manufacturing a programmable element that performs programming by applying voltage to an insulating film to break the insulation,
A step of forming an insulating film including a silicon nitride film layer on a part of the semiconductor substrate that will become a lower electrode and will be a program part, and oxidizing the surface of the semiconductor substrate using the silicon nitride film as a mask and simultaneously oxidizing the surface of the silicon nitride film layer. A method for manufacturing a programmable element, comprising the steps of: oxidizing the insulating film; and forming an upper electrode completely covering the surface of the insulating film.
JP1155427A 1989-06-16 1989-06-16 Manufacturing method of programmable element Expired - Lifetime JPH0831563B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1155427A JPH0831563B2 (en) 1989-06-16 1989-06-16 Manufacturing method of programmable element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1155427A JPH0831563B2 (en) 1989-06-16 1989-06-16 Manufacturing method of programmable element

Publications (2)

Publication Number Publication Date
JPH0320075A true JPH0320075A (en) 1991-01-29
JPH0831563B2 JPH0831563B2 (en) 1996-03-27

Family

ID=15605776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1155427A Expired - Lifetime JPH0831563B2 (en) 1989-06-16 1989-06-16 Manufacturing method of programmable element

Country Status (1)

Country Link
JP (1) JPH0831563B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1229552A1 (en) * 2001-02-02 2002-08-07 Sony Corporation One time programmable semiconductor nonvolatile memory device and method for production of same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1229552A1 (en) * 2001-02-02 2002-08-07 Sony Corporation One time programmable semiconductor nonvolatile memory device and method for production of same
US6583490B2 (en) 2001-02-02 2003-06-24 Sony Corporation One time programmable semiconductor nonvolatile memory device and method for production of same
US6800527B2 (en) 2001-02-02 2004-10-05 Sony Corporation One time programmable semiconductor nonvolatile memory device and method for production of same

Also Published As

Publication number Publication date
JPH0831563B2 (en) 1996-03-27

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