JPH03195215A - Dither circuit - Google Patents

Abstract

PURPOSE:To facilitate the adjustment of a signal level of a dither signal and to make a device employing the circuit small by constituting a dither circuit utilizing a CMOS transistor(TR) inverter whose input terminal connects to a low level power supply voltage in terms of AC and whose output terminal connects to an input stage of an A/D converter circuit. CONSTITUTION:A linear region is provided to a region of CMOS TR inverters A2, A3 in which a logic output transfers from an H level to an L level. The bias point is set to a point B in the middle (VDD/2) of the linear region. Then the input terminal of the inverter A2 connects to a low level power supply Vss via a coupling capacitor C3 to make the input voltage of the inverter A2 is 0V in terms of AC. Only the internal noise generated from the inverter A2 itself is amplified by the inverter A2. The inverter A3 amplifies the inputted white noise further and the result is outputted from an output terminal (d). The amplified white noise is fed to a band pass filter 8 as a dither signal SD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dither circuit used to suppress quantization noise generated during A/D conversion of a signal.

[Conventional technology]

DAT (Digital Audio Tape Recorder)
P CM (Pulse Code Module) such as
ation) In a recording device, an A/D conversion circuit is used to convert an input analog signal into a digital signal. In A/D conversion circuits, generation of quantization noise becomes a problem. Quantization noise has a strong correlation with the input analog signal and causes high-order harmonic distortion of the input analog signal.

This distortion is mixed into the recorded signal and appears as a harsh and unpleasant sound when the recorded signal is reproduced. A dither circuit is used to suppress this quantization noise. Dither circuit is A/D
A dither signal, which is random noise, is added to the input analog signal at the input stage of the conversion circuit to whiten periodic quantization noise.

FIG. 5 shows a conventional dither circuit. In Figure 5,
An input analog signal 81N from a line amplifier (not shown) is input to the input terminal 1. Input analog signal SIN
is applied to the adder 2, which adds the dither signal S from the dither generation circuit 7 to the input analog signal SIN. The dither generation circuit 7 has a Zener diode ZD as a dither signal S9 generation source. Thermal noise generated by passing a current through the Zener diode ZD via the resistor R3 is applied to the non-inverting input terminal of the operational amplifier A1 via the coupling capacitor C1. The operational amplifier At amplifies the input noise with a gain determined by the gain setting resistor R4, and outputs the amplified noise signal as a dither signal S to the bandpass filter 8 via the coupling capacitor C2. The bandpass filter 8 performs band limitation on the dither signal S, and outputs the dither signal S to the adder 2. The input analog signal SIN to which the dither signal S is added in the adder 2 is input to the filter 3. The low-pass filter 3 removes unnecessary signals above the upper limit of the reproduction frequency band of the input analog signal SIN, and sends the signal to the sample-and-hold circuit 4.

The sample and hold circuit 4 samples the continuously changing input analog signal SIN at a predetermined sampling frequency f8, and holds the sampled value of the input analog signal SIN for the time required for quantization in the A/D conversion circuit 5. do.

The sampled input analog signal SIN is input to the A/D conversion circuit 5. The A/D conversion circuit 5 quantizes each sample value of the input analog signal SIN according to the value, converts it into a digital signal, and outputs the digital signal to the digital filter 6. The digital filter 6 filters the digital data, removes unnecessary components including the dither signal S, and outputs the filtered data.

[Problem to be solved by the invention]

In the conventional dither circuit described above, the dither generation circuit 7 uses a Zener diode ZD, and is configured to amplify and output thermal noise generated from the Zener diode ZD using an operational amplifier A1.

However, the characteristics of Zener diode ZD are not necessarily -
There are variations, rather than uniformity. Therefore, it is necessary to adjust the signal level of the dither signal SD according to the variation. Furthermore, since the operational amplifier A+ is used, there are problems such as increased cost.

An object of the present invention is to provide a dither circuit that can generate a dither signal with a relatively simple configuration.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a dither circuit that adds a dither signal to an input signal of an A/D conversion circuit, in which an input terminal is connected to a low potential power supply voltage in an alternating current manner, and an output terminal is connected to a low potential power supply voltage. The configuration includes a dither generation circuit including a CMOS transistor inverter connected to the input stage of the A/D conversion circuit.

[Effect]

According to the present invention, since the input terminal of the CMOS transistor inverter is AC grounded, the white noise generated by the CMOS transistor inverter itself is transmitted to the CMOS transistor inverter.
8) The voltage is amplified to a predetermined voltage level by the amplification effect of the Lange inverter itself. The amplified noise signal is output as a dither signal and added to the input analog signal that is the input signal of the A/D conversion circuit. That is, CMOS
The transistor inverter takes advantage of the fact that it acts as a high-impedance linear amplifier in its linear operation region, and by using CMOSIC, which has less variation in characteristics between devices, a uniform dither signal S can be generated.

can be obtained, and the device can be made smaller.

〔Example〕

Next, preferred embodiments of the present invention will be described based on the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, an input analog signal S1. from a line amplifier (not shown) is input. is input to input terminal 1. In the adder 2, the dither signal S from the dither generation circuit 9 is added to the input analog signal SIN. Add. Adder 2 is configured using an operational amplifier or the like.

Input analog signal 5Ill to which dither signal S is added
is input to the low-pass filter 3. The low-pass filter 3 is composed of an active type analog low-pass filter using an operational amplifier, and has an attenuation characteristic as shown in FIG. 4 to remove unnecessary high frequency components.

Input analog signal S output from low-pass filter 3
IN is input to the sample hold circuit 4.

The sample hold circuit 4 converts the input analog signal S1° to a predetermined sampling frequency f8 (for example, 48K Hz).
) is sampled by n times (for example, 2 times) oversampling, and the sample value is sent to the A/D converter circuit 5.
The signal is held for the time necessary for the conversion time and is applied to the A/D conversion circuit 5. The A/D conversion circuit 5 quantizes the input sample value, converts it into a digital signal, and outputs the digital signal. The converted digital signal is extracted at a sampling frequency f8 or an oversampling frequency nfs, unnecessary components are removed, and the signal is output. The output digital signal S is sent to the recording section of the DAT, etc.

UT As shown in FIG. 2, the dither generation circuit 9 has two stages of CM
It is configured using an OS transistor inverter A2 and a CMOS transistor inverter A3. First stage CMOS
The transistor inverter A2 acts as a white noise generation source and an amplifier, and the CMOS transistor inverter A3 further amplifies the generated white noise to a predetermined level, and outputs the amplified signal to the bandpass filter 8 as a dither signal S. Acts as an amplifier.

The input terminal a of the CMOS transistor inverter A2 is connected to the low potential power supply ■88 via the coupling capacitor C3.
(or GND), and the output terminal of the CMOS transistor inverter A2 is connected to the input terminal C of the transistor inverter A3 (CMO3). C
The output terminal d of the MOS transistor inverter A3 is connected to the input terminal of the bandpass filter 8. A high-resistance feedback resistor R5 is connected between the input terminal a and the output terminal S, and a similarly high-resistance feedback resistor R6 is connected between the input terminal C and the output terminal d.

CMOS transistor inverter A2 consists of a PMOS transistor QPl and an NMOS transistor QN1. Similarly, CMOS transistor inverter A3 is PM
O8+- transistor QP2 and NMOS transistor QN
Consists of 2. The gate G of the PMOS transistor QP1 and the gate G of the NMOS transistor QN1 are commonly connected to each other and form an input terminal a. Output terminal is PMO
8) It is provided at the connection point between the source S of transistor QP1 and NMO8) D of transistor QN1. Input terminal C
is provided at a common connection point between the gate G of the PMOS transistor QP2 and the gate G of the NMOS transistor QN2. The output terminal d is provided at the connection point between the source S of the PMOS transistor QP2 and the drain D of the NMo5 transistor QN2.

PMO3) The drain D of the transistor QPl is supplied with a high-potential power supply (2), and the drain D of the PMOS transistor FUJI P2D is also supplied with a high-potential power supply (2).

Source S low potential side power supply of NMOS transistor QNl■
s8 (or GND), NMo5 transistor QN2
The source S of is also connected to the low potential side power supply VSS (GND).

The above CMOS transistor inverters A2 and A3 are
Although it is normally used as a logic gate, in this embodiment it is used as a high impedance linear amplifier. In FIG. 3, a CMOS transistor inverter A,
CMO] The transfer curve of Transis Fuji Inverter A3 is shown.

As can be seen from FIG. 3, each CMO3) range inverter ASA3 has a linear region in the region where the logic output transitions from the "H" level to the "L" level. ■ in this linear region. , /2, the CMOS transistor inverter A2 and CMOS transistor inverter A3 operate as a linear φ amplifier. Then, the input terminal a of the CMOS transistor inverter A2 is connected to the low potential power supply ■38 (or GND) via the coupling capacitor C3.
), the input voltage of CMOS transistor inverter A2 becomes 0 in AC terms, and at this time C
Only the internal noise (white noise) generated from the MOS transistor inverter A2 itself is amplified by the CMOS transistor inverter A2. This amplification gain is ■. .

At -5V, it is approximately 20dB. amplified to 0 The white noise is output from the output terminal to the input terminal C.

The CMO1h range inverter A3 further amplifies the input white noise by 20 dB) and outputs it from the output terminal d. This amplified white noise is sent to the bandpass filter 8 as a dither signal SD.

The reason for the existence of the Hunthus filter 8 is based on its relationship with the attenuation characteristics of the low-pass filter 3.

That is, the bandpass filter 8 has a passband determined by its center frequency and limits the frequency band of the dither signal S, but the center frequency fo is in the range of in relation to the sampling frequency f8. preferable. However, if the center frequency fo is set to the high frequency side, the signal level of the dither signal S will decrease due to the attenuation characteristics of the low-pass filter 3. To prevent this,
It becomes necessary to amplify again. However, the dither signal S.

Raising the signal level excessively will cause problems such as beats. Therefore, as shown in FIG. 4, the frequency corresponding to the level LM attenuated by 40 dB from the passband level L is fM, and the center frequency fo is 1·F s−f v.

Set it within the range of . By doing so, it is possible to obtain the necessary passband characteristics with an appropriate amount of attenuation.

In the above embodiments, the A/D conversion was explained as operating at twice the sampling frequency f8, but the conversion speed could be set to four times the sampling frequency f8, that is, 2n (n
= 1.2,...) times.

In addition, the dither generation circuit 9 is connected to the CMO3) range inverter A and the CMO8h range inverter A3.
Although the explanation has been made in terms of stages, the number may be one or more depending on the amplification degree of the CMOS transistor inverter.

1 2 Furthermore, the effects of the present invention will not change even if the sampling frequency f8 is not limited to the above-mentioned 48 KH, but may also be set to 32 KH, 44, or 1 KH2z.

In addition, the present invention can be used not only for A/D conversion but also for reducing quantization noise that occurs during D/A conversion. In that case, the dither signal S (analog dither) of the dither generation circuit 9 according to the present invention is provided before the D/A converter.
The configuration may be such that it is A/D converted and inputted.

〔Effect of the invention〕

As described above, according to the present invention, since the dither signal is generated using a CMOS transistor inverter, the time and effort required to adjust the signal level of the dither signal is simplified, and the device can be miniaturized.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is an electric circuit diagram of a dither generation circuit, Fig. 3 is an explanatory diagram of the amplification action of a CMOS transistor inverter, Fig. 4 is a characteristic diagram of each filter, FIG. 5 is a block diagram showing an example of a conventional dither circuit. 1... Input terminal 2... Adder 3... Low pass filter 4... Sample hold circuit 5... A/D conversion circuit 6... Digital filter 7... Dither generation circuit 8...・Band pass filter 9...Dither generation circuit AI...Operational amplifier A2...CMOS transistor inverter A3...
CMOS transistor inverter C1C1C3...Coupling capacitor 2 R3...Resistors R, R, R6...Feedback resistor 5 R4...Gain setting resistor 3 ZD...Zener diode SIN...Input analog signal S ・... Output digital signal UT S, ... Dither signal QPI ... PMOS transistor QN1 ... NMOS transistor QP2 ... PMO3) Transistor QN2 ... NMO3) Transistor D ... Drain S ... Source G ...Gate ■DD...High potential side power supply v88...Low potential side power supply a, c...Input terminal S, d...Output terminal

Claims (1)

[Claims] In a dither circuit that adds a dither signal to an input signal of an A/D conversion circuit, an input terminal is connected to a low potential power supply voltage in an alternating current manner, and
C whose output terminal is connected to the input stage of the A/D conversion circuit
A dither circuit comprising a dither generation circuit made of a MOS transistor inverter.