JP2948848B2 - Dither circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dither circuit used to suppress quantization noise generated at the time of A / D conversion of a signal.

[Conventional technology]

A PCM (Pulse Code Modulation) recording device such as a DAT (Digital Audio Tape Recorder) uses an A / D converter to convert an input analog signal into a digital signal.
A conversion circuit is used. In the A / D conversion circuit, generation of quantization noise poses a problem. The quantization noise has a strong correlation with the input analog signal, and causes high-order harmonic distortion of the input analog signal. This distortion is mixed in the recorded signal and appears as an unpleasant unpleasant sound when the recorded signal is reproduced. A dither circuit is used to suppress the quantization noise. The dither circuit adds a random noise dither signal to an input analog signal at an input stage of the A / D conversion circuit to whiten quantization noise having periodicity.

FIG. 5 shows a conventional dither circuit. In FIG. 5, an input analog signal S _IN from a line amplifier (not shown) is input to an input terminal 1. The input analog signal S _IN is given to the adder 2, where the input analog signal S
The dither signal _SD from the dither generation circuit 7 is added to _IN .
The dither generation circuit 7 has a Zener diode ZD as a dither signal _SD generation source. It applied to the non-inverting input terminal of the operational amplifier A ₁ thermal noise generated by passing a current through the resistor R ₃ in the zener diode ZD via a coupling capacitor C _1. Operational amplifier A ₁ is amplified by a gain determined the input noise by gain setting resistors R _4, and outputs the band-pass filter 8 via a coupling capacitor C ₂ noise signal amplified as a dither signal S _D.
The band-pass filter 8 performs a band limitation outputs a dither signal S _D to the adder 2 for the dither signal S _D. Input analog signal to which the dither signal _SD is added in the adder 2
S _IN is input to the low-pass filter 3. The low-pass filter 3 removes unnecessary signals above the upper limit of the reproduction frequency band of the input analog signal _SIN and sends the same to the sample-and-hold circuit 4. Sample-and-hold circuit 4, the sample of the input analog signal S _IN was sampled at a predetermined sampling frequency f _S, A / D in the conversion circuit 5 by the time required to quantize the input analog signal S _IN that varies continuously Hold the value. The sampled input analog signal S _IN is input to the A / D conversion circuit 5. The A / D conversion circuit 5 quantizes each sample value of the input analog signal S _IN according to the value, converts it into a digital signal, and outputs it to the digital filter 6.
The digital filter 6 filters digital data, removes unnecessary components including the dither signal _SD , and outputs the result.

[Problems to be solved by the invention]

In the above conventional dither circuit, the dither generation circuit 7 uses a Zener diode ZD,
The thermal noise generated from ZD has a structure for amplifying output by the operational amplifier A _1. However, Zener diode ZD
Are not necessarily uniform and vary. Therefore, it is necessary to adjust the signal level of the dither signal _SD according to the variation. Further, in order to use an operational amplifier A _1, a problem such as increasing costs.

An object of the present invention is to provide a dither circuit that can generate a dither signal with a relatively simple configuration.

[Means for solving the problem]

In order to solve the above problem, the present invention provides a dither circuit for adding a dither signal to an input signal of an A / D conversion circuit. C that is set in the linear operation area and whose output terminal is connected to the input stage of the A / D conversion circuit
A dither generation circuit composed of a MOS transistor inverter is provided.

[Action]

According to the present invention, since the input terminal of the CMOS transistor inverter is AC grounded and the bias point is set in the linear operation region, the white noise generated by the CMOS transistor inverter itself causes the amplification effect of the CMOS transistor inverter itself. To a predetermined voltage level.
The amplified noise signal is output as a dither signal,
It is added to the input analog signal that is the input signal of the A / D conversion circuit. In other words, the CMOS transistor inverter utilizes the fact that it operates as a high-impedance linear amplifier in its linear operation region.
By using a CMOS-IC with little variation in characteristics between devices, it is possible to obtain a uniform dither signal _{SD and} to reduce the size of the device.

〔Example〕

Next, a preferred embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In Figure 1, the input analog signal S _IN from the line amplifier (not shown) is inputted to the input terminal 1. The adder 2 adds the dither signal S _D from the dither generating circuit 9 to the input analog signal S _IN. The adder 2 is configured using an operational amplifier or the like. The input analog signal S _IN to which the dither signal _SD has been added is input to the low-pass filter 3. The low-pass filter 3 is composed of an active analog low-pass filter using an operational amplifier, and has an attenuation characteristic as shown in FIG. 4 to remove unnecessary high frequency components. The input analog signal S _IN output from the low-pass filter 3 is input to the sample and hold circuit 4. Sample-and-hold circuit 4 is input analog signal S _IN to a predetermined sampling frequency f _S (e.g., 48KHz) n times (e.g., twice) of sampled by the over-sampling, the sample value A / D converter circuit 5
And hold it for the time required for the A / D conversion time and give it to the A / D conversion circuit 5. The A / D conversion circuit 5 quantizes the input sample value, converts it into a digital signal, and outputs it. Converted digital signal is taken out at the sampling frequency f _S or oversampling frequency nf _S, unnecessary components are output are removed. The output digital signal S _OUT is
It is sent to the DAT recording unit.

As shown in FIG. 2, the dither generation circuit 9 has two stages of CMs.
It is configured using an OS transistor inverter A ₂ and a CMOS transistor inverter A ₃ . CMOS transistor inverter A ₂ of the first stage acts as a white noise source and an amplifier, a CMOS transistor inverter A ₃ is amplified to a further predetermined level the generated white noise, band-pass the amplified signal as the dither signal S _D It functions as an amplifier that outputs to the filter 8. CMOS transistor input terminal a of the inverter A ₂ is the low potential side power source V _SS via the coupling capacitor C ₃ (or, GND) is connected to the output terminal b of a CMOS transistor inverter A ₂ are CMOS transistor inverter A ₃ Is connected to the input terminal c. Output terminal d of the CMOS transistor inverter A ₃ is connected to the input terminal of the bandpass filter 8. Between the input terminal a and the output terminal b is feedback resistor R ₅ of the high resistance, the feedback resistor R ₆ is similarly high resistance between the input terminal c to the output terminal d are connected.

CMOS transistor inverter A ₂ is, PMOS transistor
_QP1 and an NMOS transistor _QN1 . Similarly, CMOS transistor inverter A ₃ is a PMOS transistor Q _P2 and the NMOS transistor Q _N2. The gate G of the gate G of the NMOS transistor Q _N1 of the PMOS transistor Q _P1 is mutually connected together to form an input terminal a. The output terminal b is provided to the connection point of the D source S of the NMOS transistor Q _N1 of the PMOS transistor Q _P1. The input terminal c is provided at a common connection point between the gate G of the PMOS transistor _{QP2 and} the gate G of the NMOS transistor _QN2 . Drain D of the source S and the NMOS transistor Q _N2 of the output terminal d is PMOS transistor Q _P2
Is provided at the connection point. The drain D of the PMOS transistor Q _P1 higher voltage power supply V _DD, higher voltage power supply V _DD is applied also similarly to the drain D of the PMOS transistor Q _P2. Source S of NMOS transistor Q _N1 Low-side power supply V
_SS (or GND) and the source S of the NMOS transistor _QN2 are also connected to the low-potential-side power supply V _SS (GND).

The above CMOS transistor inverters A ₂ and A ₃ are usually
Although used as a logic gate, this embodiment uses it as a high impedance linear amplifier. Third
The figure shows the transfer curves of the CMOS transistor inverter A ₂ and the CMOS transistor inverter A ₃ . As can be seen from FIG. 3, the CMOS transistor inverters A ₂ and A ₃
Each has a linear region in a region where the logical output transitions from the “H” level to the “L” level. By setting a bias point at point B of V _DD / 2 in this linear region, CMOS transistor inverters A ₂ and A ₃ operate as linear amplifiers. And
An input terminal a of the CMOS transistor inverter A ₂ via the coupling capacitor C ₃ low potential side power supply V _SS (or, G
By connecting to the ND) amplification, CMOS transistor input voltage of the inverter A ₂ are AC-0V, and only this time the internal noise generated from the CMOS transistor inverter A ₂ itself (white noise) by CMOS transistors inverter A ₂ Is done. This amplification gain is approximately 20dB when V _DD = 5V
It is. The amplified white noise is output from the output terminal b to the input terminal c.

CMOS transistor inverter A ₃ is further amplifies the inputted white noise (20 dB), output from the output terminal d. The amplified white noise is sent to the band pass filter 8 as a dither signal _SD .

The reason for the existence of the bandpass filter 8 is based on the relationship with the attenuation characteristics of the lowpass filter 3. That is, the band-pass filter 8 has a pass band determined by the center frequency thereof and limits the frequency band of the dither signal _SD . The center frequency f ₀ has a relationship with the sampling frequency f _S. Is preferably in the range. However, if the center frequency f ₀ is set to the higher frequency side, the signal level of the dither signal _SD will decrease due to the attenuation characteristics of the low-pass filter 3. In order to prevent this, it is necessary to re-amplify. However, excessively increasing the signal level of the dither signal _SD causes problems such as beats. Therefore, as shown in FIG. 4, the level attenuated by 40 dB from the passband level L
Let the frequency corresponding to the point of L _{M be} f _M and the center frequency f ₀ be To be set in the range. By doing so, it is possible to obtain necessary passband characteristics with an appropriate amount of attenuation.

In the above embodiment has been described as operating at twice the speed of the sampling frequency f _S in the A / D converter, 4 times, etc. The conversion rate, i.e. the f _S 2n (n = 1,
2,...).

Further, the dither generation circuit 9 has been described as having two stages of the CMOS transistor inverter A ₂ and the CMOS transistor inverter A _3. However, one or a plurality of dither generation circuits 9 may be provided according to the amplification degree of the CMOS transistor inverter.

Further, the sampling frequency f _S is not above 48KH _Z only, 32KH _Z, no changes to the effect of the invention to use a 44.1KH _Z.

In addition, the present invention can be used not only for A / D conversion, but also for reducing quantization noise generated during D / A conversion. In that case, the dither signal S _D (analog dither) of the dither generation circuit 9 according to the present invention is supplied to the A / D converter before the D / A converter.
What is necessary is just to comprise so that it may convert and input.

〔The invention's effect〕

As described above, according to the present invention, since the dither signal is generated by using the CMOS transistor inverter, the trouble of adjusting the signal level of the dither signal is simplified,
The size of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an electric circuit diagram of a dither generation circuit, FIG. 3 is an explanatory diagram of an amplifying operation of a CMOS transistor inverter, FIG. FIG. 5 is a block diagram showing an example of a conventional dither circuit. DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Adder 3 ... Low pass filter 4 ... Sample hold circuit 5 ... A / D conversion circuit 6 ... Digital filter 7 ... Dither generation circuit 8 ... Band pass filter 9 ... Dither Generating circuit A ₁ …… Op amp A ₂ …… CMOS transistor inverter A ₃ …… CMOS transistor inverter C ₁ , C ₂ , C ₃ … Coupling capacitor R ₃ …… Resistance R ₂ , R ₅ , R ₆ …… Feedback Resistance R ₄ … Gain setting resistance ZD… Zener diode S _IN … Input analog signal S _OUT … Output digital signal S _D … Dither signal Q _P1 … PMOS transistor Q _N1 … NMOS transistor Q _P2 … PMOS Transistor Q _N2 … NMOS transistor D… Drain S… Source G… Gate V _DD … High-potential power supply V _SS … Low-potential power supply a, c… Input terminals b, d… Output Terminal

Claims (1)

(57) [Claims] In a dither circuit for adding a dither signal to an input signal of an A / D conversion circuit, an input terminal is AC-connected to a low-potential power supply voltage, and a bias point thereof is set in a linear operation region. And an output terminal connected to the input stage of the A / D conversion circuit.
A dither circuit comprising a dither generation circuit comprising a MOS transistor inverter.