JPH03192744A - Structure for mounting semiconductor device - Google Patents

Structure for mounting semiconductor device

Info

Publication number
JPH03192744A
JPH03192744A JP1333408A JP33340889A JPH03192744A JP H03192744 A JPH03192744 A JP H03192744A JP 1333408 A JP1333408 A JP 1333408A JP 33340889 A JP33340889 A JP 33340889A JP H03192744 A JPH03192744 A JP H03192744A
Authority
JP
Japan
Prior art keywords
board
semiconductor device
wire
mounting
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1333408A
Other languages
Japanese (ja)
Inventor
Hiroshi Saito
宏 斉藤
Shigenari Takami
茂成 高見
Jiro Hashizume
二郎 橋爪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1333408A priority Critical patent/JPH03192744A/en
Publication of JPH03192744A publication Critical patent/JPH03192744A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Abstract

PURPOSE:To make it possible to make low the mounting height of a semiconductor device and moreover, to make it possible to make small the mounting area of the device by a method wherein wires having a length of a dimension almost identical with the thickness of a mounting board are formed at positions to correspond to pads and are respectively inserted in through holes connected with inner leads on the board. CONSTITUTION:Wires 12 are almost vertically bonded on aluminium pads 11 on a semiconductor device 10 and the length of the wires 12 is cut into a dimension almost identical with the thickness of a mounting board 13. These wires 12 are respectively inserted in through holes 14 formed in the board 13, are fixed with a conductive paste (a bonding agent) 15 and at the same time, are electrically connected with the pads 11. The holes 14 are respectively connected with inner leads 16 formed on the board 13. By inserting the wires 12 in the holes 14 in the board 13 in such a way, the mounting height of the device 10 can be made low. Moreover, as a second wire bonding on the inner leads is also unnecessary, the space of the board 13 which is positioned under the lower part of the device 10 can be effectively put to practical use and the mounting area of the device can, be made small.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置の実装構造に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a mounting structure for a semiconductor device.

〔従来の技術］ 第４図は従来例を示すもので、基板１上にペーストなど
の接着剤２を介してグイボンドされた半導体装置３のア
ルミニウム・パッド４と、基板１上のインナーリード５
とは、金（Ａｕ）等のワイヤ６でワイヤボンディングさ
れている。[Prior Art] FIG. 4 shows a conventional example, in which an aluminum pad 4 of a semiconductor device 3 is bonded onto a substrate 1 via an adhesive 2 such as paste, and an inner lead 5 on the substrate 1.
is wire-bonded with a wire 6 made of gold (Au) or the like.

［発明が解決しようとする課題〕 しかしながら、上述の如きワイヤボンディングの場合、
ワイヤループが有るため、実装高さが高くなり、装置の
薄型化を阻害する要因となっている。また、インナーリ
ード５の先端に、セカンド・ワイヤボンディングを行う
ためのパッド７を設けなければならず、実装面積が大き
くなり、小型化できないという欠点が有る。[Problem to be solved by the invention] However, in the case of wire bonding as described above,
The presence of the wire loop increases the mounting height, which is a factor that prevents the device from being made thinner. Furthermore, it is necessary to provide a pad 7 at the tip of the inner lead 5 for second wire bonding, which increases the mounting area and has the disadvantage that miniaturization is not possible.

本発明は、上記欠点に鑑みなされたもので、その目的と
するところは、半導体装置の実装高さを低くでき、しか
も、実装面積を小さくできる半導体装置の実装構造を提
供することにある。The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a mounting structure for a semiconductor device that can reduce the mounting height of the semiconductor device and also reduce the mounting area.

［課題を解決するための手段］ 本発明に係る実装構造は、半導体装置のパッドに略垂直
にボンディングされ、実装基板の板厚と略同寸法の長さ
を有するワイヤを、前記パッドに対応する位置に形成さ
れ、前記基板上のインナーリードと接続されたスルーホ
ールに挿入するとともに、前記ワイヤを導電性接着剤を
介して前記スルーホールに電気的接続したことを特徴と
するものである。[Means for Solving the Problems] A mounting structure according to the present invention includes a wire that is bonded substantially perpendicularly to a pad of a semiconductor device and has a length that is substantially the same as the thickness of a mounting board, and is bonded to a pad of a semiconductor device in a manner corresponding to the pad. The wire is inserted into a through hole formed at a position connected to an inner lead on the substrate, and the wire is electrically connected to the through hole via a conductive adhesive.

［実施例］ 第１図は本発明の一実施例を示すもので、半導体装置１
０のアルミニウム・パッド１１には金または銅のワイヤ
１２が略垂直にボンディングされており、ワイヤ１２の
長さは後述の実装基板１３の板厚と略同寸法に切断され
ている。このワイヤ１２は、ガラスエポキシ等のプラス
チック系あるいはアルミナ等のセラミック系材料より成
る実装基板１３に形成されたスルーホール１４に挿入さ
れ、導電性ペースト（接着剤）１５で固定されるととも
に、電気的に接続されている。また、スルーホール１４
は、基板１３上に形成されたインナーリード１６と接続
されている。[Embodiment] FIG. 1 shows an embodiment of the present invention, in which a semiconductor device 1
A gold or copper wire 12 is bonded approximately perpendicularly to the aluminum pad 11 of No. 0, and the length of the wire 12 is cut to approximately the same dimension as the thickness of a mounting board 13, which will be described later. This wire 12 is inserted into a through hole 14 formed in a mounting board 13 made of a plastic material such as glass epoxy or a ceramic material such as alumina, fixed with a conductive paste (adhesive) 15, and electrically connected. It is connected to the. Also, through hole 14
are connected to inner leads 16 formed on the substrate 13.

ここで、導電性ペースト１５は粘性の高いものが好まし
く、基板１３がプラスチック系であれば、硬化温度の低
い（約１５０℃）ものが好ましい。なお、スルーホール
１４の位置は上記パッド１１の位置に対応して形成され
ることは言うまでもないことである。また、半導体装置
１０の荷重がワイヤ１２に加わらないように、半導体装
置１０と基板１３は、パッド１１部分を除外して、絶縁
性接着剤１７等で接着されている。Here, the conductive paste 15 preferably has high viscosity, and if the substrate 13 is made of plastic, it preferably has a low curing temperature (approximately 150° C.). It goes without saying that the position of the through hole 14 is formed corresponding to the position of the pad 11. Further, the semiconductor device 10 and the substrate 13 are bonded together with an insulating adhesive 17 or the like, except for the pad 11 portion, so that the load of the semiconductor device 10 is not applied to the wire 12.

次に、ワイヤ１２をスルーホール１４に挿入する方法に
ついて説明する。第２図に示すものはエアー吸引装置を
使用するもので、エアー吸引装置１８は、例えば真空ポ
ンプであり、基板１３の裏面から半導体装置ＩＯにボン
ディングされたワイヤ１２を吸引する。このとき、ワイ
ヤ１２の先端に樹脂等の錘１９を付着すれば、ワイヤ１
２が乱流に流されることな（吸引できる。また、第３図
に示すものは磁石を用いるもので、磁石２０による挿入
方法では、ワイヤ１２の先端に帯磁性樹脂（例えば鉄粉
等を混入したペースＩ−）２１を付着し、この磁性を利
用して基板１３の裏面から磁石２０によりワイヤ１２を
吸引する。Next, a method for inserting the wire 12 into the through hole 14 will be explained. The device shown in FIG. 2 uses an air suction device, and the air suction device 18 is, for example, a vacuum pump, and sucks the wire 12 bonded to the semiconductor device IO from the back surface of the substrate 13. At this time, if a weight 19 made of resin or the like is attached to the tip of the wire 12, the wire 12
In addition, the wire 12 shown in FIG. 3 uses a magnet, and in the insertion method using the magnet 20, the tip of the wire 12 is mixed with magnetic resin (for example, iron powder). Then, the wire 12 is attracted by the magnet 20 from the back surface of the substrate 13 using this magnetism.

このように、ワイヤ１２を基板１３のスルーホール１４
に挿入することにより、実装高さを極めて低くすること
ができる。また、従来のようなインナーリードのセカン
ド・ワイヤボンディングも不要であるため、半導体装置
１０の下方に位置する基板１３のスペースが有効に活用
でき、小面積化できる。従って、非常に薄型化・小型化
が要求されるような商品、例えば、ＩＣカードや液晶テ
レビ、電卓等に用いれば極めて効果的である。In this way, the wire 12 is connected to the through hole 14 of the board 13.
By inserting it into the holder, the mounting height can be made extremely low. Further, since there is no need for second wire bonding of the inner leads as in the conventional case, the space of the substrate 13 located below the semiconductor device 10 can be effectively utilized and the area can be reduced. Therefore, it is extremely effective when used in products that require extremely thin and compact size, such as IC cards, liquid crystal televisions, and calculators.

また、半導体装置１０にボンディングされたワイヤ１２
は、スルーホール１４内で導電性ペースト１５で固定さ
れるが、このとき導電性ペースト１５は低温（約１５０
°Ｃ）で硬化させるため、熱的な影響をほとんど与えず
、安価なプラスチック系基板１３を使用することができ
、製造コストを低減できる。Further, the wire 12 bonded to the semiconductor device 10
is fixed in the through hole 14 with conductive paste 15, but at this time, the conductive paste 15 is kept at a low temperature (approximately 150
C), there is almost no thermal influence, and an inexpensive plastic substrate 13 can be used, reducing manufacturing costs.

さらに、半導体装置１０と、素材の異なる基板１３との
間で、熱膨張率の差から発生する応力はワイヤ１２の弾
力により吸収される。従って、熱的ストレスに強く、広
範囲の温度での使用が可能となる。Further, the stress generated due to the difference in coefficient of thermal expansion between the semiconductor device 10 and the substrate 13 made of different materials is absorbed by the elasticity of the wire 12. Therefore, it is resistant to thermal stress and can be used in a wide range of temperatures.

基板１３上の回路パターンと接続するために設ける半導
体装置１０上の電極は、ワイヤボンディングにより容易
に形成でき、半導体装置に電極バンブを作成するフリッ
プチップや、インナーリードの先端に電極バンブを作成
するＴＡＢ　（テープ・オートメーテツド・ボンディン
グ）などのように、バンブを作成する複雑な工程が不要
となる。The electrodes on the semiconductor device 10 that are provided for connection to the circuit pattern on the substrate 13 can be easily formed by wire bonding, such as flip-chip to create electrode bumps on the semiconductor device or electrode bumps to be created at the tips of inner leads. A complicated process for creating bumps, such as TAB (tape automated bonding), becomes unnecessary.

従って、大幅な工程の簡易化が図れる。Therefore, the process can be significantly simplified.

また、基板１３上に接合された半導体装置１０をリペア
する場合、導電性ペースト１５を溶剤で溶解することに
より容易に基板１３から分離できる。従って、半導体装
置１０のリペアは容易で、基板１３は半永久的に使用で
きる。Further, when repairing the semiconductor device 10 bonded on the substrate 13, it can be easily separated from the substrate 13 by dissolving the conductive paste 15 with a solvent. Therefore, repair of the semiconductor device 10 is easy, and the substrate 13 can be used semi-permanently.

［発明の効果］ 本発明に係る半導体装置の実装構造は、上記のように、
半導体装置のパッドに略垂直にボンディングされ、実装
基板の板厚と略同寸法の長さを有するワイヤを、前記パ
ッドに対応する位置に形成され、前記基板上のインナー
リードと接続されたスルーホールに挿入するとともに、
前記ワイヤを導電性接着剤を介して前記スルーホールに
電気的接続してなるので、半導体装置の実装高さを低く
でき、しかも、実装面積を小さくできるという効果があ
る。[Effects of the Invention] As described above, the mounting structure of the semiconductor device according to the present invention has the following features.
A wire bonded approximately perpendicularly to the pad of the semiconductor device and having a length approximately the same as the board thickness of the mounting board is formed at a position corresponding to the pad and connected to an inner lead on the board through a through hole. and insert it into
Since the wire is electrically connected to the through hole via a conductive adhesive, the mounting height of the semiconductor device can be lowered, and the mounting area can also be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す断面図、第２図及び第
３図はそれぞれ本発明に係る実装方法を示す簡略図、第
４図は従来例を示すもので、（ａ）は側面図、（ロ）は
平面図である。 １０・・・半導体装置、１１・・・パッド、１２・・・
ワイヤ、１３・・・実装基板、１４・・・スルーホール
、１５・・・導電性接着剤、１６・・・インナーリード
、１７・・・絶縁性接着剤。FIG. 1 is a cross-sectional view showing an embodiment of the present invention, FIGS. 2 and 3 are simplified diagrams showing the mounting method according to the present invention, and FIG. 4 shows a conventional example. A side view, and (b) a plan view. 10... Semiconductor device, 11... Pad, 12...
Wire, 13... Mounting board, 14... Through hole, 15... Conductive adhesive, 16... Inner lead, 17... Insulating adhesive.

Claims (1)

【特許請求の範囲】[Claims] （１）半導体装置のパッドに略垂直にボンディングされ
、実装基板の板厚と略同寸法の長さを有するワイヤを、
前記パッドに対応する位置に形成され、前記基板上のイ
ンナーリードと接続されたスルーホールに挿入するとと
もに、前記ワイヤを導電性接着剤を介して前記スルーホ
ールに電気的接続してなる半導体装置の実装構造。(1) A wire that is bonded approximately perpendicularly to the pad of the semiconductor device and has a length that is approximately the same as the thickness of the mounting board,
The semiconductor device is formed by inserting the wire into a through hole formed at a position corresponding to the pad and connected to an inner lead on the substrate, and electrically connecting the wire to the through hole via a conductive adhesive. Implementation structure.
JP1333408A 1989-12-21 1989-12-21 Structure for mounting semiconductor device Pending JPH03192744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1333408A JPH03192744A (en) 1989-12-21 1989-12-21 Structure for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1333408A JPH03192744A (en) 1989-12-21 1989-12-21 Structure for mounting semiconductor device

Publications (1)

Publication Number Publication Date
JPH03192744A true JPH03192744A (en) 1991-08-22

Family

ID=18265780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1333408A Pending JPH03192744A (en) 1989-12-21 1989-12-21 Structure for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JPH03192744A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277825A (en) * 2007-04-26 2008-11-13 Infineon Technologies Ag Chip module, and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277825A (en) * 2007-04-26 2008-11-13 Infineon Technologies Ag Chip module, and manufacturing method thereof

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